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30 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32l1xx_hal_gpio.c |
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4 | * @author MCD Application Team |
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5 | * @brief GPIO HAL module driver. |
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50 | mjames | 6 | * This file provides firmware functions to manage the following |
30 | mjames | 7 | * functionalities of the General Purpose Input/Output (GPIO) peripheral: |
8 | * + Initialization and de-initialization functions |
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9 | * + IO operation functions |
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50 | mjames | 10 | * |
30 | mjames | 11 | @verbatim |
12 | ============================================================================== |
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13 | ##### GPIO Peripheral features ##### |
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50 | mjames | 14 | ============================================================================== |
15 | [..] |
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16 | Each port bit of the general-purpose I/O (GPIO) ports can be individually |
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30 | mjames | 17 | configured by software in several modes: |
50 | mjames | 18 | (+) Input mode |
30 | mjames | 19 | (+) Analog mode |
20 | (+) Output mode |
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21 | (+) Alternate function mode |
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22 | (+) External interrupt/event lines |
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50 | mjames | 23 | |
24 | [..] |
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25 | During and just after reset, the alternate functions and external interrupt |
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30 | mjames | 26 | lines are not active and the I/O ports are configured in input floating mode. |
50 | mjames | 27 | |
28 | [..] |
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29 | All GPIO pins have weak internal pull-up and pull-down resistors, which can be |
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30 | mjames | 30 | activated or not. |
31 | |||
32 | [..] |
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33 | In Output or Alternate mode, each IO can be configured on open-drain or push-pull |
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34 | type and the IO speed can be selected depending on the VDD value. |
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50 | mjames | 35 | |
30 | mjames | 36 | [..] |
50 | mjames | 37 | The microcontroller IO pins are connected to onboard peripherals/modules through a |
38 | multiplexer that allows only one peripheral s alternate function (AF) connected |
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39 | to an IO pin at a time. In this way, there can be no conflict between peripherals |
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40 | sharing the same IO pin. |
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41 | |||
42 | [..] |
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43 | All ports have external interrupt/event capability. To use external interrupt |
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44 | lines, the port must be configured in input mode. All available GPIO pins are |
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30 | mjames | 45 | connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. |
50 | mjames | 46 | |
47 | [..] |
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48 | The external interrupt/event controller consists of up to 28 edge detectors |
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30 | mjames | 49 | (depending on products 16 lines are connected to GPIO) for generating event/interrupt |
50 | mjames | 50 | requests (each input line can be independently configured to select the type |
51 | (interrupt or event) and the corresponding trigger event (rising or falling or both). |
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52 | Each line can also be masked independently. |
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53 | |||
30 | mjames | 54 | ##### How to use this driver ##### |
50 | mjames | 55 | ============================================================================== |
30 | mjames | 56 | [..] |
50 | mjames | 57 | (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE(). |
58 | |||
30 | mjames | 59 | (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). |
60 | (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure |
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50 | mjames | 61 | (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef |
30 | mjames | 62 | structure. |
50 | mjames | 63 | (++) In case of Output or alternate function mode selection: the speed is |
64 | configured through "Speed" member from GPIO_InitTypeDef structure, |
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30 | mjames | 65 | the speed is configurable: Low, Medium and High. |
66 | (++) If alternate mode is selected, the alternate function connected to the IO |
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67 | is configured through "Alternate" member from GPIO_InitTypeDef structure |
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50 | mjames | 68 | (++) Analog mode is required when a pin is to be used as ADC channel |
30 | mjames | 69 | or DAC output. |
50 | mjames | 70 | (++) In case of external interrupt/event selection the "Mode" member from |
71 | GPIO_InitTypeDef structure select the type (interrupt or event) and |
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30 | mjames | 72 | the corresponding trigger event (rising or falling or both). |
50 | mjames | 73 | |
74 | (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority |
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30 | mjames | 75 | mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using |
76 | HAL_NVIC_EnableIRQ(). |
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50 | mjames | 77 | |
78 | (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also |
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79 | recommended to use it to unconfigure pin which was used as an external interrupt |
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80 | or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG |
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30 | mjames | 81 | registers. |
50 | mjames | 82 | |
30 | mjames | 83 | (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). |
50 | mjames | 84 | |
85 | (#) To set/reset the level of a pin configured in output mode use |
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30 | mjames | 86 | HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). |
50 | mjames | 87 | |
30 | mjames | 88 | (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). |
50 | mjames | 89 | |
90 | (#) During and just after reset, the alternate functions are not |
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30 | mjames | 91 | active and the GPIO pins are configured in input floating mode (except JTAG |
92 | pins). |
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50 | mjames | 93 | |
94 | (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose |
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95 | (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has |
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30 | mjames | 96 | priority over the GPIO function. |
50 | mjames | 97 | |
98 | (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as |
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99 | general purpose PH0 and PH1, respectively, when the HSE oscillator is off. |
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30 | mjames | 100 | The HSE has priority over the GPIO function. |
50 | mjames | 101 | |
30 | mjames | 102 | @endverbatim |
103 | ****************************************************************************** |
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104 | * @attention |
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105 | * |
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50 | mjames | 106 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
107 | * All rights reserved.</center></h2> |
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30 | mjames | 108 | * |
50 | mjames | 109 | * This software component is licensed by ST under BSD 3-Clause license, |
110 | * the "License"; You may not use this file except in compliance with the |
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111 | * License. You may obtain a copy of the License at: |
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112 | * opensource.org/licenses/BSD-3-Clause |
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30 | mjames | 113 | * |
50 | mjames | 114 | ****************************************************************************** |
30 | mjames | 115 | */ |
116 | |||
117 | /* Includes ------------------------------------------------------------------*/ |
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118 | #include "stm32l1xx_hal.h" |
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119 | |||
120 | /** @addtogroup STM32L1xx_HAL_Driver |
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121 | * @{ |
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122 | */ |
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123 | |||
124 | /** @addtogroup GPIO |
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125 | * @brief GPIO HAL module driver |
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126 | * @{ |
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127 | */ |
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128 | |||
129 | #ifdef HAL_GPIO_MODULE_ENABLED |
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130 | |||
131 | /* Private typedef -----------------------------------------------------------*/ |
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132 | /* Private define ------------------------------------------------------------*/ |
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133 | /** @addtogroup GPIO_Private_Constants |
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134 | * @{ |
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135 | */ |
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50 | mjames | 136 | #define GPIO_MODE (0x00000003U) |
137 | #define EXTI_MODE (0x10000000U) |
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138 | #define GPIO_MODE_IT (0x00010000U) |
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139 | #define GPIO_MODE_EVT (0x00020000U) |
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140 | #define RISING_EDGE (0x00100000U) |
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141 | #define FALLING_EDGE (0x00200000U) |
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142 | #define GPIO_OUTPUT_TYPE (0x00000010U) |
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30 | mjames | 143 | |
50 | mjames | 144 | #define GPIO_NUMBER (16U) |
145 | |||
30 | mjames | 146 | /** |
147 | * @} |
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148 | */ |
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50 | mjames | 149 | |
30 | mjames | 150 | /* Private macro -------------------------------------------------------------*/ |
151 | /* Private variables ---------------------------------------------------------*/ |
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152 | /* Private function prototypes -----------------------------------------------*/ |
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153 | /* Exported functions ---------------------------------------------------------*/ |
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154 | |||
155 | /** @addtogroup GPIO_Exported_Functions |
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156 | * @{ |
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157 | */ |
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158 | |||
159 | /** @addtogroup GPIO_Exported_Functions_Group1 |
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50 | mjames | 160 | * @brief Initialization and Configuration functions |
30 | mjames | 161 | * |
50 | mjames | 162 | @verbatim |
30 | mjames | 163 | =============================================================================== |
164 | ##### Initialization and Configuration functions ##### |
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165 | =============================================================================== |
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50 | mjames | 166 | |
30 | mjames | 167 | @endverbatim |
168 | * @{ |
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169 | */ |
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170 | |||
171 | /** |
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172 | * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. |
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50 | mjames | 173 | * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices |
174 | * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains |
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30 | mjames | 175 | * the configuration information for the specified GPIO peripheral. |
176 | * @retval None |
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177 | */ |
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178 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) |
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50 | mjames | 179 | { |
30 | mjames | 180 | uint32_t position = 0x00; |
181 | uint32_t iocurrent = 0x00; |
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182 | uint32_t temp = 0x00; |
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183 | |||
184 | /* Check the parameters */ |
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185 | assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); |
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186 | assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); |
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187 | assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); |
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50 | mjames | 188 | assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); |
30 | mjames | 189 | |
190 | /* Configure the port pins */ |
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191 | while (((GPIO_Init->Pin) >> position) != 0) |
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192 | { |
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193 | /* Get current io position */ |
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50 | mjames | 194 | iocurrent = (GPIO_Init->Pin) & (1U << position); |
195 | |||
196 | if (iocurrent) |
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30 | mjames | 197 | { |
198 | /*--------------------- GPIO Mode Configuration ------------------------*/ |
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199 | /* In case of Output or Alternate function mode selection */ |
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200 | if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || |
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201 | (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) |
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202 | { |
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203 | /* Check the Speed parameter */ |
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204 | assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
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205 | /* Configure the IO Speed */ |
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50 | mjames | 206 | temp = GPIOx->OSPEEDR; |
30 | mjames | 207 | CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); |
208 | SET_BIT(temp, GPIO_Init->Speed << (position * 2)); |
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209 | GPIOx->OSPEEDR = temp; |
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210 | |||
211 | /* Configure the IO Output Type */ |
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212 | temp = GPIOx->OTYPER; |
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213 | CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; |
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214 | SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); |
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215 | GPIOx->OTYPER = temp; |
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216 | } |
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217 | |||
218 | /* Activate the Pull-up or Pull down resistor for the current IO */ |
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219 | temp = GPIOx->PUPDR; |
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220 | CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); |
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221 | SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); |
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222 | GPIOx->PUPDR = temp; |
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223 | |||
50 | mjames | 224 | /* In case of Alternate function mode selection */ |
225 | if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) |
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226 | { |
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227 | /* Check the Alternate function parameters */ |
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228 | assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); |
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229 | assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); |
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230 | |||
231 | /* Configure Alternate function mapped with the current IO */ |
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232 | /* Identify AFRL or AFRH register based on IO position*/ |
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233 | temp = GPIOx->AFR[position >> 3]; |
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234 | CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); |
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235 | SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); |
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236 | GPIOx->AFR[position >> 3] = temp; |
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237 | } |
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238 | |||
239 | /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ |
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240 | temp = GPIOx->MODER; |
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241 | CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); |
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242 | SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); |
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243 | GPIOx->MODER = temp; |
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244 | |||
30 | mjames | 245 | /*--------------------- EXTI Mode Configuration ------------------------*/ |
246 | /* Configure the External Interrupt or event for the current IO */ |
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50 | mjames | 247 | if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) |
30 | mjames | 248 | { |
249 | /* Enable SYSCFG Clock */ |
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250 | __HAL_RCC_SYSCFG_CLK_ENABLE(); |
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50 | mjames | 251 | |
30 | mjames | 252 | temp = SYSCFG->EXTICR[position >> 2]; |
50 | mjames | 253 | CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); |
30 | mjames | 254 | SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); |
255 | SYSCFG->EXTICR[position >> 2] = temp; |
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50 | mjames | 256 | |
30 | mjames | 257 | /* Clear EXTI line configuration */ |
258 | temp = EXTI->IMR; |
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259 | CLEAR_BIT(temp, (uint32_t)iocurrent); |
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50 | mjames | 260 | if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) |
30 | mjames | 261 | { |
50 | mjames | 262 | SET_BIT(temp, iocurrent); |
30 | mjames | 263 | } |
264 | EXTI->IMR = temp; |
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265 | |||
266 | temp = EXTI->EMR; |
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50 | mjames | 267 | CLEAR_BIT(temp, (uint32_t)iocurrent); |
268 | if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) |
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30 | mjames | 269 | { |
50 | mjames | 270 | SET_BIT(temp, iocurrent); |
30 | mjames | 271 | } |
272 | EXTI->EMR = temp; |
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50 | mjames | 273 | |
30 | mjames | 274 | /* Clear Rising Falling edge configuration */ |
275 | temp = EXTI->RTSR; |
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50 | mjames | 276 | CLEAR_BIT(temp, (uint32_t)iocurrent); |
277 | if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) |
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30 | mjames | 278 | { |
50 | mjames | 279 | SET_BIT(temp, iocurrent); |
30 | mjames | 280 | } |
281 | EXTI->RTSR = temp; |
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282 | |||
283 | temp = EXTI->FTSR; |
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50 | mjames | 284 | CLEAR_BIT(temp, (uint32_t)iocurrent); |
285 | if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) |
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30 | mjames | 286 | { |
50 | mjames | 287 | SET_BIT(temp, iocurrent); |
30 | mjames | 288 | } |
289 | EXTI->FTSR = temp; |
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290 | } |
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291 | } |
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50 | mjames | 292 | |
30 | mjames | 293 | position++; |
50 | mjames | 294 | } |
30 | mjames | 295 | } |
296 | |||
297 | /** |
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298 | * @brief De-initializes the GPIOx peripheral registers to their default reset values. |
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50 | mjames | 299 | * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices |
300 | * @param GPIO_Pin specifies the port bit to be written. |
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30 | mjames | 301 | * This parameter can be one of GPIO_PIN_x where x can be (0..15). |
302 | * @retval None |
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303 | */ |
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304 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) |
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305 | { |
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306 | uint32_t position = 0x00; |
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307 | uint32_t iocurrent = 0x00; |
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308 | uint32_t tmp = 0x00; |
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309 | |||
310 | /* Check the parameters */ |
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311 | assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); |
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312 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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313 | |||
314 | /* Configure the port pins */ |
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315 | while ((GPIO_Pin >> position) != 0) |
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316 | { |
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317 | /* Get current io position */ |
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50 | mjames | 318 | iocurrent = (GPIO_Pin) & (1U << position); |
30 | mjames | 319 | |
320 | if (iocurrent) |
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321 | { |
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322 | /*------------------------- EXTI Mode Configuration --------------------*/ |
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323 | /* Clear the External Interrupt or Event for the current IO */ |
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50 | mjames | 324 | |
30 | mjames | 325 | tmp = SYSCFG->EXTICR[position >> 2]; |
50 | mjames | 326 | tmp &= ((0x0FU) << (4 * (position & 0x03))); |
327 | if (tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) |
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30 | mjames | 328 | { |
329 | /* Clear EXTI line configuration */ |
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330 | CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); |
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331 | CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); |
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50 | mjames | 332 | |
30 | mjames | 333 | /* Clear Rising Falling edge configuration */ |
334 | CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); |
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335 | CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); |
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50 | mjames | 336 | |
337 | tmp = (0x0FU) << (4 * (position & 0x03)); |
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338 | CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp); |
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30 | mjames | 339 | } |
50 | mjames | 340 | |
341 | /*------------------------- GPIO Mode Configuration --------------------*/ |
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342 | /* Configure IO Direction in Input Floting Mode */ |
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343 | CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2)); |
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344 | |||
345 | /* Configure the default Alternate Function in current IO */ |
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346 | CLEAR_BIT(GPIOx->AFR[position >> 3], 0xFU << ((uint32_t)(position & 0x07U) * 4)) ; |
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347 | /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ |
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348 | CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2)); |
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349 | |||
350 | /* Configure the default value IO Output Type */ |
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351 | CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; |
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352 | |||
353 | /* Configure the default value for IO Speed */ |
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354 | CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); |
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30 | mjames | 355 | } |
50 | mjames | 356 | |
30 | mjames | 357 | position++; |
358 | } |
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359 | } |
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360 | |||
361 | /** |
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362 | * @} |
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363 | */ |
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364 | |||
365 | /** @addtogroup GPIO_Exported_Functions_Group2 |
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366 | * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. |
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367 | * |
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50 | mjames | 368 | @verbatim |
30 | mjames | 369 | =============================================================================== |
370 | ##### IO operation functions ##### |
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50 | mjames | 371 | =============================================================================== |
30 | mjames | 372 | |
373 | @endverbatim |
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374 | * @{ |
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375 | */ |
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376 | |||
377 | /** |
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378 | * @brief Reads the specified input port pin. |
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50 | mjames | 379 | * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices |
380 | * @param GPIO_Pin specifies the port bit to read. |
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30 | mjames | 381 | * This parameter can be GPIO_PIN_x where x can be (0..15). |
382 | * @retval The input port pin value. |
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383 | */ |
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50 | mjames | 384 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) |
30 | mjames | 385 | { |
386 | GPIO_PinState bitstatus; |
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387 | |||
388 | /* Check the parameters */ |
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389 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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390 | |||
391 | if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) |
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392 | { |
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393 | bitstatus = GPIO_PIN_SET; |
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394 | } |
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395 | else |
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396 | { |
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397 | bitstatus = GPIO_PIN_RESET; |
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398 | } |
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399 | return bitstatus; |
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400 | } |
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401 | |||
402 | /** |
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403 | * @brief Sets or clears the selected data port bit. |
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50 | mjames | 404 | * @note This function uses GPIOx_BSRR register to allow atomic read/modify |
30 | mjames | 405 | * accesses. In this way, there is no risk of an IRQ occurring between |
406 | * the read and the modify access. |
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50 | mjames | 407 | * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices |
408 | * @param GPIO_Pin specifies the port bit to be written. |
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30 | mjames | 409 | * This parameter can be one of GPIO_PIN_x where x can be (0..15). |
50 | mjames | 410 | * @param PinState specifies the value to be written to the selected bit. |
30 | mjames | 411 | * This parameter can be one of the GPIO_PinState enum values: |
412 | * @arg GPIO_PIN_RESET: to clear the port pin |
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413 | * @arg GPIO_PIN_SET: to set the port pin |
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414 | * @retval None |
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415 | */ |
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50 | mjames | 416 | void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) |
30 | mjames | 417 | { |
418 | /* Check the parameters */ |
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419 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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420 | assert_param(IS_GPIO_PIN_ACTION(PinState)); |
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421 | |||
422 | if (PinState != GPIO_PIN_RESET) |
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423 | { |
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424 | GPIOx->BSRR = (uint32_t)GPIO_Pin; |
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425 | } |
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426 | else |
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427 | { |
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428 | GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; |
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429 | } |
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430 | } |
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50 | mjames | 431 | |
30 | mjames | 432 | /** |
433 | * @brief Toggles the specified GPIO pin |
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50 | mjames | 434 | * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices |
435 | * @param GPIO_Pin specifies the pins to be toggled. |
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30 | mjames | 436 | * @retval None |
437 | */ |
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50 | mjames | 438 | void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) |
30 | mjames | 439 | { |
50 | mjames | 440 | uint32_t odr; |
441 | |||
30 | mjames | 442 | /* Check the parameters */ |
443 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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444 | |||
50 | mjames | 445 | /* get current Ouput Data Register value */ |
446 | odr = GPIOx->ODR; |
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447 | |||
448 | /* Set selected pins that were at low level, and reset ones that were high */ |
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449 | GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); |
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30 | mjames | 450 | } |
451 | |||
452 | /** |
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453 | * @brief Locks GPIO Pins configuration registers. |
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454 | * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, |
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455 | * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. |
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456 | * @note The configuration of the locked GPIO pins can no longer be modified |
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457 | * until the next reset. |
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458 | * @note Limitation concerning GPIOx_OTYPER: Locking of GPIOx_OTYPER[i] with i = 15..8 |
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459 | * depends from setting of GPIOx_LCKR[i-8] and not from GPIOx_LCKR[i]. |
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460 | * GPIOx_LCKR[i-8] is locking GPIOx_OTYPER[i] together with GPIOx_OTYPER[i-8]. |
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461 | * It is not possible to lock GPIOx_OTYPER[i] with i = 15..8, without locking also |
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462 | * GPIOx_OTYPER[i-8]. |
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463 | * Workaround: When calling HAL_GPIO_LockPin with GPIO_Pin from GPIO_PIN_8 to GPIO_PIN_15, |
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50 | mjames | 464 | * you must call also HAL_GPIO_LockPin with GPIO_Pin - 8. |
465 | * (When locking a pin from GPIO_PIN_8 to GPIO_PIN_15, you must lock also the corresponding |
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30 | mjames | 466 | * GPIO_PIN_0 to GPIO_PIN_7). |
50 | mjames | 467 | * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices |
468 | * @param GPIO_Pin Specifies the port bit to be locked. |
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30 | mjames | 469 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). |
470 | * @retval None |
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471 | */ |
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50 | mjames | 472 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) |
30 | mjames | 473 | { |
474 | __IO uint32_t tmp = GPIO_LCKR_LCKK; |
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475 | |||
476 | /* Check the parameters */ |
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477 | assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); |
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478 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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479 | |||
480 | /* Apply lock key write sequence */ |
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481 | SET_BIT(tmp, GPIO_Pin); |
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482 | /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
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483 | GPIOx->LCKR = tmp; |
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484 | /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ |
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485 | GPIOx->LCKR = GPIO_Pin; |
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486 | /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
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487 | GPIOx->LCKR = tmp; |
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50 | mjames | 488 | /* Read LCKK register. This read is mandatory to complete key lock sequence */ |
30 | mjames | 489 | tmp = GPIOx->LCKR; |
490 | |||
50 | mjames | 491 | /* Read again in order to confirm lock is active */ |
492 | if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) |
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30 | mjames | 493 | { |
494 | return HAL_OK; |
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495 | } |
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496 | else |
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497 | { |
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498 | return HAL_ERROR; |
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499 | } |
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500 | } |
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501 | |||
502 | /** |
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503 | * @brief This function handles EXTI interrupt request. |
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50 | mjames | 504 | * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. |
30 | mjames | 505 | * @retval None |
506 | */ |
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507 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) |
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508 | { |
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509 | /* EXTI line interrupt detected */ |
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50 | mjames | 510 | if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) |
511 | { |
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30 | mjames | 512 | __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); |
513 | HAL_GPIO_EXTI_Callback(GPIO_Pin); |
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514 | } |
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515 | } |
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516 | |||
517 | /** |
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518 | * @brief EXTI line detection callbacks. |
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50 | mjames | 519 | * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. |
30 | mjames | 520 | * @retval None |
521 | */ |
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522 | __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) |
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523 | { |
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524 | /* Prevent unused argument(s) compilation warning */ |
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525 | UNUSED(GPIO_Pin); |
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526 | |||
527 | /* NOTE : This function Should not be modified, when the callback is needed, |
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528 | the HAL_GPIO_EXTI_Callback could be implemented in the user file |
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50 | mjames | 529 | */ |
30 | mjames | 530 | } |
531 | |||
532 | /** |
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533 | * @} |
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534 | */ |
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535 | |||
536 | |||
537 | /** |
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538 | * @} |
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539 | */ |
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540 | |||
541 | #endif /* HAL_GPIO_MODULE_ENABLED */ |
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542 | /** |
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543 | * @} |
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544 | */ |
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545 | |||
546 | /** |
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547 | * @} |
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548 | */ |
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549 | |||
550 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |