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77 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32l1xx_hal_dma.c |
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4 | * @author MCD Application Team |
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5 | * @brief DMA HAL module driver. |
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6 | * This file provides firmware functions to manage the following |
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7 | * functionalities of the Direct Memory Access (DMA) peripheral: |
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8 | * + Initialization and de-initialization functions |
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9 | * + IO operation functions |
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10 | * + Peripheral State and errors functions |
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11 | * |
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12 | ****************************************************************************** |
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13 | * @attention |
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14 | * |
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15 | * Copyright (c) 2017 STMicroelectronics. |
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16 | * All rights reserved. |
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17 | * |
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18 | * This software is licensed under terms that can be found in the LICENSE file |
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19 | * in the root directory of this software component. |
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20 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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21 | * |
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22 | ****************************************************************************** |
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23 | @verbatim |
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24 | ============================================================================== |
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25 | ##### How to use this driver ##### |
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26 | ============================================================================== |
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27 | [..] |
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28 | (#) Enable and configure the peripheral to be connected to the DMA Channel |
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29 | (except for internal SRAM / FLASH memories: no initialization is |
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30 | necessary). Please refer to the Reference manual for connection between peripherals |
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31 | and DMA requests. |
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32 | |||
33 | (#) For a given Channel, program the required configuration through the following parameters: |
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34 | Channel request, Transfer Direction, Source and Destination data formats, |
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35 | Circular or Normal mode, Channel Priority level, Source and Destination Increment mode |
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36 | using HAL_DMA_Init() function. |
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37 | |||
38 | (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error |
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39 | detection. |
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40 | |||
41 | (#) Use HAL_DMA_Abort() function to abort the current transfer |
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42 | |||
43 | -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. |
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44 | *** Polling mode IO operation *** |
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45 | ================================= |
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46 | [..] |
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47 | (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source |
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48 | address and destination address and the Length of data to be transferred |
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49 | (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this |
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50 | case a fixed Timeout can be configured by User depending from his application. |
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51 | |||
52 | *** Interrupt mode IO operation *** |
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53 | =================================== |
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54 | [..] |
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55 | (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() |
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56 | (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() |
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57 | (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of |
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58 | Source address and destination address and the Length of data to be transferred. |
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59 | In this case the DMA interrupt is configured |
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60 | (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine |
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61 | (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can |
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62 | add his own function to register callbacks with HAL_DMA_RegisterCallback(). |
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63 | |||
64 | *** DMA HAL driver macros list *** |
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65 | ============================================= |
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66 | [..] |
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67 | Below the list of macros in DMA HAL driver. |
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68 | |||
69 | (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. |
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70 | (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. |
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71 | (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. |
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72 | (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. |
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73 | (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. |
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74 | (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. |
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75 | (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. |
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76 | |||
77 | [..] |
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78 | (@) You can refer to the DMA HAL driver header file for more useful macros |
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79 | |||
80 | @endverbatim |
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81 | ****************************************************************************** |
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82 | */ |
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83 | |||
84 | /* Includes ------------------------------------------------------------------*/ |
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85 | #include "stm32l1xx_hal.h" |
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86 | |||
87 | /** @addtogroup STM32L1xx_HAL_Driver |
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88 | * @{ |
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89 | */ |
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90 | |||
91 | /** @defgroup DMA DMA |
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92 | * @brief DMA HAL module driver |
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93 | * @{ |
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94 | */ |
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95 | |||
96 | #ifdef HAL_DMA_MODULE_ENABLED |
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97 | |||
98 | /* Private typedef -----------------------------------------------------------*/ |
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99 | /* Private define ------------------------------------------------------------*/ |
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100 | /* Private macro -------------------------------------------------------------*/ |
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101 | /* Private variables ---------------------------------------------------------*/ |
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102 | /* Private function prototypes -----------------------------------------------*/ |
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103 | /** @defgroup DMA_Private_Functions DMA Private Functions |
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104 | * @{ |
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105 | */ |
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106 | |||
107 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
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108 | /** |
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109 | * @} |
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110 | */ |
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111 | |||
112 | /* Exported functions ---------------------------------------------------------*/ |
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113 | |||
114 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
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115 | * @{ |
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116 | */ |
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117 | |||
118 | /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
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119 | * @brief Initialization and de-initialization functions |
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120 | * |
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121 | @verbatim |
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122 | =============================================================================== |
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123 | ##### Initialization and de-initialization functions ##### |
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124 | =============================================================================== |
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125 | [..] |
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126 | This section provides functions allowing to initialize the DMA Channel source |
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127 | and destination addresses, incrementation and data sizes, transfer direction, |
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128 | circular/normal mode selection, memory-to-memory mode selection and Channel priority value. |
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129 | [..] |
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130 | The HAL_DMA_Init() function follows the DMA configuration procedures as described in |
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131 | reference manual. |
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132 | |||
133 | @endverbatim |
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134 | * @{ |
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135 | */ |
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136 | |||
137 | /** |
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138 | * @brief Initialize the DMA according to the specified |
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139 | * parameters in the DMA_InitTypeDef and initialize the associated handle. |
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140 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains |
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141 | * the configuration information for the specified DMA Channel. |
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142 | * @retval HAL status |
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143 | */ |
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144 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) |
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145 | { |
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146 | uint32_t tmp; |
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147 | |||
148 | /* Check the DMA handle allocation */ |
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149 | if(hdma == NULL) |
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150 | { |
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151 | return HAL_ERROR; |
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152 | } |
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153 | |||
154 | /* Check the parameters */ |
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155 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
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156 | assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); |
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157 | assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); |
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158 | assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); |
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159 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
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160 | assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
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161 | assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
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162 | assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
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163 | |||
164 | #if defined (DMA2) |
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165 | /* Compute the channel index */ |
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166 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
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167 | { |
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168 | /* DMA1 */ |
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169 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; |
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170 | hdma->DmaBaseAddress = DMA1; |
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171 | } |
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172 | else |
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173 | { |
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174 | /* DMA2 */ |
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175 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; |
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176 | hdma->DmaBaseAddress = DMA2; |
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177 | } |
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178 | #else |
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179 | /* calculation of the channel index */ |
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180 | /* DMA1 */ |
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181 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; |
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182 | hdma->DmaBaseAddress = DMA1; |
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183 | #endif |
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184 | |||
185 | /* Change DMA peripheral state */ |
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186 | hdma->State = HAL_DMA_STATE_BUSY; |
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187 | |||
188 | /* Get the CR register value */ |
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189 | tmp = hdma->Instance->CCR; |
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190 | |||
191 | /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ |
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192 | tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | |
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193 | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | |
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194 | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); |
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195 | |||
196 | /* Prepare the DMA Channel configuration */ |
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197 | tmp |= hdma->Init.Direction | |
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198 | hdma->Init.PeriphInc | hdma->Init.MemInc | |
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199 | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | |
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200 | hdma->Init.Mode | hdma->Init.Priority; |
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201 | |||
202 | /* Write to DMA Channel CR register */ |
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203 | hdma->Instance->CCR = tmp; |
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204 | |||
205 | /* Initialise the error code */ |
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206 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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207 | |||
208 | /* Initialize the DMA state*/ |
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209 | hdma->State = HAL_DMA_STATE_READY; |
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210 | |||
211 | /* Allocate lock resource and initialize it */ |
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212 | hdma->Lock = HAL_UNLOCKED; |
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213 | |||
214 | return HAL_OK; |
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215 | } |
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216 | |||
217 | /** |
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218 | * @brief DeInitialize the DMA peripheral. |
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219 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
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220 | * the configuration information for the specified DMA Channel. |
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221 | * @retval HAL status |
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222 | */ |
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223 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) |
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224 | { |
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225 | |||
226 | /* Check the DMA handle allocation */ |
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227 | if (NULL == hdma ) |
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228 | { |
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229 | return HAL_ERROR; |
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230 | } |
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231 | |||
232 | /* Check the parameters */ |
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233 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
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234 | |||
235 | /* Disable the selected DMA Channelx */ |
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236 | __HAL_DMA_DISABLE(hdma); |
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237 | |||
238 | #if defined (DMA2) |
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239 | /* Compute the channel index */ |
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240 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
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241 | { |
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242 | /* DMA1 */ |
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243 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; |
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244 | hdma->DmaBaseAddress = DMA1; |
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245 | } |
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246 | else |
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247 | { |
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248 | /* DMA2 */ |
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249 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; |
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250 | hdma->DmaBaseAddress = DMA2; |
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251 | } |
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252 | #else |
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253 | /* calculation of the channel index */ |
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254 | /* DMA1 */ |
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255 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; |
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256 | hdma->DmaBaseAddress = DMA1; |
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257 | #endif |
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258 | |||
259 | /* Reset DMA Channel CR register */ |
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260 | hdma->Instance->CCR = 0U; |
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261 | |||
262 | /* Clear all flags */ |
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263 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); |
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264 | |||
265 | /* Clean callbacks */ |
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266 | hdma->XferCpltCallback = NULL; |
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267 | hdma->XferHalfCpltCallback = NULL; |
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268 | hdma->XferErrorCallback = NULL; |
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269 | hdma->XferAbortCallback = NULL; |
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270 | |||
271 | /* Initialise the error code */ |
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272 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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273 | |||
274 | /* Initialize the DMA state */ |
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275 | hdma->State = HAL_DMA_STATE_RESET; |
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276 | |||
277 | /* Release Lock */ |
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278 | __HAL_UNLOCK(hdma); |
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279 | |||
280 | return HAL_OK; |
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281 | } |
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282 | |||
283 | /** |
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284 | * @} |
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285 | */ |
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286 | |||
287 | /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions |
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288 | * @brief Input and Output operation functions |
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289 | * |
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290 | @verbatim |
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291 | =============================================================================== |
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292 | ##### IO operation functions ##### |
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293 | =============================================================================== |
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294 | [..] This section provides functions allowing to: |
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295 | (+) Configure the source, destination address and data length and Start DMA transfer |
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296 | (+) Configure the source, destination address and data length and |
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297 | Start DMA transfer with interrupt |
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298 | (+) Abort DMA transfer |
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299 | (+) Poll for transfer complete |
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300 | (+) Handle DMA interrupt request |
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301 | |||
302 | @endverbatim |
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303 | * @{ |
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304 | */ |
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305 | |||
306 | /** |
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307 | * @brief Start the DMA Transfer. |
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308 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
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309 | * the configuration information for the specified DMA Channel. |
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310 | * @param SrcAddress The source memory Buffer address |
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311 | * @param DstAddress The destination memory Buffer address |
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312 | * @param DataLength The length of data to be transferred from source to destination |
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313 | * @retval HAL status |
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314 | */ |
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315 | HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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316 | { |
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317 | HAL_StatusTypeDef status = HAL_OK; |
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318 | |||
319 | /* Check the parameters */ |
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320 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
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321 | |||
322 | /* Process locked */ |
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323 | __HAL_LOCK(hdma); |
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324 | |||
325 | if(HAL_DMA_STATE_READY == hdma->State) |
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326 | { |
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327 | /* Change DMA peripheral state */ |
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328 | hdma->State = HAL_DMA_STATE_BUSY; |
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329 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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330 | |||
331 | /* Disable the peripheral */ |
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332 | __HAL_DMA_DISABLE(hdma); |
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333 | |||
334 | /* Configure the source, destination address and the data length & clear flags*/ |
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335 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
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336 | |||
337 | /* Enable the Peripheral */ |
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338 | __HAL_DMA_ENABLE(hdma); |
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339 | } |
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340 | else |
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341 | { |
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342 | /* Process Unlocked */ |
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343 | __HAL_UNLOCK(hdma); |
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344 | status = HAL_BUSY; |
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345 | } |
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346 | return status; |
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347 | } |
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348 | |||
349 | /** |
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350 | * @brief Start the DMA Transfer with interrupt enabled. |
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351 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
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352 | * the configuration information for the specified DMA Channel. |
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353 | * @param SrcAddress The source memory Buffer address |
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354 | * @param DstAddress The destination memory Buffer address |
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355 | * @param DataLength The length of data to be transferred from source to destination |
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356 | * @retval HAL status |
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357 | */ |
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358 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
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359 | { |
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360 | HAL_StatusTypeDef status = HAL_OK; |
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361 | |||
362 | /* Check the parameters */ |
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363 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
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364 | |||
365 | /* Process locked */ |
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366 | __HAL_LOCK(hdma); |
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367 | |||
368 | if(HAL_DMA_STATE_READY == hdma->State) |
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369 | { |
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370 | /* Change DMA peripheral state */ |
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371 | hdma->State = HAL_DMA_STATE_BUSY; |
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372 | hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
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373 | |||
374 | /* Disable the peripheral */ |
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375 | __HAL_DMA_DISABLE(hdma); |
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376 | |||
377 | /* Configure the source, destination address and the data length & clear flags*/ |
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378 | DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
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379 | |||
380 | /* Enable the transfer complete interrupt */ |
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381 | /* Enable the transfer Error interrupt */ |
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382 | if(NULL != hdma->XferHalfCpltCallback ) |
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383 | { |
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384 | /* Enable the Half transfer complete interrupt as well */ |
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385 | __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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386 | } |
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387 | else |
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388 | { |
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389 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
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390 | __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); |
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391 | } |
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392 | |||
393 | /* Enable the Peripheral */ |
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394 | __HAL_DMA_ENABLE(hdma); |
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395 | } |
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396 | else |
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397 | { |
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398 | /* Process Unlocked */ |
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399 | __HAL_UNLOCK(hdma); |
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400 | |||
401 | /* Remain BUSY */ |
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402 | status = HAL_BUSY; |
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403 | } |
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404 | return status; |
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405 | } |
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406 | |||
407 | /** |
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408 | * @brief Abort the DMA Transfer. |
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409 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
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410 | * the configuration information for the specified DMA Channel. |
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411 | * @retval HAL status |
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412 | */ |
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413 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
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414 | { |
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415 | HAL_StatusTypeDef status = HAL_OK; |
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416 | |||
417 | /* Check the DMA peripheral state */ |
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418 | if(hdma->State != HAL_DMA_STATE_BUSY) |
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419 | { |
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420 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
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421 | |||
422 | /* Process Unlocked */ |
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423 | __HAL_UNLOCK(hdma); |
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424 | |||
425 | return HAL_ERROR; |
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426 | } |
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427 | else |
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428 | { |
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429 | /* Disable DMA IT */ |
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430 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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431 | |||
432 | /* Disable the channel */ |
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433 | __HAL_DMA_DISABLE(hdma); |
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434 | |||
435 | /* Clear all flags */ |
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436 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); |
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437 | |||
438 | /* Change the DMA state */ |
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439 | hdma->State = HAL_DMA_STATE_READY; |
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440 | |||
441 | /* Process Unlocked */ |
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442 | __HAL_UNLOCK(hdma); |
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443 | |||
444 | return status; |
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445 | } |
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446 | } |
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447 | |||
448 | /** |
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449 | * @brief Aborts the DMA Transfer in Interrupt mode. |
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450 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
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451 | * the configuration information for the specified DMA Channel. |
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452 | * @retval HAL status |
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453 | */ |
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454 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) |
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455 | { |
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456 | HAL_StatusTypeDef status = HAL_OK; |
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457 | |||
458 | if(HAL_DMA_STATE_BUSY != hdma->State) |
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459 | { |
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460 | /* no transfer ongoing */ |
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461 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
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462 | |||
463 | status = HAL_ERROR; |
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464 | } |
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465 | else |
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466 | { |
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467 | /* Disable DMA IT */ |
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468 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
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469 | |||
470 | /* Disable the channel */ |
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471 | __HAL_DMA_DISABLE(hdma); |
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472 | |||
473 | /* Clear all flags */ |
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474 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); |
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475 | |||
476 | /* Change the DMA state */ |
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477 | hdma->State = HAL_DMA_STATE_READY; |
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478 | |||
479 | /* Process Unlocked */ |
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480 | __HAL_UNLOCK(hdma); |
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481 | |||
482 | /* Call User Abort callback */ |
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483 | if(hdma->XferAbortCallback != NULL) |
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484 | { |
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485 | hdma->XferAbortCallback(hdma); |
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486 | } |
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487 | } |
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488 | return status; |
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489 | } |
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490 | |||
491 | /** |
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492 | * @brief Polling for transfer complete. |
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493 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
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494 | * the configuration information for the specified DMA Channel. |
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495 | * @param CompleteLevel Specifies the DMA level complete. |
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496 | * @param Timeout Timeout duration. |
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497 | * @retval HAL status |
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498 | */ |
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499 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) |
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500 | { |
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501 | uint32_t temp; |
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502 | uint32_t tickstart; |
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503 | |||
504 | if(HAL_DMA_STATE_BUSY != hdma->State) |
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505 | { |
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506 | /* no transfer ongoing */ |
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507 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
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508 | __HAL_UNLOCK(hdma); |
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509 | return HAL_ERROR; |
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510 | } |
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511 | |||
512 | /* Polling mode not supported in circular mode */ |
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513 | if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) |
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514 | { |
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515 | hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; |
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516 | return HAL_ERROR; |
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517 | } |
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518 | |||
519 | /* Get the level transfer complete flag */ |
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520 | if (HAL_DMA_FULL_TRANSFER == CompleteLevel) |
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521 | { |
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522 | /* Transfer Complete flag */ |
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523 | temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU); |
||
524 | } |
||
525 | else |
||
526 | { |
||
527 | /* Half Transfer Complete flag */ |
||
528 | temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU); |
||
529 | } |
||
530 | |||
531 | /* Get tick */ |
||
532 | tickstart = HAL_GetTick(); |
||
533 | |||
534 | while((hdma->DmaBaseAddress->ISR & temp) == 0U) |
||
535 | { |
||
536 | if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U) |
||
537 | { |
||
538 | /* When a DMA transfer error occurs */ |
||
539 | /* A hardware clear of its EN bits is performed */ |
||
540 | /* Clear all flags */ |
||
541 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); |
||
542 | |||
543 | /* Update error code */ |
||
544 | hdma->ErrorCode = HAL_DMA_ERROR_TE; |
||
545 | |||
546 | /* Change the DMA state */ |
||
547 | hdma->State= HAL_DMA_STATE_READY; |
||
548 | |||
549 | /* Process Unlocked */ |
||
550 | __HAL_UNLOCK(hdma); |
||
551 | |||
552 | return HAL_ERROR; |
||
553 | } |
||
554 | /* Check for the Timeout */ |
||
555 | if(Timeout != HAL_MAX_DELAY) |
||
556 | { |
||
557 | if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) |
||
558 | { |
||
559 | /* Update error code */ |
||
560 | hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; |
||
561 | |||
562 | /* Change the DMA state */ |
||
563 | hdma->State = HAL_DMA_STATE_READY; |
||
564 | |||
565 | /* Process Unlocked */ |
||
566 | __HAL_UNLOCK(hdma); |
||
567 | |||
568 | return HAL_ERROR; |
||
569 | } |
||
570 | } |
||
571 | } |
||
572 | |||
573 | if(HAL_DMA_FULL_TRANSFER == CompleteLevel) |
||
574 | { |
||
575 | /* Clear the transfer complete flag */ |
||
576 | hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU)); |
||
577 | |||
578 | /* The selected Channelx EN bit is cleared (DMA is disabled and |
||
579 | all transfers are complete) */ |
||
580 | hdma->State = HAL_DMA_STATE_READY; |
||
581 | } |
||
582 | else |
||
583 | { |
||
584 | /* Clear the half transfer complete flag */ |
||
585 | hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)); |
||
586 | } |
||
587 | |||
588 | /* Process unlocked */ |
||
589 | __HAL_UNLOCK(hdma); |
||
590 | |||
591 | return HAL_OK; |
||
592 | } |
||
593 | |||
594 | /** |
||
595 | * @brief Handle DMA interrupt request. |
||
596 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
597 | * the configuration information for the specified DMA Channel. |
||
598 | * @retval None |
||
599 | */ |
||
600 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) |
||
601 | { |
||
602 | uint32_t flag_it = hdma->DmaBaseAddress->ISR; |
||
603 | uint32_t source_it = hdma->Instance->CCR; |
||
604 | |||
605 | /* Half Transfer Complete Interrupt management ******************************/ |
||
606 | if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) |
||
607 | { |
||
608 | /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ |
||
609 | if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
||
610 | { |
||
611 | /* Disable the half transfer interrupt */ |
||
612 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
||
613 | } |
||
614 | /* Clear the half transfer complete flag */ |
||
615 | hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); |
||
616 | |||
617 | /* DMA peripheral state is not updated in Half Transfer */ |
||
618 | /* but in Transfer Complete case */ |
||
619 | |||
620 | if(hdma->XferHalfCpltCallback != NULL) |
||
621 | { |
||
622 | /* Half transfer callback */ |
||
623 | hdma->XferHalfCpltCallback(hdma); |
||
624 | } |
||
625 | } |
||
626 | |||
627 | /* Transfer Complete Interrupt management ***********************************/ |
||
628 | else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U)) |
||
629 | { |
||
630 | |||
631 | if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
||
632 | { |
||
633 | /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ |
||
634 | /* Disable the transfer complete and error interrupt */ |
||
635 | /* if the DMA mode is not CIRCULAR */ |
||
636 | __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); |
||
637 | |||
638 | /* Change the DMA state */ |
||
639 | hdma->State = HAL_DMA_STATE_READY; |
||
640 | } |
||
641 | /* Clear the transfer complete flag */ |
||
642 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU)); |
||
643 | |||
644 | /* Process Unlocked */ |
||
645 | __HAL_UNLOCK(hdma); |
||
646 | |||
647 | if(hdma->XferCpltCallback != NULL) |
||
648 | { |
||
649 | /* Transfer complete callback */ |
||
650 | hdma->XferCpltCallback(hdma); |
||
651 | } |
||
652 | } |
||
653 | |||
654 | /* Transfer Error Interrupt management **************************************/ |
||
655 | else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) |
||
656 | { |
||
657 | /* When a DMA transfer error occurs */ |
||
658 | /* A hardware clear of its EN bits is performed */ |
||
659 | /* Disable ALL DMA IT */ |
||
660 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
||
661 | |||
662 | /* Clear all flags */ |
||
663 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); |
||
664 | |||
665 | /* Update error code */ |
||
666 | hdma->ErrorCode = HAL_DMA_ERROR_TE; |
||
667 | |||
668 | /* Change the DMA state */ |
||
669 | hdma->State = HAL_DMA_STATE_READY; |
||
670 | |||
671 | /* Process Unlocked */ |
||
672 | __HAL_UNLOCK(hdma); |
||
673 | |||
674 | if (hdma->XferErrorCallback != NULL) |
||
675 | { |
||
676 | /* Transfer error callback */ |
||
677 | hdma->XferErrorCallback(hdma); |
||
678 | } |
||
679 | } |
||
680 | else |
||
681 | { |
||
682 | /* Nothing To Do */ |
||
683 | } |
||
684 | return; |
||
685 | } |
||
686 | |||
687 | /** |
||
688 | * @brief Register callbacks |
||
689 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
690 | * the configuration information for the specified DMA Channel. |
||
691 | * @param CallbackID User Callback identifier |
||
692 | * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
||
693 | * @param pCallback pointer to private callback function which has pointer to |
||
694 | * a DMA_HandleTypeDef structure as parameter. |
||
695 | * @retval HAL status |
||
696 | */ |
||
697 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) |
||
698 | { |
||
699 | HAL_StatusTypeDef status = HAL_OK; |
||
700 | |||
701 | /* Process locked */ |
||
702 | __HAL_LOCK(hdma); |
||
703 | |||
704 | if(HAL_DMA_STATE_READY == hdma->State) |
||
705 | { |
||
706 | switch (CallbackID) |
||
707 | { |
||
708 | case HAL_DMA_XFER_CPLT_CB_ID: |
||
709 | hdma->XferCpltCallback = pCallback; |
||
710 | break; |
||
711 | |||
712 | case HAL_DMA_XFER_HALFCPLT_CB_ID: |
||
713 | hdma->XferHalfCpltCallback = pCallback; |
||
714 | break; |
||
715 | |||
716 | case HAL_DMA_XFER_ERROR_CB_ID: |
||
717 | hdma->XferErrorCallback = pCallback; |
||
718 | break; |
||
719 | |||
720 | case HAL_DMA_XFER_ABORT_CB_ID: |
||
721 | hdma->XferAbortCallback = pCallback; |
||
722 | break; |
||
723 | |||
724 | default: |
||
725 | status = HAL_ERROR; |
||
726 | break; |
||
727 | } |
||
728 | } |
||
729 | else |
||
730 | { |
||
731 | status = HAL_ERROR; |
||
732 | } |
||
733 | |||
734 | /* Release Lock */ |
||
735 | __HAL_UNLOCK(hdma); |
||
736 | |||
737 | return status; |
||
738 | } |
||
739 | |||
740 | /** |
||
741 | * @brief UnRegister callbacks |
||
742 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
743 | * the configuration information for the specified DMA Channel. |
||
744 | * @param CallbackID User Callback identifier |
||
745 | * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
||
746 | * @retval HAL status |
||
747 | */ |
||
748 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) |
||
749 | { |
||
750 | HAL_StatusTypeDef status = HAL_OK; |
||
751 | |||
752 | /* Process locked */ |
||
753 | __HAL_LOCK(hdma); |
||
754 | |||
755 | if(HAL_DMA_STATE_READY == hdma->State) |
||
756 | { |
||
757 | switch (CallbackID) |
||
758 | { |
||
759 | case HAL_DMA_XFER_CPLT_CB_ID: |
||
760 | hdma->XferCpltCallback = NULL; |
||
761 | break; |
||
762 | |||
763 | case HAL_DMA_XFER_HALFCPLT_CB_ID: |
||
764 | hdma->XferHalfCpltCallback = NULL; |
||
765 | break; |
||
766 | |||
767 | case HAL_DMA_XFER_ERROR_CB_ID: |
||
768 | hdma->XferErrorCallback = NULL; |
||
769 | break; |
||
770 | |||
771 | case HAL_DMA_XFER_ABORT_CB_ID: |
||
772 | hdma->XferAbortCallback = NULL; |
||
773 | break; |
||
774 | |||
775 | case HAL_DMA_XFER_ALL_CB_ID: |
||
776 | hdma->XferCpltCallback = NULL; |
||
777 | hdma->XferHalfCpltCallback = NULL; |
||
778 | hdma->XferErrorCallback = NULL; |
||
779 | hdma->XferAbortCallback = NULL; |
||
780 | break; |
||
781 | |||
782 | default: |
||
783 | status = HAL_ERROR; |
||
784 | break; |
||
785 | } |
||
786 | } |
||
787 | else |
||
788 | { |
||
789 | status = HAL_ERROR; |
||
790 | } |
||
791 | |||
792 | /* Release Lock */ |
||
793 | __HAL_UNLOCK(hdma); |
||
794 | |||
795 | return status; |
||
796 | } |
||
797 | |||
798 | /** |
||
799 | * @} |
||
800 | */ |
||
801 | |||
802 | |||
803 | |||
804 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions |
||
805 | * @brief Peripheral State and Errors functions |
||
806 | * |
||
807 | @verbatim |
||
808 | =============================================================================== |
||
809 | ##### Peripheral State and Errors functions ##### |
||
810 | =============================================================================== |
||
811 | [..] |
||
812 | This subsection provides functions allowing to |
||
813 | (+) Check the DMA state |
||
814 | (+) Get error code |
||
815 | |||
816 | @endverbatim |
||
817 | * @{ |
||
818 | */ |
||
819 | |||
820 | /** |
||
821 | * @brief Return the DMA handle state. |
||
822 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
823 | * the configuration information for the specified DMA Channel. |
||
824 | * @retval HAL state |
||
825 | */ |
||
826 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) |
||
827 | { |
||
828 | /* Return DMA handle state */ |
||
829 | return hdma->State; |
||
830 | } |
||
831 | |||
832 | /** |
||
833 | * @brief Return the DMA error code. |
||
834 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
835 | * the configuration information for the specified DMA Channel. |
||
836 | * @retval DMA Error Code |
||
837 | */ |
||
838 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) |
||
839 | { |
||
840 | return hdma->ErrorCode; |
||
841 | } |
||
842 | |||
843 | /** |
||
844 | * @} |
||
845 | */ |
||
846 | |||
847 | /** |
||
848 | * @} |
||
849 | */ |
||
850 | |||
851 | /** @addtogroup DMA_Private_Functions |
||
852 | * @{ |
||
853 | */ |
||
854 | |||
855 | /** |
||
856 | * @brief Sets the DMA Transfer parameter. |
||
857 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains |
||
858 | * the configuration information for the specified DMA Channel. |
||
859 | * @param SrcAddress The source memory Buffer address |
||
860 | * @param DstAddress The destination memory Buffer address |
||
861 | * @param DataLength The length of data to be transferred from source to destination |
||
862 | * @retval HAL status |
||
863 | */ |
||
864 | static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
||
865 | { |
||
866 | /* Clear all flags */ |
||
867 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); |
||
868 | |||
869 | /* Configure DMA Channel data length */ |
||
870 | hdma->Instance->CNDTR = DataLength; |
||
871 | |||
872 | /* Memory to Peripheral */ |
||
873 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) |
||
874 | { |
||
875 | /* Configure DMA Channel destination address */ |
||
876 | hdma->Instance->CPAR = DstAddress; |
||
877 | |||
878 | /* Configure DMA Channel source address */ |
||
879 | hdma->Instance->CMAR = SrcAddress; |
||
880 | } |
||
881 | /* Peripheral to Memory */ |
||
882 | else |
||
883 | { |
||
884 | /* Configure DMA Channel source address */ |
||
885 | hdma->Instance->CPAR = SrcAddress; |
||
886 | |||
887 | /* Configure DMA Channel destination address */ |
||
888 | hdma->Instance->CMAR = DstAddress; |
||
889 | } |
||
890 | } |
||
891 | |||
892 | /** |
||
893 | * @} |
||
894 | */ |
||
895 | |||
896 | /** |
||
897 | * @} |
||
898 | */ |
||
899 | |||
900 | #endif /* HAL_DMA_MODULE_ENABLED */ |
||
901 | /** |
||
902 | * @} |
||
903 | */ |
||
904 | |||
905 | /** |
||
906 | * @} |
||
907 | */ |
||
908 | |||
909 |