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| Rev | Author | Line No. | Line |
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| 77 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_hal_adc.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief This file provides firmware functions to manage the following |
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| 6 | * functionalities of the Analog to Digital Convertor (ADC) |
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| 7 | * peripheral: |
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| 8 | * + Initialization and de-initialization functions |
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| 9 | * + Peripheral Control functions |
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| 10 | * + Peripheral State functions |
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| 11 | * Other functions (extended functions) are available in file |
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| 12 | * "stm32l1xx_hal_adc_ex.c". |
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| 13 | * |
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| 14 | ****************************************************************************** |
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| 15 | * @attention |
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| 16 | * |
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| 17 | * Copyright (c) 2017 STMicroelectronics. |
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| 18 | * All rights reserved. |
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| 19 | * |
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| 20 | * This software is licensed under terms that can be found in the LICENSE file |
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| 21 | * in the root directory of this software component. |
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| 22 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| 23 | * |
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| 24 | ****************************************************************************** |
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| 25 | @verbatim |
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| 26 | ============================================================================== |
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| 27 | ##### ADC peripheral features ##### |
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| 28 | ============================================================================== |
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| 29 | [..] |
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| 30 | (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution |
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| 31 | |||
| 32 | (+) Interrupt generation at the end of regular conversion, end of injected |
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| 33 | conversion, and in case of analog watchdog or overrun events. |
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| 34 | |||
| 35 | (+) Single and continuous conversion modes. |
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| 36 | |||
| 37 | (+) Scan mode for conversion of several channels sequentially. |
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| 38 | |||
| 39 | (+) Data alignment with in-built data coherency. |
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| 40 | |||
| 41 | (+) Programmable sampling time (channel wise) |
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| 42 | |||
| 43 | (+) ADC conversion of regular group and injected group. |
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| 44 | |||
| 45 | (+) External trigger (timer or EXTI) with configurable polarity |
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| 46 | for both regular and injected groups. |
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| 47 | |||
| 48 | (+) DMA request generation for transfer of conversions data of regular group. |
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| 49 | |||
| 50 | (+) ADC offset on injected channels |
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| 51 | |||
| 52 | (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
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| 53 | slower speed. |
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| 54 | |||
| 55 | (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to |
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| 56 | Vdda or to an external voltage reference). |
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| 57 | |||
| 58 | |||
| 59 | ##### How to use this driver ##### |
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| 60 | ============================================================================== |
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| 61 | [..] |
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| 62 | |||
| 63 | *** Configuration of top level parameters related to ADC *** |
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| 64 | ============================================================ |
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| 65 | [..] |
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| 66 | |||
| 67 | (#) Enable the ADC interface |
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| 68 | (++) As prerequisite, ADC clock must be configured at RCC top level. |
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| 69 | Caution: On STM32L1, ADC clock frequency max is 16MHz (refer |
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| 70 | to device datasheet). |
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| 71 | Therefore, ADC clock prescaler must be configured in |
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| 72 | function of ADC clock source frequency to remain below |
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| 73 | this maximum frequency. |
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| 74 | |||
| 75 | (++) Two clock settings are mandatory: |
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| 76 | (+++) ADC clock (core clock). |
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| 77 | (+++) ADC clock (conversions clock). |
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| 78 | Only one possible clock source: derived from HSI RC 16MHz oscillator |
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| 79 | (HSI). |
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| 80 | ADC is connected directly to HSI RC 16MHz oscillator. |
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| 81 | Therefore, RCC PLL setting has no impact on ADC. |
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| 82 | PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or |
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| 83 | enabled with HSI16 as clock source |
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| 84 | (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device |
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| 85 | main clock source SYSCLK. |
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| 86 | The only mandatory setting is ".HSIState = RCC_HSI_ON" |
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| 87 | |||
| 88 | (+++) Example: |
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| 89 | Into HAL_ADC_MspInit() (recommended code location) or with |
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| 90 | other device clock parameters configuration: |
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| 91 | (+++) __HAL_RCC_ADC1_CLK_ENABLE(); |
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| 92 | |||
| 93 | (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); |
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| 94 | (+++) RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI); |
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| 95 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON; |
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| 96 | (+++) RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
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| 97 | (+++) RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE; |
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| 98 | (+++) RCC_OscInitStructure.PLL.PLLSource = ... |
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| 99 | (+++) RCC_OscInitStructure.PLL... |
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| 100 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
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| 101 | |||
| 102 | (++) ADC clock prescaler is configured at ADC level with |
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| 103 | parameter "ClockPrescaler" using function HAL_ADC_Init(). |
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| 104 | |||
| 105 | (#) ADC pins configuration |
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| 106 | (++) Enable the clock for the ADC GPIOs |
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| 107 | using macro __HAL_RCC_GPIOx_CLK_ENABLE() |
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| 108 | (++) Configure these ADC pins in analog mode |
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| 109 | using function HAL_GPIO_Init() |
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| 110 | |||
| 111 | (#) Optionally, in case of usage of ADC with interruptions: |
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| 112 | (++) Configure the NVIC for ADC |
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| 113 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
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| 114 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
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| 115 | into the function of corresponding ADC interruption vector |
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| 116 | ADCx_IRQHandler(). |
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| 117 | |||
| 118 | (#) Optionally, in case of usage of DMA: |
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| 119 | (++) Configure the DMA (DMA channel, mode normal or circular, ...) |
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| 120 | using function HAL_DMA_Init(). |
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| 121 | (++) Configure the NVIC for DMA |
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| 122 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
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| 123 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
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| 124 | into the function of corresponding DMA interruption vector |
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| 125 | DMAx_Channelx_IRQHandler(). |
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| 126 | |||
| 127 | *** Configuration of ADC, groups regular/injected, channels parameters *** |
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| 128 | ========================================================================== |
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| 129 | [..] |
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| 130 | |||
| 131 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
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| 132 | and regular group parameters (conversion trigger, sequencer, ...) |
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| 133 | using function HAL_ADC_Init(). |
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| 134 | |||
| 135 | (#) Configure the channels for regular group parameters (channel number, |
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| 136 | channel rank into sequencer, ..., into regular group) |
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| 137 | using function HAL_ADC_ConfigChannel(). |
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| 138 | |||
| 139 | (#) Optionally, configure the injected group parameters (conversion trigger, |
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| 140 | sequencer, ..., of injected group) |
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| 141 | and the channels for injected group parameters (channel number, |
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| 142 | channel rank into sequencer, ..., into injected group) |
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| 143 | using function HAL_ADCEx_InjectedConfigChannel(). |
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| 144 | |||
| 145 | (#) Optionally, configure the analog watchdog parameters (channels |
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| 146 | monitored, thresholds, ...) |
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| 147 | using function HAL_ADC_AnalogWDGConfig(). |
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| 148 | |||
| 149 | (#) Optionally, for devices with several ADC instances: configure the |
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| 150 | multimode parameters |
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| 151 | using function HAL_ADCEx_MultiModeConfigChannel(). |
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| 152 | |||
| 153 | *** Execution of ADC conversions *** |
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| 154 | ==================================== |
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| 155 | [..] |
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| 156 | |||
| 157 | (#) ADC driver can be used among three modes: polling, interruption, |
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| 158 | transfer by DMA. |
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| 159 | |||
| 160 | (++) ADC conversion by polling: |
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| 161 | (+++) Activate the ADC peripheral and start conversions |
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| 162 | using function HAL_ADC_Start() |
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| 163 | (+++) Wait for ADC conversion completion |
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| 164 | using function HAL_ADC_PollForConversion() |
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| 165 | (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) |
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| 166 | (+++) Retrieve conversion results |
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| 167 | using function HAL_ADC_GetValue() |
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| 168 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
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| 169 | (+++) Stop conversion and disable the ADC peripheral |
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| 170 | using function HAL_ADC_Stop() |
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| 171 | |||
| 172 | (++) ADC conversion by interruption: |
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| 173 | (+++) Activate the ADC peripheral and start conversions |
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| 174 | using function HAL_ADC_Start_IT() |
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| 175 | (+++) Wait for ADC conversion completion by call of function |
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| 176 | HAL_ADC_ConvCpltCallback() |
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| 177 | (this function must be implemented in user program) |
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| 178 | (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) |
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| 179 | (+++) Retrieve conversion results |
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| 180 | using function HAL_ADC_GetValue() |
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| 181 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
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| 182 | (+++) Stop conversion and disable the ADC peripheral |
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| 183 | using function HAL_ADC_Stop_IT() |
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| 184 | |||
| 185 | (++) ADC conversion with transfer by DMA: |
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| 186 | (+++) Activate the ADC peripheral and start conversions |
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| 187 | using function HAL_ADC_Start_DMA() |
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| 188 | (+++) Wait for ADC conversion completion by call of function |
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| 189 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
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| 190 | (these functions must be implemented in user program) |
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| 191 | (+++) Conversion results are automatically transferred by DMA into |
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| 192 | destination variable address. |
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| 193 | (+++) Stop conversion and disable the ADC peripheral |
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| 194 | using function HAL_ADC_Stop_DMA() |
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| 195 | |||
| 196 | (++) For devices with several ADCs: ADC multimode conversion |
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| 197 | with transfer by DMA: |
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| 198 | (+++) Activate the ADC peripheral (slave) and start conversions |
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| 199 | using function HAL_ADC_Start() |
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| 200 | (+++) Activate the ADC peripheral (master) and start conversions |
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| 201 | using function HAL_ADCEx_MultiModeStart_DMA() |
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| 202 | (+++) Wait for ADC conversion completion by call of function |
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| 203 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
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| 204 | (these functions must be implemented in user program) |
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| 205 | (+++) Conversion results are automatically transferred by DMA into |
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| 206 | destination variable address. |
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| 207 | (+++) Stop conversion and disable the ADC peripheral (master) |
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| 208 | using function HAL_ADCEx_MultiModeStop_DMA() |
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| 209 | (+++) Stop conversion and disable the ADC peripheral (slave) |
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| 210 | using function HAL_ADC_Stop_IT() |
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| 211 | |||
| 212 | [..] |
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| 213 | |||
| 214 | (@) Callback functions must be implemented in user program: |
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| 215 | (+@) HAL_ADC_ErrorCallback() |
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| 216 | (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) |
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| 217 | (+@) HAL_ADC_ConvCpltCallback() |
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| 218 | (+@) HAL_ADC_ConvHalfCpltCallback |
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| 219 | (+@) HAL_ADCEx_InjectedConvCpltCallback() |
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| 220 | |||
| 221 | *** Deinitialization of ADC *** |
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| 222 | ============================================================ |
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| 223 | [..] |
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| 224 | |||
| 225 | (#) Disable the ADC interface |
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| 226 | (++) ADC clock can be hard reset and disabled at RCC top level. |
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| 227 | (++) Hard reset of ADC peripherals |
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| 228 | using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). |
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| 229 | (++) ADC clock disable |
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| 230 | using the equivalent macro/functions as configuration step. |
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| 231 | (+++) Example: |
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| 232 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
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| 233 | other device clock parameters configuration: |
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| 234 | (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); |
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| 235 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
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| 236 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) |
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| 237 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
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| 238 | |||
| 239 | (#) ADC pins configuration |
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| 240 | (++) Disable the clock for the ADC GPIOs |
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| 241 | using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
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| 242 | |||
| 243 | (#) Optionally, in case of usage of ADC with interruptions: |
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| 244 | (++) Disable the NVIC for ADC |
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| 245 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
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| 246 | |||
| 247 | (#) Optionally, in case of usage of DMA: |
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| 248 | (++) Deinitialize the DMA |
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| 249 | using function HAL_DMA_Init(). |
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| 250 | (++) Disable the NVIC for DMA |
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| 251 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
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| 252 | |||
| 253 | [..] |
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| 254 | |||
| 255 | *** Callback registration *** |
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| 256 | ============================================= |
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| 257 | [..] |
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| 258 | |||
| 259 | The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, |
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| 260 | allows the user to configure dynamically the driver callbacks. |
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| 261 | Use Functions HAL_ADC_RegisterCallback() |
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| 262 | to register an interrupt callback. |
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| 263 | [..] |
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| 264 | |||
| 265 | Function HAL_ADC_RegisterCallback() allows to register following callbacks: |
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| 266 | (+) ConvCpltCallback : ADC conversion complete callback |
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| 267 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
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| 268 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
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| 269 | (+) ErrorCallback : ADC error callback |
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| 270 | (+) InjectedConvCpltCallback : ADC group injected conversion complete callback |
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| 271 | (+) MspInitCallback : ADC Msp Init callback |
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| 272 | (+) MspDeInitCallback : ADC Msp DeInit callback |
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| 273 | This function takes as parameters the HAL peripheral handle, the Callback ID |
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| 274 | and a pointer to the user callback function. |
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| 275 | [..] |
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| 276 | |||
| 277 | Use function HAL_ADC_UnRegisterCallback to reset a callback to the default |
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| 278 | weak function. |
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| 279 | [..] |
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| 280 | |||
| 281 | HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, |
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| 282 | and the Callback ID. |
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| 283 | This function allows to reset following callbacks: |
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| 284 | (+) ConvCpltCallback : ADC conversion complete callback |
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| 285 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
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| 286 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
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| 287 | (+) ErrorCallback : ADC error callback |
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| 288 | (+) InjectedConvCpltCallback : ADC group injected conversion complete callback |
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| 289 | (+) MspInitCallback : ADC Msp Init callback |
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| 290 | (+) MspDeInitCallback : ADC Msp DeInit callback |
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| 291 | [..] |
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| 292 | |||
| 293 | By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET |
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| 294 | all callbacks are set to the corresponding weak functions: |
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| 295 | examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). |
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| 296 | Exception done for MspInit and MspDeInit functions that are |
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| 297 | reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when |
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| 298 | these callbacks are null (not registered beforehand). |
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| 299 | [..] |
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| 300 | |||
| 301 | If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() |
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| 302 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
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| 303 | [..] |
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| 304 | |||
| 305 | Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. |
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| 306 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
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| 307 | in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, |
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| 308 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
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| 309 | [..] |
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| 310 | |||
| 311 | Then, the user first registers the MspInit/MspDeInit user callbacks |
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| 312 | using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() |
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| 313 | or HAL_ADC_Init() function. |
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| 314 | [..] |
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| 315 | |||
| 316 | When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or |
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| 317 | not defined, the callback registration feature is not available and all callbacks |
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| 318 | are set to the corresponding weak functions. |
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| 319 | |||
| 320 | @endverbatim |
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| 321 | */ |
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| 322 | |||
| 323 | /* Includes ------------------------------------------------------------------*/ |
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| 324 | #include "stm32l1xx_hal.h" |
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| 325 | |||
| 326 | /** @addtogroup STM32L1xx_HAL_Driver |
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| 327 | * @{ |
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| 328 | */ |
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| 329 | |||
| 330 | /** @defgroup ADC ADC |
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| 331 | * @brief ADC HAL module driver |
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| 332 | * @{ |
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| 333 | */ |
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| 334 | |||
| 335 | #ifdef HAL_ADC_MODULE_ENABLED |
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| 336 | |||
| 337 | /* Private typedef -----------------------------------------------------------*/ |
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| 338 | /* Private define ------------------------------------------------------------*/ |
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| 339 | /** @defgroup ADC_Private_Constants ADC Private Constants |
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| 340 | * @{ |
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| 341 | */ |
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| 342 | |||
| 343 | /* Timeout values for ADC enable and disable settling time. */ |
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| 344 | /* Values defined to be higher than worst cases: low clocks freq, */ |
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| 345 | /* maximum prescaler. */ |
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| 346 | /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ |
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| 347 | /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ |
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| 348 | /* Unit: ms */ |
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| 349 | #define ADC_ENABLE_TIMEOUT (2U) |
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| 350 | #define ADC_DISABLE_TIMEOUT (2U) |
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| 351 | |||
| 352 | /* Delay for ADC stabilization time. */ |
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| 353 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
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| 354 | /* Unit: us */ |
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| 355 | #define ADC_STAB_DELAY_US (3U) |
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| 356 | |||
| 357 | /* Delay for temperature sensor stabilization time. */ |
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| 358 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
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| 359 | /* Unit: us */ |
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| 360 | #define ADC_TEMPSENSOR_DELAY_US (10U) |
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| 361 | |||
| 362 | /** |
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| 363 | * @} |
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| 364 | */ |
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| 365 | |||
| 366 | /* Private macro -------------------------------------------------------------*/ |
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| 367 | /* Private variables ---------------------------------------------------------*/ |
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| 368 | /* Private function prototypes -----------------------------------------------*/ |
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| 369 | /** @defgroup ADC_Private_Functions ADC Private Functions |
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| 370 | * @{ |
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| 371 | */ |
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| 372 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
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| 373 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
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| 374 | static void ADC_DMAError(DMA_HandleTypeDef *hdma); |
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| 375 | /** |
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| 376 | * @} |
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| 377 | */ |
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| 378 | |||
| 379 | /* Exported functions --------------------------------------------------------*/ |
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| 380 | |||
| 381 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
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| 382 | * @{ |
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| 383 | */ |
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| 384 | |||
| 385 | /** @defgroup ADC_Exported_Functions_Group1 ADC Initialization/de-initialization functions |
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| 386 | * @brief ADC Initialization and Configuration functions |
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| 387 | * |
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| 388 | @verbatim |
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| 389 | =============================================================================== |
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| 390 | ##### Initialization and de-initialization functions ##### |
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| 391 | =============================================================================== |
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| 392 | [..] This section provides functions allowing to: |
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| 393 | (+) Initialize and configure the ADC. |
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| 394 | (+) De-initialize the ADC. |
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| 395 | @endverbatim |
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| 396 | * @{ |
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| 397 | */ |
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| 398 | |||
| 399 | /** |
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| 400 | * @brief Initializes the ADC peripheral and regular group according to |
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| 401 | * parameters specified in structure "ADC_InitTypeDef". |
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| 402 | * @note As prerequisite, ADC clock must be configured at RCC top level |
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| 403 | * (clock source APB2). |
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| 404 | * See commented example code below that can be copied and uncommented |
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| 405 | * into HAL_ADC_MspInit(). |
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| 406 | * @note Possibility to update parameters on the fly: |
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| 407 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
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| 408 | * coming from ADC state reset. Following calls to this function can |
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| 409 | * be used to reconfigure some parameters of ADC_InitTypeDef |
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| 410 | * structure on the fly, without modifying MSP configuration. If ADC |
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| 411 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
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| 412 | * before HAL_ADC_Init(). |
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| 413 | * The setting of these parameters is conditioned to ADC state. |
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| 414 | * For parameters constraints, see comments of structure |
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| 415 | * "ADC_InitTypeDef". |
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| 416 | * @note This function configures the ADC within 2 scopes: scope of entire |
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| 417 | * ADC and scope of regular group. For parameters details, see comments |
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| 418 | * of structure "ADC_InitTypeDef". |
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| 419 | * @param hadc ADC handle |
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| 420 | * @retval HAL status |
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| 421 | */ |
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| 422 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
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| 423 | { |
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| 424 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
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| 425 | uint32_t tmp_cr1 = 0; |
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| 426 | uint32_t tmp_cr2 = 0; |
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| 427 | |||
| 428 | /* Check ADC handle */ |
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| 429 | if(hadc == NULL) |
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| 430 | { |
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| 431 | return HAL_ERROR; |
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| 432 | } |
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| 433 | |||
| 434 | /* Check the parameters */ |
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| 435 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
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| 436 | assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); |
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| 437 | assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); |
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| 438 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
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| 439 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
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| 440 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
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| 441 | assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait)); |
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| 442 | assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff)); |
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| 443 | assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank)); |
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| 444 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
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| 445 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
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| 446 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
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| 447 | |||
| 448 | if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) |
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| 449 | { |
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| 450 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
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| 451 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
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| 452 | if(hadc->Init.DiscontinuousConvMode != DISABLE) |
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| 453 | { |
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| 454 | assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); |
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| 455 | } |
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| 456 | } |
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| 457 | |||
| 458 | if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
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| 459 | { |
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| 460 | assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
||
| 461 | } |
||
| 462 | |||
| 463 | |||
| 464 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
||
| 465 | /* at RCC top level. */ |
||
| 466 | /* Refer to header of this file for more details on clock enabling */ |
||
| 467 | /* procedure. */ |
||
| 468 | |||
| 469 | /* Actions performed only if ADC is coming from state reset: */ |
||
| 470 | /* - Initialization of ADC MSP */ |
||
| 471 | if (hadc->State == HAL_ADC_STATE_RESET) |
||
| 472 | { |
||
| 473 | /* Initialize ADC error code */ |
||
| 474 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 475 | |||
| 476 | /* Allocate lock resource and initialize it */ |
||
| 477 | hadc->Lock = HAL_UNLOCKED; |
||
| 478 | |||
| 479 | /* Enable SYSCFG clock to control the routing Interface (RI) */ |
||
| 480 | __HAL_RCC_SYSCFG_CLK_ENABLE(); |
||
| 481 | |||
| 482 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 483 | /* Init the ADC Callback settings */ |
||
| 484 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ |
||
| 485 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ |
||
| 486 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ |
||
| 487 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ |
||
| 488 | hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ |
||
| 489 | |||
| 490 | if (hadc->MspInitCallback == NULL) |
||
| 491 | { |
||
| 492 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
| 493 | } |
||
| 494 | |||
| 495 | /* Init the low level hardware */ |
||
| 496 | hadc->MspInitCallback(hadc); |
||
| 497 | #else |
||
| 498 | /* Init the low level hardware */ |
||
| 499 | HAL_ADC_MspInit(hadc); |
||
| 500 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 501 | } |
||
| 502 | |||
| 503 | /* Configuration of ADC parameters if previous preliminary actions are */ |
||
| 504 | /* correctly completed. */ |
||
| 505 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
||
| 506 | { |
||
| 507 | /* Set ADC state */ |
||
| 508 | ADC_STATE_CLR_SET(hadc->State, |
||
| 509 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
| 510 | HAL_ADC_STATE_BUSY_INTERNAL); |
||
| 511 | |||
| 512 | /* Set ADC parameters */ |
||
| 513 | |||
| 514 | /* Configuration of common ADC clock: clock source HSI with selectable */ |
||
| 515 | /* prescaler */ |
||
| 516 | MODIFY_REG(ADC->CCR , |
||
| 517 | ADC_CCR_ADCPRE , |
||
| 518 | hadc->Init.ClockPrescaler ); |
||
| 519 | |||
| 520 | /* Configuration of ADC: */ |
||
| 521 | /* - external trigger polarity */ |
||
| 522 | /* - End of conversion selection */ |
||
| 523 | /* - DMA continuous request */ |
||
| 524 | /* - Channels bank (Banks availability depends on devices categories) */ |
||
| 525 | /* - continuous conversion mode */ |
||
| 526 | tmp_cr2 |= (hadc->Init.DataAlign | |
||
| 527 | hadc->Init.EOCSelection | |
||
| 528 | ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) | |
||
| 529 | hadc->Init.ChannelsBank | |
||
| 530 | ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); |
||
| 531 | |||
| 532 | /* Enable external trigger if trigger selection is different of software */ |
||
| 533 | /* start. */ |
||
| 534 | /* Note: This configuration keeps the hardware feature of parameter */ |
||
| 535 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
||
| 536 | /* software start. */ |
||
| 537 | if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
||
| 538 | { |
||
| 539 | tmp_cr2 |= ( hadc->Init.ExternalTrigConv | |
||
| 540 | hadc->Init.ExternalTrigConvEdge ); |
||
| 541 | } |
||
| 542 | |||
| 543 | /* Parameters update conditioned to ADC state: */ |
||
| 544 | /* Parameters that can be updated only when ADC is disabled: */ |
||
| 545 | /* - delay selection (LowPowerAutoWait mode) */ |
||
| 546 | /* - resolution */ |
||
| 547 | /* - auto power off (LowPowerAutoPowerOff mode) */ |
||
| 548 | /* - scan mode */ |
||
| 549 | /* - discontinuous mode disable/enable */ |
||
| 550 | /* - discontinuous mode number of conversions */ |
||
| 551 | if ((ADC_IS_ENABLE(hadc) == RESET)) |
||
| 552 | { |
||
| 553 | tmp_cr2 |= hadc->Init.LowPowerAutoWait; |
||
| 554 | |||
| 555 | tmp_cr1 |= (hadc->Init.Resolution | |
||
| 556 | hadc->Init.LowPowerAutoPowerOff | |
||
| 557 | ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) ); |
||
| 558 | |||
| 559 | /* Enable discontinuous mode only if continuous mode is disabled */ |
||
| 560 | /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ |
||
| 561 | /* discontinuous is set anyway, but has no effect on ADC HW. */ |
||
| 562 | if (hadc->Init.DiscontinuousConvMode == ENABLE) |
||
| 563 | { |
||
| 564 | if (hadc->Init.ContinuousConvMode == DISABLE) |
||
| 565 | { |
||
| 566 | /* Enable the selected ADC regular discontinuous mode */ |
||
| 567 | /* Set the number of channels to be converted in discontinuous mode */ |
||
| 568 | SET_BIT(tmp_cr1, ADC_CR1_DISCEN | |
||
| 569 | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); |
||
| 570 | } |
||
| 571 | else |
||
| 572 | { |
||
| 573 | /* ADC regular group settings continuous and sequencer discontinuous*/ |
||
| 574 | /* cannot be enabled simultaneously. */ |
||
| 575 | |||
| 576 | /* Update ADC state machine to error */ |
||
| 577 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
| 578 | |||
| 579 | /* Set ADC error code to ADC IP internal error */ |
||
| 580 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
| 581 | } |
||
| 582 | } |
||
| 583 | |||
| 584 | /* Update ADC configuration register CR1 with previous settings */ |
||
| 585 | MODIFY_REG(hadc->Instance->CR1, |
||
| 586 | ADC_CR1_RES | |
||
| 587 | ADC_CR1_PDI | |
||
| 588 | ADC_CR1_PDD | |
||
| 589 | ADC_CR1_DISCNUM | |
||
| 590 | ADC_CR1_DISCEN | |
||
| 591 | ADC_CR1_SCAN , |
||
| 592 | tmp_cr1 ); |
||
| 593 | } |
||
| 594 | |||
| 595 | /* Update ADC configuration register CR2 with previous settings */ |
||
| 596 | MODIFY_REG(hadc->Instance->CR2 , |
||
| 597 | ADC_CR2_MASK_ADCINIT() , |
||
| 598 | tmp_cr2 ); |
||
| 599 | |||
| 600 | /* Configuration of regular group sequencer: */ |
||
| 601 | /* - if scan mode is disabled, regular channels sequence length is set to */ |
||
| 602 | /* 0x00: 1 channel converted (channel on regular rank 1) */ |
||
| 603 | /* Parameter "NbrOfConversion" is discarded. */ |
||
| 604 | /* Note: Scan mode is present by hardware on this device and, if */ |
||
| 605 | /* disabled, discards automatically nb of conversions. Anyway, nb of */ |
||
| 606 | /* conversions is forced to 0x00 for alignment over all STM32 devices. */ |
||
| 607 | /* - if scan mode is enabled, regular channels sequence length is set to */ |
||
| 608 | /* parameter "NbrOfConversion" */ |
||
| 609 | if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) |
||
| 610 | { |
||
| 611 | MODIFY_REG(hadc->Instance->SQR1 , |
||
| 612 | ADC_SQR1_L , |
||
| 613 | ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion) ); |
||
| 614 | } |
||
| 615 | else |
||
| 616 | { |
||
| 617 | MODIFY_REG(hadc->Instance->SQR1, |
||
| 618 | ADC_SQR1_L , |
||
| 619 | 0x00000000 ); |
||
| 620 | } |
||
| 621 | |||
| 622 | /* Check back that ADC registers have effectively been configured to */ |
||
| 623 | /* ensure of no potential problem of ADC core IP clocking. */ |
||
| 624 | /* Check through register CR2 (excluding execution control bits ADON, */ |
||
| 625 | /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */ |
||
| 626 | if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON | |
||
| 627 | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | |
||
| 628 | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL )) |
||
| 629 | == tmp_cr2) |
||
| 630 | { |
||
| 631 | /* Set ADC error code to none */ |
||
| 632 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 633 | |||
| 634 | /* Set the ADC state */ |
||
| 635 | ADC_STATE_CLR_SET(hadc->State, |
||
| 636 | HAL_ADC_STATE_BUSY_INTERNAL, |
||
| 637 | HAL_ADC_STATE_READY); |
||
| 638 | } |
||
| 639 | else |
||
| 640 | { |
||
| 641 | /* Update ADC state machine to error */ |
||
| 642 | ADC_STATE_CLR_SET(hadc->State, |
||
| 643 | HAL_ADC_STATE_BUSY_INTERNAL, |
||
| 644 | HAL_ADC_STATE_ERROR_INTERNAL); |
||
| 645 | |||
| 646 | /* Set ADC error code to ADC IP internal error */ |
||
| 647 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
| 648 | |||
| 649 | tmp_hal_status = HAL_ERROR; |
||
| 650 | } |
||
| 651 | |||
| 652 | } |
||
| 653 | else |
||
| 654 | { |
||
| 655 | tmp_hal_status = HAL_ERROR; |
||
| 656 | } |
||
| 657 | |||
| 658 | /* Return function status */ |
||
| 659 | return tmp_hal_status; |
||
| 660 | } |
||
| 661 | |||
| 662 | /** |
||
| 663 | * @brief Deinitialize the ADC peripheral registers to its default reset values. |
||
| 664 | * @note To not impact other ADCs, reset of common ADC registers have been |
||
| 665 | * left commented below. |
||
| 666 | * If needed, the example code can be copied and uncommented into |
||
| 667 | * function HAL_ADC_MspDeInit(). |
||
| 668 | * @param hadc ADC handle |
||
| 669 | * @retval HAL status |
||
| 670 | */ |
||
| 671 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
||
| 672 | { |
||
| 673 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 674 | |||
| 675 | /* Check ADC handle */ |
||
| 676 | if(hadc == NULL) |
||
| 677 | { |
||
| 678 | return HAL_ERROR; |
||
| 679 | } |
||
| 680 | |||
| 681 | /* Check the parameters */ |
||
| 682 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 683 | |||
| 684 | /* Set ADC state */ |
||
| 685 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
||
| 686 | |||
| 687 | /* Stop potential conversion on going, on regular and injected groups */ |
||
| 688 | /* Disable ADC peripheral */ |
||
| 689 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
| 690 | |||
| 691 | |||
| 692 | /* Configuration of ADC parameters if previous preliminary actions are */ |
||
| 693 | /* correctly completed. */ |
||
| 694 | if (tmp_hal_status == HAL_OK) |
||
| 695 | { |
||
| 696 | /* ========== Reset ADC registers ========== */ |
||
| 697 | /* Reset register SR */ |
||
| 698 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | |
||
| 699 | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); |
||
| 700 | |||
| 701 | /* Reset register CR1 */ |
||
| 702 | CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN | |
||
| 703 | ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD | |
||
| 704 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | |
||
| 705 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | |
||
| 706 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE | |
||
| 707 | ADC_CR1_AWDCH )); |
||
| 708 | |||
| 709 | /* Reset register CR2 */ |
||
| 710 | ADC_CR2_CLEAR(hadc); |
||
| 711 | |||
| 712 | /* Reset register SMPR0 */ |
||
| 713 | ADC_SMPR0_CLEAR(hadc); |
||
| 714 | |||
| 715 | /* Reset register SMPR1 */ |
||
| 716 | ADC_SMPR1_CLEAR(hadc); |
||
| 717 | |||
| 718 | /* Reset register SMPR2 */ |
||
| 719 | CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | |
||
| 720 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | |
||
| 721 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | |
||
| 722 | ADC_SMPR2_SMP10 )); |
||
| 723 | |||
| 724 | /* Reset register SMPR3 */ |
||
| 725 | CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 | |
||
| 726 | ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 | |
||
| 727 | ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 | |
||
| 728 | ADC_SMPR3_SMP0 )); |
||
| 729 | |||
| 730 | /* Reset register JOFR1 */ |
||
| 731 | CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); |
||
| 732 | /* Reset register JOFR2 */ |
||
| 733 | CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); |
||
| 734 | /* Reset register JOFR3 */ |
||
| 735 | CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); |
||
| 736 | /* Reset register JOFR4 */ |
||
| 737 | CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); |
||
| 738 | |||
| 739 | /* Reset register HTR */ |
||
| 740 | CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); |
||
| 741 | /* Reset register LTR */ |
||
| 742 | CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); |
||
| 743 | |||
| 744 | /* Reset register SQR1 */ |
||
| 745 | CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L | __ADC_SQR1_SQXX)); |
||
| 746 | |||
| 747 | /* Reset register SQR2 */ |
||
| 748 | CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 | |
||
| 749 | ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19 )); |
||
| 750 | |||
| 751 | /* Reset register SQR3 */ |
||
| 752 | CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 | |
||
| 753 | ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13 )); |
||
| 754 | |||
| 755 | /* Reset register SQR4 */ |
||
| 756 | CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 | |
||
| 757 | ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 )); |
||
| 758 | |||
| 759 | /* Reset register SQR5 */ |
||
| 760 | CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 | |
||
| 761 | ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 )); |
||
| 762 | |||
| 763 | |||
| 764 | /* Reset register JSQR */ |
||
| 765 | CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL | |
||
| 766 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | |
||
| 767 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )); |
||
| 768 | |||
| 769 | /* Reset register DR */ |
||
| 770 | /* bits in access mode read only, no direct reset applicable*/ |
||
| 771 | |||
| 772 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
||
| 773 | /* bits in access mode read only, no direct reset applicable*/ |
||
| 774 | |||
| 775 | /* Reset register CCR */ |
||
| 776 | CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE); |
||
| 777 | |||
| 778 | /* ========== Hard reset ADC peripheral ========== */ |
||
| 779 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
||
| 780 | /* forced to a similar state after device power-on. */ |
||
| 781 | /* If needed, copy-paste and uncomment the following reset code into */ |
||
| 782 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
||
| 783 | /* */ |
||
| 784 | /* __HAL_RCC_ADC1_FORCE_RESET() */ |
||
| 785 | /* __HAL_RCC_ADC1_RELEASE_RESET() */ |
||
| 786 | |||
| 787 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 788 | if (hadc->MspDeInitCallback == NULL) |
||
| 789 | { |
||
| 790 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
| 791 | } |
||
| 792 | |||
| 793 | /* DeInit the low level hardware */ |
||
| 794 | hadc->MspDeInitCallback(hadc); |
||
| 795 | #else |
||
| 796 | /* DeInit the low level hardware */ |
||
| 797 | HAL_ADC_MspDeInit(hadc); |
||
| 798 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 799 | |||
| 800 | /* Set ADC error code to none */ |
||
| 801 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 802 | |||
| 803 | /* Set ADC state */ |
||
| 804 | hadc->State = HAL_ADC_STATE_RESET; |
||
| 805 | |||
| 806 | } |
||
| 807 | |||
| 808 | /* Process unlocked */ |
||
| 809 | __HAL_UNLOCK(hadc); |
||
| 810 | |||
| 811 | /* Return function status */ |
||
| 812 | return tmp_hal_status; |
||
| 813 | } |
||
| 814 | |||
| 815 | /** |
||
| 816 | * @brief Initializes the ADC MSP. |
||
| 817 | * @param hadc ADC handle |
||
| 818 | * @retval None |
||
| 819 | */ |
||
| 820 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
||
| 821 | { |
||
| 822 | /* Prevent unused argument(s) compilation warning */ |
||
| 823 | UNUSED(hadc); |
||
| 824 | |||
| 825 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 826 | function HAL_ADC_MspInit must be implemented in the user file. |
||
| 827 | */ |
||
| 828 | } |
||
| 829 | |||
| 830 | /** |
||
| 831 | * @brief DeInitializes the ADC MSP. |
||
| 832 | * @param hadc ADC handle |
||
| 833 | * @retval None |
||
| 834 | */ |
||
| 835 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
||
| 836 | { |
||
| 837 | /* Prevent unused argument(s) compilation warning */ |
||
| 838 | UNUSED(hadc); |
||
| 839 | |||
| 840 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 841 | function HAL_ADC_MspDeInit must be implemented in the user file. |
||
| 842 | */ |
||
| 843 | } |
||
| 844 | |||
| 845 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 846 | /** |
||
| 847 | * @brief Register a User ADC Callback |
||
| 848 | * To be used instead of the weak predefined callback |
||
| 849 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
||
| 850 | * the configuration information for the specified ADC. |
||
| 851 | * @param CallbackID ID of the callback to be registered |
||
| 852 | * This parameter can be one of the following values: |
||
| 853 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
||
| 854 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
||
| 855 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
||
| 856 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
||
| 857 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
||
| 858 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
||
| 859 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
||
| 860 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
||
| 861 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
||
| 862 | * @param pCallback pointer to the Callback function |
||
| 863 | * @retval HAL status |
||
| 864 | */ |
||
| 865 | HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) |
||
| 866 | { |
||
| 867 | HAL_StatusTypeDef status = HAL_OK; |
||
| 868 | |||
| 869 | if (pCallback == NULL) |
||
| 870 | { |
||
| 871 | /* Update the error code */ |
||
| 872 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 873 | |||
| 874 | return HAL_ERROR; |
||
| 875 | } |
||
| 876 | |||
| 877 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
||
| 878 | { |
||
| 879 | switch (CallbackID) |
||
| 880 | { |
||
| 881 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
||
| 882 | hadc->ConvCpltCallback = pCallback; |
||
| 883 | break; |
||
| 884 | |||
| 885 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
||
| 886 | hadc->ConvHalfCpltCallback = pCallback; |
||
| 887 | break; |
||
| 888 | |||
| 889 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
||
| 890 | hadc->LevelOutOfWindowCallback = pCallback; |
||
| 891 | break; |
||
| 892 | |||
| 893 | case HAL_ADC_ERROR_CB_ID : |
||
| 894 | hadc->ErrorCallback = pCallback; |
||
| 895 | break; |
||
| 896 | |||
| 897 | case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : |
||
| 898 | hadc->InjectedConvCpltCallback = pCallback; |
||
| 899 | break; |
||
| 900 | |||
| 901 | case HAL_ADC_MSPINIT_CB_ID : |
||
| 902 | hadc->MspInitCallback = pCallback; |
||
| 903 | break; |
||
| 904 | |||
| 905 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
| 906 | hadc->MspDeInitCallback = pCallback; |
||
| 907 | break; |
||
| 908 | |||
| 909 | default : |
||
| 910 | /* Update the error code */ |
||
| 911 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 912 | |||
| 913 | /* Return error status */ |
||
| 914 | status = HAL_ERROR; |
||
| 915 | break; |
||
| 916 | } |
||
| 917 | } |
||
| 918 | else if (HAL_ADC_STATE_RESET == hadc->State) |
||
| 919 | { |
||
| 920 | switch (CallbackID) |
||
| 921 | { |
||
| 922 | case HAL_ADC_MSPINIT_CB_ID : |
||
| 923 | hadc->MspInitCallback = pCallback; |
||
| 924 | break; |
||
| 925 | |||
| 926 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
| 927 | hadc->MspDeInitCallback = pCallback; |
||
| 928 | break; |
||
| 929 | |||
| 930 | default : |
||
| 931 | /* Update the error code */ |
||
| 932 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 933 | |||
| 934 | /* Return error status */ |
||
| 935 | status = HAL_ERROR; |
||
| 936 | break; |
||
| 937 | } |
||
| 938 | } |
||
| 939 | else |
||
| 940 | { |
||
| 941 | /* Update the error code */ |
||
| 942 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 943 | |||
| 944 | /* Return error status */ |
||
| 945 | status = HAL_ERROR; |
||
| 946 | } |
||
| 947 | |||
| 948 | return status; |
||
| 949 | } |
||
| 950 | |||
| 951 | /** |
||
| 952 | * @brief Unregister a ADC Callback |
||
| 953 | * ADC callback is redirected to the weak predefined callback |
||
| 954 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
||
| 955 | * the configuration information for the specified ADC. |
||
| 956 | * @param CallbackID ID of the callback to be unregistered |
||
| 957 | * This parameter can be one of the following values: |
||
| 958 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
||
| 959 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
||
| 960 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
||
| 961 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
||
| 962 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
||
| 963 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
||
| 964 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
||
| 965 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
||
| 966 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
||
| 967 | * @retval HAL status |
||
| 968 | */ |
||
| 969 | HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) |
||
| 970 | { |
||
| 971 | HAL_StatusTypeDef status = HAL_OK; |
||
| 972 | |||
| 973 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
||
| 974 | { |
||
| 975 | switch (CallbackID) |
||
| 976 | { |
||
| 977 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
||
| 978 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; |
||
| 979 | break; |
||
| 980 | |||
| 981 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
||
| 982 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; |
||
| 983 | break; |
||
| 984 | |||
| 985 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
||
| 986 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; |
||
| 987 | break; |
||
| 988 | |||
| 989 | case HAL_ADC_ERROR_CB_ID : |
||
| 990 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; |
||
| 991 | break; |
||
| 992 | |||
| 993 | case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : |
||
| 994 | hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; |
||
| 995 | break; |
||
| 996 | |||
| 997 | case HAL_ADC_MSPINIT_CB_ID : |
||
| 998 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
| 999 | break; |
||
| 1000 | |||
| 1001 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
| 1002 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
| 1003 | break; |
||
| 1004 | |||
| 1005 | default : |
||
| 1006 | /* Update the error code */ |
||
| 1007 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 1008 | |||
| 1009 | /* Return error status */ |
||
| 1010 | status = HAL_ERROR; |
||
| 1011 | break; |
||
| 1012 | } |
||
| 1013 | } |
||
| 1014 | else if (HAL_ADC_STATE_RESET == hadc->State) |
||
| 1015 | { |
||
| 1016 | switch (CallbackID) |
||
| 1017 | { |
||
| 1018 | case HAL_ADC_MSPINIT_CB_ID : |
||
| 1019 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
| 1020 | break; |
||
| 1021 | |||
| 1022 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
| 1023 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
| 1024 | break; |
||
| 1025 | |||
| 1026 | default : |
||
| 1027 | /* Update the error code */ |
||
| 1028 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 1029 | |||
| 1030 | /* Return error status */ |
||
| 1031 | status = HAL_ERROR; |
||
| 1032 | break; |
||
| 1033 | } |
||
| 1034 | } |
||
| 1035 | else |
||
| 1036 | { |
||
| 1037 | /* Update the error code */ |
||
| 1038 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
| 1039 | |||
| 1040 | /* Return error status */ |
||
| 1041 | status = HAL_ERROR; |
||
| 1042 | } |
||
| 1043 | |||
| 1044 | return status; |
||
| 1045 | } |
||
| 1046 | |||
| 1047 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 1048 | |||
| 1049 | /** |
||
| 1050 | * @} |
||
| 1051 | */ |
||
| 1052 | |||
| 1053 | /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions |
||
| 1054 | * @brief ADC IO operation functions |
||
| 1055 | * |
||
| 1056 | @verbatim |
||
| 1057 | =============================================================================== |
||
| 1058 | ##### IO operation functions ##### |
||
| 1059 | =============================================================================== |
||
| 1060 | [..] This section provides functions allowing to: |
||
| 1061 | (+) Start conversion of regular group. |
||
| 1062 | (+) Stop conversion of regular group. |
||
| 1063 | (+) Poll for conversion complete on regular group. |
||
| 1064 | (+) Poll for conversion event. |
||
| 1065 | (+) Get result of regular channel conversion. |
||
| 1066 | (+) Start conversion of regular group and enable interruptions. |
||
| 1067 | (+) Stop conversion of regular group and disable interruptions. |
||
| 1068 | (+) Handle ADC interrupt request |
||
| 1069 | (+) Start conversion of regular group and enable DMA transfer. |
||
| 1070 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
||
| 1071 | @endverbatim |
||
| 1072 | * @{ |
||
| 1073 | */ |
||
| 1074 | |||
| 1075 | /** |
||
| 1076 | * @brief Enables ADC, starts conversion of regular group. |
||
| 1077 | * Interruptions enabled in this function: None. |
||
| 1078 | * @param hadc ADC handle |
||
| 1079 | * @retval HAL status |
||
| 1080 | */ |
||
| 1081 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
||
| 1082 | { |
||
| 1083 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1084 | |||
| 1085 | /* Check the parameters */ |
||
| 1086 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1087 | |||
| 1088 | /* Process locked */ |
||
| 1089 | __HAL_LOCK(hadc); |
||
| 1090 | |||
| 1091 | /* Enable the ADC peripheral */ |
||
| 1092 | tmp_hal_status = ADC_Enable(hadc); |
||
| 1093 | |||
| 1094 | /* Start conversion if ADC is effectively enabled */ |
||
| 1095 | if (tmp_hal_status == HAL_OK) |
||
| 1096 | { |
||
| 1097 | /* Set ADC state */ |
||
| 1098 | /* - Clear state bitfield related to regular group conversion results */ |
||
| 1099 | /* - Set state bitfield related to regular group operation */ |
||
| 1100 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1101 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
||
| 1102 | HAL_ADC_STATE_REG_BUSY); |
||
| 1103 | |||
| 1104 | /* If conversions on group regular are also triggering group injected, */ |
||
| 1105 | /* update ADC state. */ |
||
| 1106 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
||
| 1107 | { |
||
| 1108 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
| 1109 | } |
||
| 1110 | |||
| 1111 | /* State machine update: Check if an injected conversion is ongoing */ |
||
| 1112 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 1113 | { |
||
| 1114 | /* Reset ADC error code fields related to conversions on group regular */ |
||
| 1115 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
||
| 1116 | } |
||
| 1117 | else |
||
| 1118 | { |
||
| 1119 | /* Reset ADC all error code fields */ |
||
| 1120 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 1121 | } |
||
| 1122 | |||
| 1123 | /* Process unlocked */ |
||
| 1124 | /* Unlock before starting ADC conversions: in case of potential */ |
||
| 1125 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
| 1126 | __HAL_UNLOCK(hadc); |
||
| 1127 | |||
| 1128 | /* Clear regular group conversion flag and overrun flag */ |
||
| 1129 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
||
| 1130 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
||
| 1131 | |||
| 1132 | /* Enable conversion of regular group. */ |
||
| 1133 | /* If software start has been selected, conversion starts immediately. */ |
||
| 1134 | /* If external trigger has been selected, conversion will start at next */ |
||
| 1135 | /* trigger event. */ |
||
| 1136 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
||
| 1137 | { |
||
| 1138 | /* Start ADC conversion on regular group */ |
||
| 1139 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
||
| 1140 | } |
||
| 1141 | } |
||
| 1142 | |||
| 1143 | /* Return function status */ |
||
| 1144 | return tmp_hal_status; |
||
| 1145 | } |
||
| 1146 | |||
| 1147 | /** |
||
| 1148 | * @brief Stop ADC conversion of regular group (and injected channels in |
||
| 1149 | * case of auto_injection mode), disable ADC peripheral. |
||
| 1150 | * @note: ADC peripheral disable is forcing stop of potential |
||
| 1151 | * conversion on injected group. If injected group is under use, it |
||
| 1152 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
||
| 1153 | * @param hadc ADC handle |
||
| 1154 | * @retval HAL status. |
||
| 1155 | */ |
||
| 1156 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
||
| 1157 | { |
||
| 1158 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1159 | |||
| 1160 | /* Check the parameters */ |
||
| 1161 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1162 | |||
| 1163 | /* Process locked */ |
||
| 1164 | __HAL_LOCK(hadc); |
||
| 1165 | |||
| 1166 | /* Stop potential conversion on going, on regular and injected groups */ |
||
| 1167 | /* Disable ADC peripheral */ |
||
| 1168 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
| 1169 | |||
| 1170 | /* Check if ADC is effectively disabled */ |
||
| 1171 | if (tmp_hal_status == HAL_OK) |
||
| 1172 | { |
||
| 1173 | /* Set ADC state */ |
||
| 1174 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1175 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
| 1176 | HAL_ADC_STATE_READY); |
||
| 1177 | } |
||
| 1178 | |||
| 1179 | /* Process unlocked */ |
||
| 1180 | __HAL_UNLOCK(hadc); |
||
| 1181 | |||
| 1182 | /* Return function status */ |
||
| 1183 | return tmp_hal_status; |
||
| 1184 | } |
||
| 1185 | |||
| 1186 | /** |
||
| 1187 | * @brief Wait for regular group conversion to be completed. |
||
| 1188 | * @note ADC conversion flags EOS (end of sequence) and EOC (end of |
||
| 1189 | * conversion) are cleared by this function, with an exception: |
||
| 1190 | * if low power feature "LowPowerAutoWait" is enabled, flags are |
||
| 1191 | * not cleared to not interfere with this feature until data register |
||
| 1192 | * is read using function HAL_ADC_GetValue(). |
||
| 1193 | * @note This function cannot be used in a particular setup: ADC configured |
||
| 1194 | * in DMA mode and polling for end of each conversion (ADC init |
||
| 1195 | * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). |
||
| 1196 | * In this case, DMA resets the flag EOC and polling cannot be |
||
| 1197 | * performed on each conversion. Nevertheless, polling can still |
||
| 1198 | * be performed on the complete sequence (ADC init |
||
| 1199 | * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). |
||
| 1200 | * @param hadc ADC handle |
||
| 1201 | * @param Timeout Timeout value in millisecond. |
||
| 1202 | * @retval HAL status |
||
| 1203 | */ |
||
| 1204 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
||
| 1205 | { |
||
| 1206 | uint32_t tickstart = 0; |
||
| 1207 | |||
| 1208 | /* Check the parameters */ |
||
| 1209 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1210 | |||
| 1211 | /* Verification that ADC configuration is compliant with polling for */ |
||
| 1212 | /* each conversion: */ |
||
| 1213 | /* Particular case is ADC configured in DMA mode and ADC sequencer with */ |
||
| 1214 | /* several ranks and polling for end of each conversion. */ |
||
| 1215 | /* For code simplicity sake, this particular case is generalized to */ |
||
| 1216 | /* ADC configured in DMA mode and and polling for end of each conversion. */ |
||
| 1217 | if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && |
||
| 1218 | HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) |
||
| 1219 | { |
||
| 1220 | /* Update ADC state machine to error */ |
||
| 1221 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
| 1222 | |||
| 1223 | /* Process unlocked */ |
||
| 1224 | __HAL_UNLOCK(hadc); |
||
| 1225 | |||
| 1226 | return HAL_ERROR; |
||
| 1227 | } |
||
| 1228 | |||
| 1229 | /* Get tick count */ |
||
| 1230 | tickstart = HAL_GetTick(); |
||
| 1231 | |||
| 1232 | /* Wait until End of Conversion flag is raised */ |
||
| 1233 | while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) |
||
| 1234 | { |
||
| 1235 | /* Check if timeout is disabled (set to infinite wait) */ |
||
| 1236 | if(Timeout != HAL_MAX_DELAY) |
||
| 1237 | { |
||
| 1238 | if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) |
||
| 1239 | { |
||
| 1240 | /* New check to avoid false timeout detection in case of preemption */ |
||
| 1241 | if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) |
||
| 1242 | { |
||
| 1243 | /* Update ADC state machine to timeout */ |
||
| 1244 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
||
| 1245 | |||
| 1246 | /* Process unlocked */ |
||
| 1247 | __HAL_UNLOCK(hadc); |
||
| 1248 | |||
| 1249 | return HAL_TIMEOUT; |
||
| 1250 | } |
||
| 1251 | } |
||
| 1252 | } |
||
| 1253 | } |
||
| 1254 | |||
| 1255 | /* Clear end of conversion flag of regular group if low power feature */ |
||
| 1256 | /* "Auto Wait" is disabled, to not interfere with this feature until data */ |
||
| 1257 | /* register is read using function HAL_ADC_GetValue(). */ |
||
| 1258 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
||
| 1259 | { |
||
| 1260 | /* Clear regular group conversion flag */ |
||
| 1261 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
||
| 1262 | } |
||
| 1263 | |||
| 1264 | /* Update ADC state machine */ |
||
| 1265 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
| 1266 | |||
| 1267 | /* Determine whether any further conversion upcoming on group regular */ |
||
| 1268 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
| 1269 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
||
| 1270 | /* The test of scan sequence on going is done either with scan */ |
||
| 1271 | /* sequence disabled or with end of conversion flag set to */ |
||
| 1272 | /* of end of sequence. */ |
||
| 1273 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
| 1274 | (hadc->Init.ContinuousConvMode == DISABLE) && |
||
| 1275 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
||
| 1276 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
||
| 1277 | { |
||
| 1278 | /* Set ADC state */ |
||
| 1279 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
||
| 1280 | |||
| 1281 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 1282 | { |
||
| 1283 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
| 1284 | } |
||
| 1285 | } |
||
| 1286 | |||
| 1287 | /* Return ADC state */ |
||
| 1288 | return HAL_OK; |
||
| 1289 | } |
||
| 1290 | |||
| 1291 | /** |
||
| 1292 | * @brief Poll for conversion event. |
||
| 1293 | * @param hadc ADC handle |
||
| 1294 | * @param EventType the ADC event type. |
||
| 1295 | * This parameter can be one of the following values: |
||
| 1296 | * @arg ADC_AWD_EVENT: ADC Analog watchdog event. |
||
| 1297 | * @arg ADC_OVR_EVENT: ADC Overrun event. |
||
| 1298 | * @param Timeout Timeout value in millisecond. |
||
| 1299 | * @retval HAL status |
||
| 1300 | */ |
||
| 1301 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
||
| 1302 | { |
||
| 1303 | uint32_t tickstart = 0; |
||
| 1304 | |||
| 1305 | /* Check the parameters */ |
||
| 1306 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1307 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
||
| 1308 | |||
| 1309 | /* Get tick count */ |
||
| 1310 | tickstart = HAL_GetTick(); |
||
| 1311 | |||
| 1312 | /* Check selected event flag */ |
||
| 1313 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
||
| 1314 | { |
||
| 1315 | /* Check if timeout is disabled (set to infinite wait) */ |
||
| 1316 | if(Timeout != HAL_MAX_DELAY) |
||
| 1317 | { |
||
| 1318 | if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) |
||
| 1319 | { |
||
| 1320 | /* New check to avoid false timeout detection in case of preemption */ |
||
| 1321 | if(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
||
| 1322 | { |
||
| 1323 | /* Update ADC state machine to timeout */ |
||
| 1324 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
||
| 1325 | |||
| 1326 | /* Process unlocked */ |
||
| 1327 | __HAL_UNLOCK(hadc); |
||
| 1328 | |||
| 1329 | return HAL_TIMEOUT; |
||
| 1330 | } |
||
| 1331 | } |
||
| 1332 | } |
||
| 1333 | } |
||
| 1334 | |||
| 1335 | switch(EventType) |
||
| 1336 | { |
||
| 1337 | /* Analog watchdog (level out of window) event */ |
||
| 1338 | case ADC_AWD_EVENT: |
||
| 1339 | /* Set ADC state */ |
||
| 1340 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
||
| 1341 | |||
| 1342 | /* Clear ADC analog watchdog flag */ |
||
| 1343 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
||
| 1344 | break; |
||
| 1345 | |||
| 1346 | /* Overrun event */ |
||
| 1347 | default: /* Case ADC_OVR_EVENT */ |
||
| 1348 | /* Note: On STM32L1, ADC overrun can be set through other parameters */ |
||
| 1349 | /* refer to description of parameter "EOCSelection" for more */ |
||
| 1350 | /* details. */ |
||
| 1351 | |||
| 1352 | /* Set ADC state */ |
||
| 1353 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); |
||
| 1354 | /* Set ADC error code to overrun */ |
||
| 1355 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
||
| 1356 | |||
| 1357 | /* Clear ADC overrun flag */ |
||
| 1358 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
||
| 1359 | break; |
||
| 1360 | } |
||
| 1361 | |||
| 1362 | /* Return ADC state */ |
||
| 1363 | return HAL_OK; |
||
| 1364 | } |
||
| 1365 | |||
| 1366 | /** |
||
| 1367 | * @brief Enables ADC, starts conversion of regular group with interruption. |
||
| 1368 | * Interruptions enabled in this function: |
||
| 1369 | * - EOC (end of conversion of regular group) |
||
| 1370 | * - overrun |
||
| 1371 | * Each of these interruptions has its dedicated callback function. |
||
| 1372 | * @param hadc ADC handle |
||
| 1373 | * @retval HAL status |
||
| 1374 | */ |
||
| 1375 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
||
| 1376 | { |
||
| 1377 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1378 | |||
| 1379 | /* Check the parameters */ |
||
| 1380 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1381 | |||
| 1382 | /* Process locked */ |
||
| 1383 | __HAL_LOCK(hadc); |
||
| 1384 | |||
| 1385 | /* Enable the ADC peripheral */ |
||
| 1386 | tmp_hal_status = ADC_Enable(hadc); |
||
| 1387 | |||
| 1388 | /* Start conversion if ADC is effectively enabled */ |
||
| 1389 | if (tmp_hal_status == HAL_OK) |
||
| 1390 | { |
||
| 1391 | /* Set ADC state */ |
||
| 1392 | /* - Clear state bitfield related to regular group conversion results */ |
||
| 1393 | /* - Set state bitfield related to regular group operation */ |
||
| 1394 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1395 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
||
| 1396 | HAL_ADC_STATE_REG_BUSY); |
||
| 1397 | |||
| 1398 | /* If conversions on group regular are also triggering group injected, */ |
||
| 1399 | /* update ADC state. */ |
||
| 1400 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
||
| 1401 | { |
||
| 1402 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
| 1403 | } |
||
| 1404 | |||
| 1405 | /* State machine update: Check if an injected conversion is ongoing */ |
||
| 1406 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 1407 | { |
||
| 1408 | /* Reset ADC error code fields related to conversions on group regular */ |
||
| 1409 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
||
| 1410 | } |
||
| 1411 | else |
||
| 1412 | { |
||
| 1413 | /* Reset ADC all error code fields */ |
||
| 1414 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 1415 | } |
||
| 1416 | |||
| 1417 | /* Process unlocked */ |
||
| 1418 | /* Unlock before starting ADC conversions: in case of potential */ |
||
| 1419 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
| 1420 | __HAL_UNLOCK(hadc); |
||
| 1421 | |||
| 1422 | /* Clear regular group conversion flag and overrun flag */ |
||
| 1423 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
||
| 1424 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
||
| 1425 | |||
| 1426 | /* Enable end of conversion interrupt for regular group */ |
||
| 1427 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); |
||
| 1428 | |||
| 1429 | /* Enable conversion of regular group. */ |
||
| 1430 | /* If software start has been selected, conversion starts immediately. */ |
||
| 1431 | /* If external trigger has been selected, conversion will start at next */ |
||
| 1432 | /* trigger event. */ |
||
| 1433 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
||
| 1434 | { |
||
| 1435 | /* Start ADC conversion on regular group */ |
||
| 1436 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
||
| 1437 | } |
||
| 1438 | } |
||
| 1439 | |||
| 1440 | /* Return function status */ |
||
| 1441 | return tmp_hal_status; |
||
| 1442 | } |
||
| 1443 | |||
| 1444 | /** |
||
| 1445 | * @brief Stop ADC conversion of regular group (and injected group in |
||
| 1446 | * case of auto_injection mode), disable interrution of |
||
| 1447 | * end-of-conversion, disable ADC peripheral. |
||
| 1448 | * @param hadc ADC handle |
||
| 1449 | * @retval None |
||
| 1450 | */ |
||
| 1451 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
||
| 1452 | { |
||
| 1453 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1454 | |||
| 1455 | /* Check the parameters */ |
||
| 1456 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1457 | |||
| 1458 | /* Process locked */ |
||
| 1459 | __HAL_LOCK(hadc); |
||
| 1460 | |||
| 1461 | /* Stop potential conversion on going, on regular and injected groups */ |
||
| 1462 | /* Disable ADC peripheral */ |
||
| 1463 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
| 1464 | |||
| 1465 | /* Check if ADC is effectively disabled */ |
||
| 1466 | if (tmp_hal_status == HAL_OK) |
||
| 1467 | { |
||
| 1468 | /* Disable ADC end of conversion interrupt for regular group */ |
||
| 1469 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
||
| 1470 | |||
| 1471 | /* Set ADC state */ |
||
| 1472 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1473 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
| 1474 | HAL_ADC_STATE_READY); |
||
| 1475 | } |
||
| 1476 | |||
| 1477 | /* Process unlocked */ |
||
| 1478 | __HAL_UNLOCK(hadc); |
||
| 1479 | |||
| 1480 | /* Return function status */ |
||
| 1481 | return tmp_hal_status; |
||
| 1482 | } |
||
| 1483 | |||
| 1484 | /** |
||
| 1485 | * @brief Enables ADC, starts conversion of regular group and transfers result |
||
| 1486 | * through DMA. |
||
| 1487 | * Interruptions enabled in this function: |
||
| 1488 | * - DMA transfer complete |
||
| 1489 | * - DMA half transfer |
||
| 1490 | * - overrun |
||
| 1491 | * Each of these interruptions has its dedicated callback function. |
||
| 1492 | * @param hadc ADC handle |
||
| 1493 | * @param pData The destination Buffer address. |
||
| 1494 | * @param Length The length of data to be transferred from ADC peripheral to memory. |
||
| 1495 | * @retval None |
||
| 1496 | */ |
||
| 1497 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
||
| 1498 | { |
||
| 1499 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1500 | |||
| 1501 | /* Check the parameters */ |
||
| 1502 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1503 | |||
| 1504 | /* Process locked */ |
||
| 1505 | __HAL_LOCK(hadc); |
||
| 1506 | |||
| 1507 | /* Enable the ADC peripheral */ |
||
| 1508 | tmp_hal_status = ADC_Enable(hadc); |
||
| 1509 | |||
| 1510 | /* Start conversion if ADC is effectively enabled */ |
||
| 1511 | if (tmp_hal_status == HAL_OK) |
||
| 1512 | { |
||
| 1513 | /* Set ADC state */ |
||
| 1514 | /* - Clear state bitfield related to regular group conversion results */ |
||
| 1515 | /* - Set state bitfield related to regular group operation */ |
||
| 1516 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1517 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
||
| 1518 | HAL_ADC_STATE_REG_BUSY); |
||
| 1519 | |||
| 1520 | /* If conversions on group regular are also triggering group injected, */ |
||
| 1521 | /* update ADC state. */ |
||
| 1522 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
||
| 1523 | { |
||
| 1524 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
| 1525 | } |
||
| 1526 | |||
| 1527 | /* State machine update: Check if an injected conversion is ongoing */ |
||
| 1528 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 1529 | { |
||
| 1530 | /* Reset ADC error code fields related to conversions on group regular */ |
||
| 1531 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
||
| 1532 | } |
||
| 1533 | else |
||
| 1534 | { |
||
| 1535 | /* Reset ADC all error code fields */ |
||
| 1536 | ADC_CLEAR_ERRORCODE(hadc); |
||
| 1537 | } |
||
| 1538 | |||
| 1539 | /* Process unlocked */ |
||
| 1540 | /* Unlock before starting ADC conversions: in case of potential */ |
||
| 1541 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
| 1542 | __HAL_UNLOCK(hadc); |
||
| 1543 | |||
| 1544 | /* Set the DMA transfer complete callback */ |
||
| 1545 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
||
| 1546 | |||
| 1547 | /* Set the DMA half transfer complete callback */ |
||
| 1548 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
||
| 1549 | |||
| 1550 | /* Set the DMA error callback */ |
||
| 1551 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
||
| 1552 | |||
| 1553 | |||
| 1554 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
||
| 1555 | /* start (in case of SW start): */ |
||
| 1556 | |||
| 1557 | /* Clear regular group conversion flag and overrun flag */ |
||
| 1558 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
||
| 1559 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
||
| 1560 | |||
| 1561 | /* Enable ADC overrun interrupt */ |
||
| 1562 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
||
| 1563 | |||
| 1564 | /* Enable ADC DMA mode */ |
||
| 1565 | hadc->Instance->CR2 |= ADC_CR2_DMA; |
||
| 1566 | |||
| 1567 | /* Start the DMA channel */ |
||
| 1568 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
||
| 1569 | |||
| 1570 | /* Enable conversion of regular group. */ |
||
| 1571 | /* If software start has been selected, conversion starts immediately. */ |
||
| 1572 | /* If external trigger has been selected, conversion will start at next */ |
||
| 1573 | /* trigger event. */ |
||
| 1574 | /* Note: Alternate trigger for single conversion could be to force an */ |
||
| 1575 | /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ |
||
| 1576 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
||
| 1577 | { |
||
| 1578 | /* Start ADC conversion on regular group */ |
||
| 1579 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
||
| 1580 | } |
||
| 1581 | } |
||
| 1582 | |||
| 1583 | /* Return function status */ |
||
| 1584 | return tmp_hal_status; |
||
| 1585 | } |
||
| 1586 | |||
| 1587 | /** |
||
| 1588 | * @brief Stop ADC conversion of regular group (and injected group in |
||
| 1589 | * case of auto_injection mode), disable ADC DMA transfer, disable |
||
| 1590 | * ADC peripheral. |
||
| 1591 | * @note: ADC peripheral disable is forcing stop of potential |
||
| 1592 | * conversion on injected group. If injected group is under use, it |
||
| 1593 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
||
| 1594 | * @param hadc ADC handle |
||
| 1595 | * @retval HAL status. |
||
| 1596 | */ |
||
| 1597 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
||
| 1598 | { |
||
| 1599 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1600 | |||
| 1601 | /* Check the parameters */ |
||
| 1602 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1603 | |||
| 1604 | /* Process locked */ |
||
| 1605 | __HAL_LOCK(hadc); |
||
| 1606 | |||
| 1607 | /* Stop potential conversion on going, on regular and injected groups */ |
||
| 1608 | /* Disable ADC peripheral */ |
||
| 1609 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
| 1610 | |||
| 1611 | /* Check if ADC is effectively disabled */ |
||
| 1612 | if (tmp_hal_status == HAL_OK) |
||
| 1613 | { |
||
| 1614 | /* Disable ADC DMA mode */ |
||
| 1615 | hadc->Instance->CR2 &= ~ADC_CR2_DMA; |
||
| 1616 | |||
| 1617 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
||
| 1618 | /* DMA transfer is on going) */ |
||
| 1619 | if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) |
||
| 1620 | { |
||
| 1621 | HAL_DMA_Abort(hadc->DMA_Handle); |
||
| 1622 | |||
| 1623 | /* Check if DMA channel effectively disabled */ |
||
| 1624 | if (tmp_hal_status != HAL_OK) |
||
| 1625 | { |
||
| 1626 | /* Update ADC state machine to error */ |
||
| 1627 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
||
| 1628 | } |
||
| 1629 | } |
||
| 1630 | |||
| 1631 | /* Set ADC state */ |
||
| 1632 | ADC_STATE_CLR_SET(hadc->State, |
||
| 1633 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
| 1634 | HAL_ADC_STATE_READY); |
||
| 1635 | |||
| 1636 | /* Disable ADC overrun interrupt */ |
||
| 1637 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
||
| 1638 | } |
||
| 1639 | |||
| 1640 | /* Process unlocked */ |
||
| 1641 | __HAL_UNLOCK(hadc); |
||
| 1642 | |||
| 1643 | /* Return function status */ |
||
| 1644 | return tmp_hal_status; |
||
| 1645 | } |
||
| 1646 | |||
| 1647 | /** |
||
| 1648 | * @brief Get ADC regular group conversion result. |
||
| 1649 | * @note Reading register DR automatically clears ADC flag EOC |
||
| 1650 | * (ADC group regular end of unitary conversion). |
||
| 1651 | * @note This function does not clear ADC flag EOS |
||
| 1652 | * (ADC group regular end of sequence conversion). |
||
| 1653 | * Occurrence of flag EOS rising: |
||
| 1654 | * - If sequencer is composed of 1 rank, flag EOS is equivalent |
||
| 1655 | * to flag EOC. |
||
| 1656 | * - If sequencer is composed of several ranks, during the scan |
||
| 1657 | * sequence flag EOC only is raised, at the end of the scan sequence |
||
| 1658 | * both flags EOC and EOS are raised. |
||
| 1659 | * To clear this flag, either use function: |
||
| 1660 | * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming |
||
| 1661 | * model polling: @ref HAL_ADC_PollForConversion() |
||
| 1662 | * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). |
||
| 1663 | * @param hadc ADC handle |
||
| 1664 | * @retval ADC group regular conversion data |
||
| 1665 | */ |
||
| 1666 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
||
| 1667 | { |
||
| 1668 | /* Check the parameters */ |
||
| 1669 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1670 | |||
| 1671 | /* Note: EOC flag is not cleared here by software because automatically */ |
||
| 1672 | /* cleared by hardware when reading register DR. */ |
||
| 1673 | |||
| 1674 | /* Return ADC converted value */ |
||
| 1675 | return hadc->Instance->DR; |
||
| 1676 | } |
||
| 1677 | |||
| 1678 | /** |
||
| 1679 | * @brief Handles ADC interrupt request |
||
| 1680 | * @param hadc ADC handle |
||
| 1681 | * @retval None |
||
| 1682 | */ |
||
| 1683 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
||
| 1684 | { |
||
| 1685 | uint32_t tmp_sr = hadc->Instance->SR; |
||
| 1686 | uint32_t tmp_cr1 = hadc->Instance->CR1; |
||
| 1687 | |||
| 1688 | /* Check the parameters */ |
||
| 1689 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1690 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
||
| 1691 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
||
| 1692 | |||
| 1693 | |||
| 1694 | /* ========== Check End of Conversion flag for regular group ========== */ |
||
| 1695 | if((tmp_cr1 & ADC_IT_EOC) == ADC_IT_EOC) |
||
| 1696 | { |
||
| 1697 | if((tmp_sr & ADC_FLAG_EOC) == ADC_FLAG_EOC) |
||
| 1698 | { |
||
| 1699 | /* Update state machine on conversion status if not in error state */ |
||
| 1700 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
||
| 1701 | { |
||
| 1702 | /* Set ADC state */ |
||
| 1703 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
| 1704 | } |
||
| 1705 | |||
| 1706 | /* Determine whether any further conversion upcoming on group regular */ |
||
| 1707 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
| 1708 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
||
| 1709 | /* The test of scan sequence on going is done either with scan */ |
||
| 1710 | /* sequence disabled or with end of conversion flag set to */ |
||
| 1711 | /* of end of sequence. */ |
||
| 1712 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
| 1713 | (hadc->Init.ContinuousConvMode == DISABLE) && |
||
| 1714 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
||
| 1715 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
||
| 1716 | { |
||
| 1717 | /* Disable ADC end of single conversion interrupt on group regular */ |
||
| 1718 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
||
| 1719 | /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ |
||
| 1720 | /* by overrun IRQ process below. */ |
||
| 1721 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
||
| 1722 | |||
| 1723 | /* Set ADC state */ |
||
| 1724 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
||
| 1725 | |||
| 1726 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 1727 | { |
||
| 1728 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
| 1729 | } |
||
| 1730 | } |
||
| 1731 | |||
| 1732 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 1733 | hadc->ConvCpltCallback(hadc); |
||
| 1734 | #else |
||
| 1735 | HAL_ADC_ConvCpltCallback(hadc); |
||
| 1736 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 1737 | |||
| 1738 | /* Clear regular group conversion flag */ |
||
| 1739 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
||
| 1740 | } |
||
| 1741 | } |
||
| 1742 | |||
| 1743 | /* ========== Check End of Conversion flag for injected group ========== */ |
||
| 1744 | if((tmp_cr1 & ADC_IT_JEOC) == ADC_IT_JEOC) |
||
| 1745 | { |
||
| 1746 | if((tmp_sr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) |
||
| 1747 | { |
||
| 1748 | /* Update state machine on conversion status if not in error state */ |
||
| 1749 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
||
| 1750 | { |
||
| 1751 | /* Set ADC state */ |
||
| 1752 | SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); |
||
| 1753 | } |
||
| 1754 | |||
| 1755 | /* Determine whether any further conversion upcoming on group injected */ |
||
| 1756 | /* by external trigger, scan sequence on going or by automatic injected */ |
||
| 1757 | /* conversion from group regular (same conditions as group regular */ |
||
| 1758 | /* interruption disabling above). */ |
||
| 1759 | if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && |
||
| 1760 | (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || |
||
| 1761 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && |
||
| 1762 | (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && |
||
| 1763 | (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
| 1764 | (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) |
||
| 1765 | { |
||
| 1766 | /* Disable ADC end of single conversion interrupt on group injected */ |
||
| 1767 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
||
| 1768 | |||
| 1769 | /* Set ADC state */ |
||
| 1770 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); |
||
| 1771 | |||
| 1772 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) |
||
| 1773 | { |
||
| 1774 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
| 1775 | } |
||
| 1776 | } |
||
| 1777 | |||
| 1778 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 1779 | hadc->InjectedConvCpltCallback(hadc); |
||
| 1780 | #else |
||
| 1781 | HAL_ADCEx_InjectedConvCpltCallback(hadc); |
||
| 1782 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 1783 | |||
| 1784 | /* Clear injected group conversion flag */ |
||
| 1785 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); |
||
| 1786 | } |
||
| 1787 | } |
||
| 1788 | |||
| 1789 | /* ========== Check Analog watchdog flags ========== */ |
||
| 1790 | if((tmp_cr1 & ADC_IT_AWD) == ADC_IT_AWD) |
||
| 1791 | { |
||
| 1792 | if((tmp_sr & ADC_FLAG_AWD) == ADC_FLAG_AWD) |
||
| 1793 | { |
||
| 1794 | /* Set ADC state */ |
||
| 1795 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
||
| 1796 | |||
| 1797 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 1798 | hadc->LevelOutOfWindowCallback(hadc); |
||
| 1799 | #else |
||
| 1800 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
||
| 1801 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 1802 | |||
| 1803 | /* Clear the ADC analog watchdog flag */ |
||
| 1804 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
||
| 1805 | } |
||
| 1806 | } |
||
| 1807 | |||
| 1808 | /* ========== Check Overrun flag ========== */ |
||
| 1809 | if((tmp_cr1 & ADC_IT_OVR) == ADC_IT_OVR) |
||
| 1810 | { |
||
| 1811 | if((tmp_sr & ADC_FLAG_OVR) == ADC_FLAG_OVR) |
||
| 1812 | { |
||
| 1813 | /* Note: On STM32L1, ADC overrun can be set through other parameters */ |
||
| 1814 | /* refer to description of parameter "EOCSelection" for more */ |
||
| 1815 | /* details. */ |
||
| 1816 | |||
| 1817 | /* Set ADC error code to overrun */ |
||
| 1818 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
||
| 1819 | |||
| 1820 | /* Clear ADC overrun flag */ |
||
| 1821 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
||
| 1822 | |||
| 1823 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 1824 | hadc->ErrorCallback(hadc); |
||
| 1825 | #else |
||
| 1826 | HAL_ADC_ErrorCallback(hadc); |
||
| 1827 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 1828 | |||
| 1829 | /* Clear the Overrun flag */ |
||
| 1830 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
||
| 1831 | } |
||
| 1832 | } |
||
| 1833 | |||
| 1834 | } |
||
| 1835 | |||
| 1836 | /** |
||
| 1837 | * @brief Conversion complete callback in non blocking mode |
||
| 1838 | * @param hadc ADC handle |
||
| 1839 | * @retval None |
||
| 1840 | */ |
||
| 1841 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
||
| 1842 | { |
||
| 1843 | /* Prevent unused argument(s) compilation warning */ |
||
| 1844 | UNUSED(hadc); |
||
| 1845 | |||
| 1846 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 1847 | function HAL_ADC_ConvCpltCallback must be implemented in the user file. |
||
| 1848 | */ |
||
| 1849 | } |
||
| 1850 | |||
| 1851 | /** |
||
| 1852 | * @brief Conversion DMA half-transfer callback in non blocking mode |
||
| 1853 | * @param hadc ADC handle |
||
| 1854 | * @retval None |
||
| 1855 | */ |
||
| 1856 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
||
| 1857 | { |
||
| 1858 | /* Prevent unused argument(s) compilation warning */ |
||
| 1859 | UNUSED(hadc); |
||
| 1860 | |||
| 1861 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 1862 | function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. |
||
| 1863 | */ |
||
| 1864 | } |
||
| 1865 | |||
| 1866 | /** |
||
| 1867 | * @brief Analog watchdog callback in non blocking mode. |
||
| 1868 | * @param hadc ADC handle |
||
| 1869 | * @retval None |
||
| 1870 | */ |
||
| 1871 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
||
| 1872 | { |
||
| 1873 | /* Prevent unused argument(s) compilation warning */ |
||
| 1874 | UNUSED(hadc); |
||
| 1875 | |||
| 1876 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 1877 | function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. |
||
| 1878 | */ |
||
| 1879 | } |
||
| 1880 | |||
| 1881 | /** |
||
| 1882 | * @brief ADC error callback in non blocking mode |
||
| 1883 | * (ADC conversion with interruption or transfer by DMA) |
||
| 1884 | * @note In case of error due to overrun when using ADC with DMA transfer |
||
| 1885 | * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): |
||
| 1886 | * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". |
||
| 1887 | * - If needed, restart a new ADC conversion using function |
||
| 1888 | * "HAL_ADC_Start_DMA()" |
||
| 1889 | * (this function is also clearing overrun flag) |
||
| 1890 | * @param hadc ADC handle |
||
| 1891 | * @retval None |
||
| 1892 | */ |
||
| 1893 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
||
| 1894 | { |
||
| 1895 | /* Prevent unused argument(s) compilation warning */ |
||
| 1896 | UNUSED(hadc); |
||
| 1897 | |||
| 1898 | /* NOTE : This function should not be modified. When the callback is needed, |
||
| 1899 | function HAL_ADC_ErrorCallback must be implemented in the user file. |
||
| 1900 | */ |
||
| 1901 | } |
||
| 1902 | |||
| 1903 | |||
| 1904 | /** |
||
| 1905 | * @} |
||
| 1906 | */ |
||
| 1907 | |||
| 1908 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
||
| 1909 | * @brief Peripheral Control functions |
||
| 1910 | * |
||
| 1911 | @verbatim |
||
| 1912 | =============================================================================== |
||
| 1913 | ##### Peripheral Control functions ##### |
||
| 1914 | =============================================================================== |
||
| 1915 | [..] This section provides functions allowing to: |
||
| 1916 | (+) Configure channels on regular group |
||
| 1917 | (+) Configure the analog watchdog |
||
| 1918 | |||
| 1919 | @endverbatim |
||
| 1920 | * @{ |
||
| 1921 | */ |
||
| 1922 | |||
| 1923 | /** |
||
| 1924 | * @brief Configures the the selected channel to be linked to the regular |
||
| 1925 | * group. |
||
| 1926 | * @note In case of usage of internal measurement channels: |
||
| 1927 | * Vbat/VrefInt/TempSensor. |
||
| 1928 | * These internal paths can be be disabled using function |
||
| 1929 | * HAL_ADC_DeInit(). |
||
| 1930 | * @note Possibility to update parameters on the fly: |
||
| 1931 | * This function initializes channel into regular group, following |
||
| 1932 | * calls to this function can be used to reconfigure some parameters |
||
| 1933 | * of structure "ADC_ChannelConfTypeDef" on the fly, without resetting |
||
| 1934 | * the ADC. |
||
| 1935 | * The setting of these parameters is conditioned to ADC state. |
||
| 1936 | * For parameters constraints, see comments of structure |
||
| 1937 | * "ADC_ChannelConfTypeDef". |
||
| 1938 | * @param hadc ADC handle |
||
| 1939 | * @param sConfig Structure of ADC channel for regular group. |
||
| 1940 | * @retval HAL status |
||
| 1941 | */ |
||
| 1942 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
||
| 1943 | { |
||
| 1944 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
| 1945 | __IO uint32_t wait_loop_index = 0; |
||
| 1946 | |||
| 1947 | /* Check the parameters */ |
||
| 1948 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 1949 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
||
| 1950 | assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); |
||
| 1951 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
||
| 1952 | |||
| 1953 | /* Process locked */ |
||
| 1954 | __HAL_LOCK(hadc); |
||
| 1955 | |||
| 1956 | |||
| 1957 | /* Regular sequence configuration */ |
||
| 1958 | /* For Rank 1 to 6 */ |
||
| 1959 | if (sConfig->Rank < 7) |
||
| 1960 | { |
||
| 1961 | MODIFY_REG(hadc->Instance->SQR5, |
||
| 1962 | ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank), |
||
| 1963 | ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) ); |
||
| 1964 | } |
||
| 1965 | /* For Rank 7 to 12 */ |
||
| 1966 | else if (sConfig->Rank < 13) |
||
| 1967 | { |
||
| 1968 | MODIFY_REG(hadc->Instance->SQR4, |
||
| 1969 | ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank), |
||
| 1970 | ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) ); |
||
| 1971 | } |
||
| 1972 | /* For Rank 13 to 18 */ |
||
| 1973 | else if (sConfig->Rank < 19) |
||
| 1974 | { |
||
| 1975 | MODIFY_REG(hadc->Instance->SQR3, |
||
| 1976 | ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank), |
||
| 1977 | ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); |
||
| 1978 | } |
||
| 1979 | /* For Rank 19 to 24 */ |
||
| 1980 | else if (sConfig->Rank < 25) |
||
| 1981 | { |
||
| 1982 | MODIFY_REG(hadc->Instance->SQR2, |
||
| 1983 | ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank), |
||
| 1984 | ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); |
||
| 1985 | } |
||
| 1986 | /* For Rank 25 to 28 */ |
||
| 1987 | else |
||
| 1988 | { |
||
| 1989 | MODIFY_REG(hadc->Instance->SQR1, |
||
| 1990 | ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank), |
||
| 1991 | ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); |
||
| 1992 | } |
||
| 1993 | |||
| 1994 | |||
| 1995 | /* Channel sampling time configuration */ |
||
| 1996 | /* For channels 0 to 9 */ |
||
| 1997 | if (sConfig->Channel < ADC_CHANNEL_10) |
||
| 1998 | { |
||
| 1999 | MODIFY_REG(hadc->Instance->SMPR3, |
||
| 2000 | ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel), |
||
| 2001 | ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) ); |
||
| 2002 | } |
||
| 2003 | /* For channels 10 to 19 */ |
||
| 2004 | else if (sConfig->Channel < ADC_CHANNEL_20) |
||
| 2005 | { |
||
| 2006 | MODIFY_REG(hadc->Instance->SMPR2, |
||
| 2007 | ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel), |
||
| 2008 | ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); |
||
| 2009 | } |
||
| 2010 | /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ |
||
| 2011 | /* For channels 20 to 29 for devices Cat4, Cat.5 */ |
||
| 2012 | else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX) |
||
| 2013 | { |
||
| 2014 | MODIFY_REG(hadc->Instance->SMPR1, |
||
| 2015 | ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel), |
||
| 2016 | ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); |
||
| 2017 | } |
||
| 2018 | /* For channels 30 to 31 for devices Cat4, Cat.5 */ |
||
| 2019 | else |
||
| 2020 | { |
||
| 2021 | ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel); |
||
| 2022 | } |
||
| 2023 | |||
| 2024 | /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ |
||
| 2025 | /* and VREFINT measurement path. */ |
||
| 2026 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || |
||
| 2027 | (sConfig->Channel == ADC_CHANNEL_VREFINT) ) |
||
| 2028 | { |
||
| 2029 | if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET) |
||
| 2030 | { |
||
| 2031 | SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); |
||
| 2032 | |||
| 2033 | if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) |
||
| 2034 | { |
||
| 2035 | /* Delay for temperature sensor stabilization time */ |
||
| 2036 | /* Compute number of CPU cycles to wait for */ |
||
| 2037 | wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); |
||
| 2038 | while(wait_loop_index != 0) |
||
| 2039 | { |
||
| 2040 | wait_loop_index--; |
||
| 2041 | } |
||
| 2042 | } |
||
| 2043 | } |
||
| 2044 | } |
||
| 2045 | |||
| 2046 | /* Process unlocked */ |
||
| 2047 | __HAL_UNLOCK(hadc); |
||
| 2048 | |||
| 2049 | /* Return function status */ |
||
| 2050 | return tmp_hal_status; |
||
| 2051 | } |
||
| 2052 | |||
| 2053 | /** |
||
| 2054 | * @brief Configures the analog watchdog. |
||
| 2055 | * @note Analog watchdog thresholds can be modified while ADC conversion |
||
| 2056 | * is on going. |
||
| 2057 | * In this case, some constraints must be taken into account: |
||
| 2058 | * the programmed threshold values are effective from the next |
||
| 2059 | * ADC EOC (end of unitary conversion). |
||
| 2060 | * Considering that registers write delay may happen due to |
||
| 2061 | * bus activity, this might cause an uncertainty on the |
||
| 2062 | * effective timing of the new programmed threshold values. |
||
| 2063 | * @param hadc ADC handle |
||
| 2064 | * @param AnalogWDGConfig Structure of ADC analog watchdog configuration |
||
| 2065 | * @retval HAL status |
||
| 2066 | */ |
||
| 2067 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
||
| 2068 | { |
||
| 2069 | /* Check the parameters */ |
||
| 2070 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
| 2071 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
||
| 2072 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
||
| 2073 | assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); |
||
| 2074 | assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); |
||
| 2075 | |||
| 2076 | if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || |
||
| 2077 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || |
||
| 2078 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) |
||
| 2079 | { |
||
| 2080 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
||
| 2081 | } |
||
| 2082 | |||
| 2083 | /* Process locked */ |
||
| 2084 | __HAL_LOCK(hadc); |
||
| 2085 | |||
| 2086 | /* Analog watchdog configuration */ |
||
| 2087 | |||
| 2088 | /* Configure ADC Analog watchdog interrupt */ |
||
| 2089 | if(AnalogWDGConfig->ITMode == ENABLE) |
||
| 2090 | { |
||
| 2091 | /* Enable the ADC Analog watchdog interrupt */ |
||
| 2092 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
||
| 2093 | } |
||
| 2094 | else |
||
| 2095 | { |
||
| 2096 | /* Disable the ADC Analog watchdog interrupt */ |
||
| 2097 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
||
| 2098 | } |
||
| 2099 | |||
| 2100 | /* Configuration of analog watchdog: */ |
||
| 2101 | /* - Set the analog watchdog enable mode: regular and/or injected groups, */ |
||
| 2102 | /* one or all channels. */ |
||
| 2103 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
||
| 2104 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
||
| 2105 | hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL | |
||
| 2106 | ADC_CR1_JAWDEN | |
||
| 2107 | ADC_CR1_AWDEN | |
||
| 2108 | ADC_CR1_AWDCH ); |
||
| 2109 | |||
| 2110 | hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode | |
||
| 2111 | AnalogWDGConfig->Channel ); |
||
| 2112 | |||
| 2113 | /* Set the high threshold */ |
||
| 2114 | hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; |
||
| 2115 | |||
| 2116 | /* Set the low threshold */ |
||
| 2117 | hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; |
||
| 2118 | |||
| 2119 | /* Process unlocked */ |
||
| 2120 | __HAL_UNLOCK(hadc); |
||
| 2121 | |||
| 2122 | /* Return function status */ |
||
| 2123 | return HAL_OK; |
||
| 2124 | } |
||
| 2125 | |||
| 2126 | |||
| 2127 | /** |
||
| 2128 | * @} |
||
| 2129 | */ |
||
| 2130 | |||
| 2131 | |||
| 2132 | /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions |
||
| 2133 | * @brief Peripheral State functions |
||
| 2134 | * |
||
| 2135 | @verbatim |
||
| 2136 | =============================================================================== |
||
| 2137 | ##### Peripheral State and Errors functions ##### |
||
| 2138 | =============================================================================== |
||
| 2139 | [..] |
||
| 2140 | This subsection provides functions to get in run-time the status of the |
||
| 2141 | peripheral. |
||
| 2142 | (+) Check the ADC state |
||
| 2143 | (+) Check the ADC error code |
||
| 2144 | |||
| 2145 | @endverbatim |
||
| 2146 | * @{ |
||
| 2147 | */ |
||
| 2148 | |||
| 2149 | /** |
||
| 2150 | * @brief return the ADC state |
||
| 2151 | * @param hadc ADC handle |
||
| 2152 | * @retval HAL state |
||
| 2153 | */ |
||
| 2154 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
||
| 2155 | { |
||
| 2156 | /* Return ADC state */ |
||
| 2157 | return hadc->State; |
||
| 2158 | } |
||
| 2159 | |||
| 2160 | /** |
||
| 2161 | * @brief Return the ADC error code |
||
| 2162 | * @param hadc ADC handle |
||
| 2163 | * @retval ADC Error Code |
||
| 2164 | */ |
||
| 2165 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
||
| 2166 | { |
||
| 2167 | return hadc->ErrorCode; |
||
| 2168 | } |
||
| 2169 | |||
| 2170 | /** |
||
| 2171 | * @} |
||
| 2172 | */ |
||
| 2173 | |||
| 2174 | /** |
||
| 2175 | * @} |
||
| 2176 | */ |
||
| 2177 | |||
| 2178 | /** @defgroup ADC_Private_Functions ADC Private Functions |
||
| 2179 | * @{ |
||
| 2180 | */ |
||
| 2181 | |||
| 2182 | /** |
||
| 2183 | * @brief Enable the selected ADC. |
||
| 2184 | * @note Prerequisite condition to use this function: ADC must be disabled |
||
| 2185 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
||
| 2186 | * @note If low power mode AutoPowerOff is enabled, power-on/off phases are |
||
| 2187 | * performed automatically by hardware. |
||
| 2188 | * In this mode, this function is useless and must not be called because |
||
| 2189 | * flag ADC_FLAG_RDY is not usable. |
||
| 2190 | * Therefore, this function must be called under condition of |
||
| 2191 | * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". |
||
| 2192 | * @param hadc ADC handle |
||
| 2193 | * @retval HAL status. |
||
| 2194 | */ |
||
| 2195 | HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
||
| 2196 | { |
||
| 2197 | uint32_t tickstart = 0; |
||
| 2198 | __IO uint32_t wait_loop_index = 0; |
||
| 2199 | |||
| 2200 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
||
| 2201 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
||
| 2202 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
||
| 2203 | /* causes: ADC clock not running, ...). */ |
||
| 2204 | if (ADC_IS_ENABLE(hadc) == RESET) |
||
| 2205 | { |
||
| 2206 | /* Enable the Peripheral */ |
||
| 2207 | __HAL_ADC_ENABLE(hadc); |
||
| 2208 | |||
| 2209 | /* Delay for ADC stabilization time */ |
||
| 2210 | /* Compute number of CPU cycles to wait for */ |
||
| 2211 | wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); |
||
| 2212 | while(wait_loop_index != 0) |
||
| 2213 | { |
||
| 2214 | wait_loop_index--; |
||
| 2215 | } |
||
| 2216 | |||
| 2217 | /* Get tick count */ |
||
| 2218 | tickstart = HAL_GetTick(); |
||
| 2219 | |||
| 2220 | /* Wait for ADC effectively enabled */ |
||
| 2221 | while(ADC_IS_ENABLE(hadc) == RESET) |
||
| 2222 | { |
||
| 2223 | if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT) |
||
| 2224 | { |
||
| 2225 | /* New check to avoid false timeout detection in case of preemption */ |
||
| 2226 | if(ADC_IS_ENABLE(hadc) == RESET) |
||
| 2227 | { |
||
| 2228 | /* Update ADC state machine to error */ |
||
| 2229 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
| 2230 | |||
| 2231 | /* Set ADC error code to ADC IP internal error */ |
||
| 2232 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
| 2233 | |||
| 2234 | /* Process unlocked */ |
||
| 2235 | __HAL_UNLOCK(hadc); |
||
| 2236 | |||
| 2237 | return HAL_ERROR; |
||
| 2238 | } |
||
| 2239 | } |
||
| 2240 | } |
||
| 2241 | } |
||
| 2242 | |||
| 2243 | /* Return HAL status */ |
||
| 2244 | return HAL_OK; |
||
| 2245 | } |
||
| 2246 | |||
| 2247 | /** |
||
| 2248 | * @brief Stop ADC conversion and disable the selected ADC |
||
| 2249 | * @note Prerequisite condition to use this function: ADC conversions must be |
||
| 2250 | * stopped to disable the ADC. |
||
| 2251 | * @param hadc ADC handle |
||
| 2252 | * @retval HAL status. |
||
| 2253 | */ |
||
| 2254 | HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) |
||
| 2255 | { |
||
| 2256 | uint32_t tickstart = 0; |
||
| 2257 | |||
| 2258 | /* Verification if ADC is not already disabled */ |
||
| 2259 | if (ADC_IS_ENABLE(hadc) != RESET) |
||
| 2260 | { |
||
| 2261 | /* Disable the ADC peripheral */ |
||
| 2262 | __HAL_ADC_DISABLE(hadc); |
||
| 2263 | |||
| 2264 | /* Get tick count */ |
||
| 2265 | tickstart = HAL_GetTick(); |
||
| 2266 | |||
| 2267 | /* Wait for ADC effectively disabled */ |
||
| 2268 | while(ADC_IS_ENABLE(hadc) != RESET) |
||
| 2269 | { |
||
| 2270 | if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT) |
||
| 2271 | { |
||
| 2272 | /* New check to avoid false timeout detection in case of preemption */ |
||
| 2273 | if(ADC_IS_ENABLE(hadc) != RESET) |
||
| 2274 | { |
||
| 2275 | /* Update ADC state machine to error */ |
||
| 2276 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
| 2277 | |||
| 2278 | /* Set ADC error code to ADC IP internal error */ |
||
| 2279 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
| 2280 | |||
| 2281 | return HAL_ERROR; |
||
| 2282 | } |
||
| 2283 | } |
||
| 2284 | } |
||
| 2285 | } |
||
| 2286 | |||
| 2287 | /* Return HAL status */ |
||
| 2288 | return HAL_OK; |
||
| 2289 | } |
||
| 2290 | |||
| 2291 | /** |
||
| 2292 | * @brief DMA transfer complete callback. |
||
| 2293 | * @param hdma pointer to DMA handle. |
||
| 2294 | * @retval None |
||
| 2295 | */ |
||
| 2296 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
||
| 2297 | { |
||
| 2298 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
| 2299 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
| 2300 | |||
| 2301 | /* Update state machine on conversion status if not in error state */ |
||
| 2302 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
||
| 2303 | { |
||
| 2304 | /* Update ADC state machine */ |
||
| 2305 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
| 2306 | |||
| 2307 | /* Determine whether any further conversion upcoming on group regular */ |
||
| 2308 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
| 2309 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
||
| 2310 | /* The test of scan sequence on going is done either with scan */ |
||
| 2311 | /* sequence disabled or with end of conversion flag set to */ |
||
| 2312 | /* of end of sequence. */ |
||
| 2313 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
| 2314 | (hadc->Init.ContinuousConvMode == DISABLE) && |
||
| 2315 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
||
| 2316 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
||
| 2317 | { |
||
| 2318 | /* Disable ADC end of single conversion interrupt on group regular */ |
||
| 2319 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
||
| 2320 | /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ |
||
| 2321 | /* by overrun IRQ process below. */ |
||
| 2322 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
||
| 2323 | |||
| 2324 | /* Set ADC state */ |
||
| 2325 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
||
| 2326 | |||
| 2327 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
| 2328 | { |
||
| 2329 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
| 2330 | } |
||
| 2331 | } |
||
| 2332 | |||
| 2333 | /* Conversion complete callback */ |
||
| 2334 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 2335 | hadc->ConvCpltCallback(hadc); |
||
| 2336 | #else |
||
| 2337 | HAL_ADC_ConvCpltCallback(hadc); |
||
| 2338 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 2339 | } |
||
| 2340 | else |
||
| 2341 | { |
||
| 2342 | /* Call DMA error callback */ |
||
| 2343 | hadc->DMA_Handle->XferErrorCallback(hdma); |
||
| 2344 | } |
||
| 2345 | } |
||
| 2346 | |||
| 2347 | /** |
||
| 2348 | * @brief DMA half transfer complete callback. |
||
| 2349 | * @param hdma pointer to DMA handle. |
||
| 2350 | * @retval None |
||
| 2351 | */ |
||
| 2352 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
||
| 2353 | { |
||
| 2354 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
| 2355 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
| 2356 | |||
| 2357 | /* Half conversion callback */ |
||
| 2358 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 2359 | hadc->ConvHalfCpltCallback(hadc); |
||
| 2360 | #else |
||
| 2361 | HAL_ADC_ConvHalfCpltCallback(hadc); |
||
| 2362 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 2363 | } |
||
| 2364 | |||
| 2365 | /** |
||
| 2366 | * @brief DMA error callback |
||
| 2367 | * @param hdma pointer to DMA handle. |
||
| 2368 | * @retval None |
||
| 2369 | */ |
||
| 2370 | static void ADC_DMAError(DMA_HandleTypeDef *hdma) |
||
| 2371 | { |
||
| 2372 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
| 2373 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
| 2374 | |||
| 2375 | /* Set ADC state */ |
||
| 2376 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
||
| 2377 | |||
| 2378 | /* Set ADC error code to DMA error */ |
||
| 2379 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); |
||
| 2380 | |||
| 2381 | /* Error callback */ |
||
| 2382 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 2383 | hadc->ErrorCallback(hadc); |
||
| 2384 | #else |
||
| 2385 | HAL_ADC_ErrorCallback(hadc); |
||
| 2386 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 2387 | } |
||
| 2388 | |||
| 2389 | /** |
||
| 2390 | * @} |
||
| 2391 | */ |
||
| 2392 | |||
| 2393 | #endif /* HAL_ADC_MODULE_ENABLED */ |
||
| 2394 | /** |
||
| 2395 | * @} |
||
| 2396 | */ |
||
| 2397 | |||
| 2398 | /** |
||
| 2399 | * @} |
||
| 2400 | */ |