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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 77 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_ll_adc.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of ADC LL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved. |
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| 11 | * |
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| 12 | * This software is licensed under terms that can be found in the LICENSE file |
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| 13 | * in the root directory of this software component. |
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| 14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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| 15 | * |
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| 16 | ****************************************************************************** |
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| 17 | */ |
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| 18 | |||
| 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 20 | #ifndef __STM32L1xx_LL_ADC_H |
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| 21 | #define __STM32L1xx_LL_ADC_H |
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| 22 | |||
| 23 | #ifdef __cplusplus |
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| 24 | extern "C" { |
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| 25 | #endif |
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| 26 | |||
| 27 | /* Includes ------------------------------------------------------------------*/ |
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| 28 | #include "stm32l1xx.h" |
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| 29 | |||
| 30 | /** @addtogroup STM32L1xx_LL_Driver |
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| 31 | * @{ |
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| 32 | */ |
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| 33 | |||
| 34 | #if defined (ADC1) |
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| 35 | |||
| 36 | /** @defgroup ADC_LL ADC |
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| 37 | * @{ |
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| 38 | */ |
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| 39 | |||
| 40 | /* Private types -------------------------------------------------------------*/ |
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| 41 | /* Private variables ---------------------------------------------------------*/ |
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| 42 | |||
| 43 | /* Private constants ---------------------------------------------------------*/ |
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| 44 | /** @defgroup ADC_LL_Private_Constants ADC Private Constants |
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| 45 | * @{ |
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| 46 | */ |
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| 47 | |||
| 48 | /* Internal mask for ADC group regular sequencer: */ |
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| 49 | /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ |
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| 50 | /* - sequencer register offset */ |
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| 51 | /* - sequencer rank bits position into the selected register */ |
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| 52 | |||
| 53 | /* Internal register offset for ADC group regular sequencer configuration */ |
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| 54 | /* (offset placed into a spare area of literal definition) */ |
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| 55 | #define ADC_SQR1_REGOFFSET 0x00000000U |
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| 56 | #define ADC_SQR2_REGOFFSET 0x00000100U |
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| 57 | #define ADC_SQR3_REGOFFSET 0x00000200U |
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| 58 | #define ADC_SQR4_REGOFFSET 0x00000300U |
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| 59 | #define ADC_SQR5_REGOFFSET 0x00000400U |
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| 60 | |||
| 61 | #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET | ADC_SQR5_REGOFFSET) |
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| 62 | #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) |
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| 63 | |||
| 64 | /* Definition of ADC group regular sequencer bits information to be inserted */ |
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| 65 | /* into ADC group regular sequencer ranks literals definition. */ |
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| 66 | #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ1) */ |
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| 67 | #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ2) */ |
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| 68 | #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ3) */ |
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| 69 | #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ4) */ |
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| 70 | #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ5) */ |
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| 71 | #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ6) */ |
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| 72 | #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ7) */ |
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| 73 | #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ8) */ |
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| 74 | #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ9) */ |
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| 75 | #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ10) */ |
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| 76 | #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ11) */ |
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| 77 | #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ12) */ |
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| 78 | #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */ |
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| 79 | #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */ |
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| 80 | #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ15) */ |
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| 81 | #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ16) */ |
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| 82 | #define ADC_REG_RANK_17_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ17) */ |
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| 83 | #define ADC_REG_RANK_18_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ18) */ |
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| 84 | #define ADC_REG_RANK_19_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ29) */ |
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| 85 | #define ADC_REG_RANK_20_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ20) */ |
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| 86 | #define ADC_REG_RANK_21_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ21) */ |
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| 87 | #define ADC_REG_RANK_22_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ22) */ |
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| 88 | #define ADC_REG_RANK_23_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ23) */ |
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| 89 | #define ADC_REG_RANK_24_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ24) */ |
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| 90 | #define ADC_REG_RANK_25_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ25) */ |
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| 91 | #define ADC_REG_RANK_26_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ26) */ |
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| 92 | #define ADC_REG_RANK_27_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ27) */ |
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| 93 | #if defined(ADC_SQR1_SQ28) |
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| 94 | #define ADC_REG_RANK_28_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ28) */ |
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| 95 | #endif |
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| 96 | |||
| 97 | |||
| 98 | |||
| 99 | /* Internal mask for ADC group injected sequencer: */ |
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| 100 | /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ |
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| 101 | /* - data register offset */ |
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| 102 | /* - offset register offset */ |
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| 103 | /* - sequencer rank bits position into the selected register */ |
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| 104 | |||
| 105 | /* Internal register offset for ADC group injected data register */ |
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| 106 | /* (offset placed into a spare area of literal definition) */ |
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| 107 | #define ADC_JDR1_REGOFFSET 0x00000000U |
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| 108 | #define ADC_JDR2_REGOFFSET 0x00000100U |
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| 109 | #define ADC_JDR3_REGOFFSET 0x00000200U |
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| 110 | #define ADC_JDR4_REGOFFSET 0x00000300U |
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| 111 | |||
| 112 | /* Internal register offset for ADC group injected offset configuration */ |
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| 113 | /* (offset placed into a spare area of literal definition) */ |
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| 114 | #define ADC_JOFR1_REGOFFSET 0x00000000U |
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| 115 | #define ADC_JOFR2_REGOFFSET 0x00001000U |
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| 116 | #define ADC_JOFR3_REGOFFSET 0x00002000U |
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| 117 | #define ADC_JOFR4_REGOFFSET 0x00003000U |
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| 118 | |||
| 119 | #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) |
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| 120 | #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) |
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| 121 | #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) |
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| 122 | |||
| 123 | /* Definition of ADC group injected sequencer bits information to be inserted */ |
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| 124 | /* into ADC group injected sequencer ranks literals definition. */ |
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| 125 | #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */ |
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| 126 | #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */ |
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| 127 | #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */ |
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| 128 | #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */ |
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| 129 | |||
| 130 | |||
| 131 | |||
| 132 | /* Internal mask for ADC group regular trigger: */ |
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| 133 | /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ |
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| 134 | /* - regular trigger source */ |
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| 135 | /* - regular trigger edge */ |
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| 136 | #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ |
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| 137 | |||
| 138 | /* Mask containing trigger source masks for each of possible */ |
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| 139 | /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ |
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| 140 | /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ |
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| 141 | #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \ |
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| 142 | ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \ |
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| 143 | ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \ |
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| 144 | ((ADC_CR2_EXTSEL) >> (4U * 3U))) |
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| 145 | |||
| 146 | /* Mask containing trigger edge masks for each of possible */ |
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| 147 | /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ |
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| 148 | /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ |
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| 149 | #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \ |
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| 150 | ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ |
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| 151 | ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ |
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| 152 | ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U))) |
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| 153 | |||
| 154 | /* Definition of ADC group regular trigger bits information. */ |
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| 155 | #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */ |
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| 156 | #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */ |
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| 157 | |||
| 158 | |||
| 159 | |||
| 160 | /* Internal mask for ADC group injected trigger: */ |
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| 161 | /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ |
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| 162 | /* - injected trigger source */ |
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| 163 | /* - injected trigger edge */ |
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| 164 | #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ |
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| 165 | |||
| 166 | /* Mask containing trigger source masks for each of possible */ |
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| 167 | /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ |
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| 168 | /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ |
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| 169 | #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \ |
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| 170 | ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \ |
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| 171 | ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \ |
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| 172 | ((ADC_CR2_JEXTSEL) >> (4U * 3U))) |
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| 173 | |||
| 174 | /* Mask containing trigger edge masks for each of possible */ |
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| 175 | /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ |
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| 176 | /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ |
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| 177 | #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \ |
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| 178 | ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ |
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| 179 | ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ |
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| 180 | ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U))) |
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| 181 | |||
| 182 | /* Definition of ADC group injected trigger bits information. */ |
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| 183 | #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */ |
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| 184 | #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */ |
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| 185 | |||
| 186 | |||
| 187 | |||
| 188 | |||
| 189 | |||
| 190 | |||
| 191 | /* Internal mask for ADC channel: */ |
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| 192 | /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ |
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| 193 | /* - channel identifier defined by number */ |
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| 194 | /* - channel differentiation between external channels (connected to */ |
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| 195 | /* GPIO pins) and internal channels (connected to internal paths) */ |
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| 196 | /* - channel sampling time defined by SMPRx register offset */ |
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| 197 | /* and SMPx bits positions into SMPRx register */ |
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| 198 | #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) |
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| 199 | #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ |
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| 200 | #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) |
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| 201 | /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ |
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| 202 | #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ |
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| 203 | |||
| 204 | /* Channel differentiation between external and internal channels */ |
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| 205 | #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ |
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| 206 | #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH) |
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| 207 | |||
| 208 | /* Internal register offset for ADC channel sampling time configuration */ |
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| 209 | /* (offset placed into a spare area of literal definition) */ |
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| 210 | #define ADC_SMPR1_REGOFFSET 0x00000000U |
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| 211 | #define ADC_SMPR2_REGOFFSET 0x02000000U |
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| 212 | #define ADC_SMPR3_REGOFFSET 0x04000000U |
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| 213 | #if defined(ADC_SMPR0_SMP31) |
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| 214 | #define ADC_SMPR0_REGOFFSET 0x28000000U /* SMPR0 register offset from SMPR1 is 20 registers. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
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| 215 | #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET | ADC_SMPR0_REGOFFSET) |
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| 216 | #else |
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| 217 | #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET) |
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| 218 | #endif /* ADC_SMPR0_SMP31 */ |
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| 219 | |||
| 220 | #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U |
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| 221 | #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ |
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| 222 | |||
| 223 | /* Definition of channels ID number information to be inserted into */ |
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| 224 | /* channels literals definition. */ |
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| 225 | #define ADC_CHANNEL_0_NUMBER 0x00000000U |
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| 226 | #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) |
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| 227 | #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) |
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| 228 | #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
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| 229 | #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) |
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| 230 | #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) |
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| 231 | #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) |
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| 232 | #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
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| 233 | #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) |
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| 234 | #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) |
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| 235 | #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) |
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| 236 | #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
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| 237 | #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) |
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| 238 | #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) |
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| 239 | #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) |
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| 240 | #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
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| 241 | #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) |
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| 242 | #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) |
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| 243 | #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 ) |
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| 244 | #define ADC_CHANNEL_19_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
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| 245 | #define ADC_CHANNEL_20_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_2 ) |
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| 246 | #define ADC_CHANNEL_21_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) |
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| 247 | #define ADC_CHANNEL_22_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) |
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| 248 | #define ADC_CHANNEL_23_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
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| 249 | #define ADC_CHANNEL_24_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 ) |
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| 250 | #define ADC_CHANNEL_25_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) |
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| 251 | #define ADC_CHANNEL_26_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) |
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| 252 | #if defined(ADC_SMPR0_SMP31) |
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| 253 | #define ADC_CHANNEL_27_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
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| 254 | #define ADC_CHANNEL_28_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) |
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| 255 | #define ADC_CHANNEL_29_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) |
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| 256 | #define ADC_CHANNEL_30_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) |
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| 257 | #define ADC_CHANNEL_31_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
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| 258 | #endif /* ADC_SMPR0_SMP31 */ |
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| 259 | |||
| 260 | /* Definition of channels sampling time information to be inserted into */ |
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| 261 | /* channels literals definition. */ |
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| 262 | #define ADC_CHANNEL_0_SMP (ADC_SMPR3_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP0) */ |
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| 263 | #define ADC_CHANNEL_1_SMP (ADC_SMPR3_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP1) */ |
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| 264 | #define ADC_CHANNEL_2_SMP (ADC_SMPR3_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP2) */ |
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| 265 | #define ADC_CHANNEL_3_SMP (ADC_SMPR3_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP3) */ |
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| 266 | #define ADC_CHANNEL_4_SMP (ADC_SMPR3_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP4) */ |
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| 267 | #define ADC_CHANNEL_5_SMP (ADC_SMPR3_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP5) */ |
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| 268 | #define ADC_CHANNEL_6_SMP (ADC_SMPR3_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP6) */ |
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| 269 | #define ADC_CHANNEL_7_SMP (ADC_SMPR3_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP7) */ |
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| 270 | #define ADC_CHANNEL_8_SMP (ADC_SMPR3_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP8) */ |
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| 271 | #define ADC_CHANNEL_9_SMP (ADC_SMPR3_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP9) */ |
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| 272 | #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */ |
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| 273 | #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */ |
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| 274 | #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */ |
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| 275 | #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */ |
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| 276 | #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */ |
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| 277 | #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */ |
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| 278 | #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */ |
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| 279 | #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */ |
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| 280 | #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */ |
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| 281 | #define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP19) */ |
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| 282 | #define ADC_CHANNEL_20_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP20) */ |
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| 283 | #define ADC_CHANNEL_21_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP21) */ |
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| 284 | #define ADC_CHANNEL_22_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP22) */ |
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| 285 | #define ADC_CHANNEL_23_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP23) */ |
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| 286 | #define ADC_CHANNEL_24_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP24) */ |
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| 287 | #define ADC_CHANNEL_25_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP25) */ |
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| 288 | #define ADC_CHANNEL_26_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP26) */ |
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| 289 | #if defined(ADC_SMPR0_SMP31) |
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| 290 | #define ADC_CHANNEL_27_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP27) */ |
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| 291 | #define ADC_CHANNEL_28_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP28) */ |
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| 292 | #define ADC_CHANNEL_29_SMP (ADC_SMPR1_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP19) */ |
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| 293 | #define ADC_CHANNEL_30_SMP (ADC_SMPR0_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP30) */ |
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| 294 | #define ADC_CHANNEL_31_SMP (ADC_SMPR0_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP31) */ |
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| 295 | #endif /* ADC_SMPR0_SMP31 */ |
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| 296 | |||
| 297 | |||
| 298 | /* Internal mask for ADC analog watchdog: */ |
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| 299 | /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ |
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| 300 | /* (concatenation of multiple bits used in different analog watchdogs, */ |
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| 301 | /* (feature of several watchdogs not available on all STM32 families)). */ |
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| 302 | /* - analog watchdog 1: monitored channel defined by number, */ |
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| 303 | /* selection of ADC group (ADC groups regular and-or injected). */ |
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| 304 | |||
| 305 | /* Internal register offset for ADC analog watchdog channel configuration */ |
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| 306 | #define ADC_AWD_CR1_REGOFFSET 0x00000000U |
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| 307 | |||
| 308 | #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) |
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| 309 | |||
| 310 | #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) |
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| 311 | #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) |
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| 312 | |||
| 313 | /* Internal register offset for ADC analog watchdog threshold configuration */ |
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| 314 | #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U |
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| 315 | #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U |
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| 316 | #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) |
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| 317 | |||
| 318 | |||
| 319 | /* ADC registers bits positions */ |
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| 320 | #define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */ |
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| 321 | #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ |
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| 322 | |||
| 323 | |||
| 324 | /* ADC internal channels related definitions */ |
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| 325 | /* Internal voltage reference VrefInt */ |
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| 326 | #define VREFINT_CAL_ADDR ((uint16_t*) VREFINT_CAL_ADDR_CMSIS) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ |
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| 327 | #define VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ |
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| 328 | /* Temperature sensor */ |
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| 329 | #if defined (TEMPSENSOR_CAL1_ADDR_CMSIS) |
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| 330 | #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) TEMPSENSOR_CAL1_ADDR_CMSIS) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ |
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| 331 | #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) TEMPSENSOR_CAL2_ADDR_CMSIS) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ |
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| 332 | #endif /* TEMPSENSOR_CAL1_ADDR_CMSIS */ |
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| 333 | #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ |
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| 334 | #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ |
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| 335 | #define TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ |
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| 336 | |||
| 337 | |||
| 338 | /** |
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| 339 | * @} |
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| 340 | */ |
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| 341 | |||
| 342 | |||
| 343 | /* Private macros ------------------------------------------------------------*/ |
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| 344 | /** @defgroup ADC_LL_Private_Macros ADC Private Macros |
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| 345 | * @{ |
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| 346 | */ |
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| 347 | |||
| 348 | /** |
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| 349 | * @brief Driver macro reserved for internal use: isolate bits with the |
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| 350 | * selected mask and shift them to the register LSB |
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| 351 | * (shift mask on register position bit 0). |
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| 352 | * @param __BITS__ Bits in register 32 bits |
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| 353 | * @param __MASK__ Mask in register 32 bits |
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| 354 | * @retval Bits in register 32 bits |
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| 355 | */ |
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| 356 | #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ |
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| 357 | (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) |
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| 358 | |||
| 359 | /** |
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| 360 | * @brief Driver macro reserved for internal use: set a pointer to |
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| 361 | * a register from a register basis from which an offset |
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| 362 | * is applied. |
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| 363 | * @param __REG__ Register basis from which the offset is applied. |
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| 364 | * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). |
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| 365 | * @retval Pointer to register address |
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| 366 | */ |
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| 367 | #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ |
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| 368 | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) |
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| 369 | |||
| 370 | /** |
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| 371 | * @} |
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| 372 | */ |
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| 373 | |||
| 374 | |||
| 375 | /* Exported types ------------------------------------------------------------*/ |
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| 376 | #if defined(USE_FULL_LL_DRIVER) |
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| 377 | /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure |
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| 378 | * @{ |
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| 379 | */ |
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| 380 | |||
| 381 | /** |
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| 382 | * @brief Structure definition of some features of ADC common parameters |
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| 383 | * and multimode |
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| 384 | * (all ADC instances belonging to the same ADC common instance). |
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| 385 | * @note The setting of these parameters by function @ref LL_ADC_CommonInit() |
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| 386 | * is conditioned to ADC instances state (all ADC instances |
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| 387 | * sharing the same ADC common instance): |
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| 388 | * All ADC instances sharing the same ADC common instance must be |
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| 389 | * disabled. |
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| 390 | */ |
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| 391 | typedef struct |
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| 392 | { |
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| 393 | uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. |
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| 394 | This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE |
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| 395 | @note On this STM32 series, HSI RC oscillator is the only clock source for ADC. |
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| 396 | Therefore, HSI RC oscillator must be preliminarily enabled at RCC top level. |
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| 397 | @note On this STM32 series, some clock ratio constraints between ADC clock and APB clock |
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| 398 | must be respected: |
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| 399 | - In all cases: if APB clock frequency is too low compared ADC clock frequency, a delay between conversions must be inserted. |
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| 400 | - If ADC group injected is used: ADC clock frequency should be lower than APB clock frequency /4 for resolution 12 or 10 bits, APB clock frequency /3 for resolution 8 bits, APB clock frequency /2 for resolution 6 bits. |
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| 401 | Refer to reference manual. |
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| 402 | |||
| 403 | This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ |
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| 404 | |||
| 405 | } LL_ADC_CommonInitTypeDef; |
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| 406 | |||
| 407 | /** |
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| 408 | * @brief Structure definition of some features of ADC instance. |
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| 409 | * @note These parameters have an impact on ADC scope: ADC instance. |
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| 410 | * Affects both group regular and group injected (availability |
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| 411 | * of ADC group injected depends on STM32 families). |
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| 412 | * Refer to corresponding unitary functions into |
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| 413 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
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| 414 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
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| 415 | * is conditioned to ADC state: |
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| 416 | * ADC instance must be disabled. |
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| 417 | * This condition is applied to all ADC features, for efficiency |
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| 418 | * and compatibility over all STM32 families. However, the different |
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| 419 | * features can be set under different ADC state conditions |
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| 420 | * (setting possible with ADC enabled without conversion on going, |
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| 421 | * ADC enabled with conversion on going, ...) |
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| 422 | * Each feature can be updated afterwards with a unitary function |
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| 423 | * and potentially with ADC in a different state than disabled, |
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| 424 | * refer to description of each function for setting |
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| 425 | * conditioned to ADC state. |
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| 426 | */ |
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| 427 | typedef struct |
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| 428 | { |
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| 429 | uint32_t Resolution; /*!< Set ADC resolution. |
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| 430 | This parameter can be a value of @ref ADC_LL_EC_RESOLUTION |
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| 431 | |||
| 432 | This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ |
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| 433 | |||
| 434 | uint32_t DataAlignment; /*!< Set ADC conversion data alignment. |
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| 435 | This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN |
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| 436 | |||
| 437 | This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ |
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| 438 | |||
| 439 | uint32_t LowPowerMode; /*!< Set ADC low power mode. |
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| 440 | This parameter can be a concatenation of a value of @ref ADC_LL_EC_LP_MODE_AUTOWAIT and a value of @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF |
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| 441 | |||
| 442 | This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerModeAutoWait() and @ref LL_ADC_SetLowPowerModeAutoPowerOff(). */ |
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| 443 | |||
| 444 | uint32_t SequencersScanMode; /*!< Set ADC scan selection. |
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| 445 | This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION |
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| 446 | |||
| 447 | This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ |
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| 448 | |||
| 449 | } LL_ADC_InitTypeDef; |
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| 450 | |||
| 451 | /** |
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| 452 | * @brief Structure definition of some features of ADC group regular. |
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| 453 | * @note These parameters have an impact on ADC scope: ADC group regular. |
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| 454 | * Refer to corresponding unitary functions into |
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| 455 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
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| 456 | * (functions with prefix "REG"). |
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| 457 | * @note The setting of these parameters by function @ref LL_ADC_REG_Init() |
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| 458 | * is conditioned to ADC state: |
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| 459 | * ADC instance must be disabled. |
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| 460 | * This condition is applied to all ADC features, for efficiency |
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| 461 | * and compatibility over all STM32 families. However, the different |
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| 462 | * features can be set under different ADC state conditions |
||
| 463 | * (setting possible with ADC enabled without conversion on going, |
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| 464 | * ADC enabled with conversion on going, ...) |
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| 465 | * Each feature can be updated afterwards with a unitary function |
||
| 466 | * and potentially with ADC in a different state than disabled, |
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| 467 | * refer to description of each function for setting |
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| 468 | * conditioned to ADC state. |
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| 469 | */ |
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| 470 | typedef struct |
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| 471 | { |
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| 472 | uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). |
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| 473 | This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE |
||
| 474 | @note On this STM32 series, setting of external trigger edge is performed |
||
| 475 | using function @ref LL_ADC_REG_StartConversionExtTrig(). |
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| 476 | |||
| 477 | This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ |
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| 478 | |||
| 479 | uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. |
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| 480 | This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH |
||
| 481 | @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). |
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| 482 | |||
| 483 | This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ |
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| 484 | |||
| 485 | uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. |
||
| 486 | This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE |
||
| 487 | @note This parameter has an effect only if group regular sequencer is enabled |
||
| 488 | (scan length of 2 ranks or more). |
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| 489 | |||
| 490 | This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ |
||
| 491 | |||
| 492 | uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). |
||
| 493 | This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE |
||
| 494 | Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. |
||
| 495 | |||
| 496 | This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ |
||
| 497 | |||
| 498 | uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. |
||
| 499 | This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER |
||
| 500 | |||
| 501 | This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ |
||
| 502 | |||
| 503 | } LL_ADC_REG_InitTypeDef; |
||
| 504 | |||
| 505 | /** |
||
| 506 | * @brief Structure definition of some features of ADC group injected. |
||
| 507 | * @note These parameters have an impact on ADC scope: ADC group injected. |
||
| 508 | * Refer to corresponding unitary functions into |
||
| 509 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
||
| 510 | * (functions with prefix "INJ"). |
||
| 511 | * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() |
||
| 512 | * is conditioned to ADC state: |
||
| 513 | * ADC instance must be disabled. |
||
| 514 | * This condition is applied to all ADC features, for efficiency |
||
| 515 | * and compatibility over all STM32 families. However, the different |
||
| 516 | * features can be set under different ADC state conditions |
||
| 517 | * (setting possible with ADC enabled without conversion on going, |
||
| 518 | * ADC enabled with conversion on going, ...) |
||
| 519 | * Each feature can be updated afterwards with a unitary function |
||
| 520 | * and potentially with ADC in a different state than disabled, |
||
| 521 | * refer to description of each function for setting |
||
| 522 | * conditioned to ADC state. |
||
| 523 | */ |
||
| 524 | typedef struct |
||
| 525 | { |
||
| 526 | uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). |
||
| 527 | This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE |
||
| 528 | @note On this STM32 series, setting of external trigger edge is performed |
||
| 529 | using function @ref LL_ADC_INJ_StartConversionExtTrig(). |
||
| 530 | |||
| 531 | This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ |
||
| 532 | |||
| 533 | uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. |
||
| 534 | This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH |
||
| 535 | @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). |
||
| 536 | |||
| 537 | This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ |
||
| 538 | |||
| 539 | uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. |
||
| 540 | This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE |
||
| 541 | @note This parameter has an effect only if group injected sequencer is enabled |
||
| 542 | (scan length of 2 ranks or more). |
||
| 543 | |||
| 544 | This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ |
||
| 545 | |||
| 546 | uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. |
||
| 547 | This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO |
||
| 548 | Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. |
||
| 549 | |||
| 550 | This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ |
||
| 551 | |||
| 552 | } LL_ADC_INJ_InitTypeDef; |
||
| 553 | |||
| 554 | /** |
||
| 555 | * @} |
||
| 556 | */ |
||
| 557 | #endif /* USE_FULL_LL_DRIVER */ |
||
| 558 | |||
| 559 | /* Exported constants --------------------------------------------------------*/ |
||
| 560 | /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants |
||
| 561 | * @{ |
||
| 562 | */ |
||
| 563 | |||
| 564 | /** @defgroup ADC_LL_EC_FLAG ADC flags |
||
| 565 | * @brief Flags defines which can be used with LL_ADC_ReadReg function |
||
| 566 | * @{ |
||
| 567 | */ |
||
| 568 | #define LL_ADC_FLAG_ADRDY ADC_SR_ADONS /*!< ADC flag ADC instance ready */ |
||
| 569 | #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ |
||
| 570 | #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ |
||
| 571 | #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */ |
||
| 572 | #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ |
||
| 573 | #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ |
||
| 574 | #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ |
||
| 575 | /** |
||
| 576 | * @} |
||
| 577 | */ |
||
| 578 | |||
| 579 | /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) |
||
| 580 | * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions |
||
| 581 | * @{ |
||
| 582 | */ |
||
| 583 | #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ |
||
| 584 | #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */ |
||
| 585 | #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ |
||
| 586 | #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ |
||
| 587 | /** |
||
| 588 | * @} |
||
| 589 | */ |
||
| 590 | |||
| 591 | /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose |
||
| 592 | * @{ |
||
| 593 | */ |
||
| 594 | /* List of ADC registers intended to be used (most commonly) with */ |
||
| 595 | /* DMA transfer. */ |
||
| 596 | /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ |
||
| 597 | #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ |
||
| 598 | /** |
||
| 599 | * @} |
||
| 600 | */ |
||
| 601 | |||
| 602 | /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source |
||
| 603 | * @{ |
||
| 604 | */ |
||
| 605 | #define LL_ADC_CLOCK_ASYNC_DIV1 0x00000000U /*!< ADC asynchronous clock without prescaler */ |
||
| 606 | #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock with prescaler division by 2 */ |
||
| 607 | #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock with prescaler division by 4 */ |
||
| 608 | /** |
||
| 609 | * @} |
||
| 610 | */ |
||
| 611 | |||
| 612 | /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels |
||
| 613 | * @{ |
||
| 614 | */ |
||
| 615 | /* Note: Other measurement paths to internal channels may be available */ |
||
| 616 | /* (connections to other peripherals). */ |
||
| 617 | /* If they are not listed below, they do not require any specific */ |
||
| 618 | /* path enable. In this case, Access to measurement path is done */ |
||
| 619 | /* only by selecting the corresponding ADC internal channel. */ |
||
| 620 | #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all disabled */ |
||
| 621 | #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ |
||
| 622 | #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ |
||
| 623 | /** |
||
| 624 | * @} |
||
| 625 | */ |
||
| 626 | |||
| 627 | /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution |
||
| 628 | * @{ |
||
| 629 | */ |
||
| 630 | #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */ |
||
| 631 | #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */ |
||
| 632 | #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */ |
||
| 633 | #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */ |
||
| 634 | /** |
||
| 635 | * @} |
||
| 636 | */ |
||
| 637 | |||
| 638 | /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment |
||
| 639 | * @{ |
||
| 640 | */ |
||
| 641 | #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ |
||
| 642 | #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ |
||
| 643 | /** |
||
| 644 | * @} |
||
| 645 | */ |
||
| 646 | |||
| 647 | /** @defgroup ADC_LL_EC_LP_MODE_AUTOWAIT ADC instance - Low power mode auto wait (auto delay) |
||
| 648 | * @{ |
||
| 649 | */ |
||
| 650 | #define LL_ADC_LP_AUTOWAIT_NONE 0x00000000U /*!< ADC low power mode auto wait not activated */ |
||
| 651 | #define LL_ADC_LP_AUTOWAIT ( ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerModeAutoWait(). */ |
||
| 652 | #define LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES ( ADC_CR2_DELS_1 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 7 APB clock cycles */ |
||
| 653 | #define LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES ( ADC_CR2_DELS_1 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 15 APB clock cycles */ |
||
| 654 | #define LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES (ADC_CR2_DELS_2 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 31 APB clock cycles */ |
||
| 655 | #define LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES (ADC_CR2_DELS_2 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 63 APB clock cycles */ |
||
| 656 | #define LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES (ADC_CR2_DELS_2 | ADC_CR2_DELS_1 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 127 APB clock cycles */ |
||
| 657 | #define LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES (ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 255 APB clock cycles */ |
||
| 658 | /** |
||
| 659 | * @} |
||
| 660 | */ |
||
| 661 | |||
| 662 | /** @defgroup ADC_LL_EC_LP_MODE_AUTOPOWEROFF ADC instance - Low power mode auto power-off |
||
| 663 | * @{ |
||
| 664 | */ |
||
| 665 | #define LL_ADC_LP_AUTOPOWEROFF_NONE 0x00000000U /*!< ADC low power mode auto power-off not activated */ |
||
| 666 | #define LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE (ADC_CR1_PDI) /*!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) */ |
||
| 667 | #define LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE (ADC_CR1_PDD) /*!< ADC low power mode auto power-off: ADC power off when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) */ |
||
| 668 | #define LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES (ADC_CR1_PDI | ADC_CR1_PDD) /*!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) */ |
||
| 669 | /** |
||
| 670 | * @} |
||
| 671 | */ |
||
| 672 | |||
| 673 | /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection |
||
| 674 | * @{ |
||
| 675 | */ |
||
| 676 | #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ |
||
| 677 | #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ |
||
| 678 | /** |
||
| 679 | * @} |
||
| 680 | */ |
||
| 681 | |||
| 682 | #if defined(ADC_CR2_CFG) |
||
| 683 | /** @defgroup ADC_LL_EC_CHANNELS_BANK ADC instance - Channels bank |
||
| 684 | * @{ |
||
| 685 | */ |
||
| 686 | #define LL_ADC_CHANNELS_BANK_A 0x00000000U /*!< ADC channels bank A */ |
||
| 687 | #define LL_ADC_CHANNELS_BANK_B (ADC_CR2_CFG) /*!< ADC channels bank B, available in devices categories 3, 4, 5. */ |
||
| 688 | /** |
||
| 689 | * @} |
||
| 690 | */ |
||
| 691 | #endif |
||
| 692 | |||
| 693 | /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups |
||
| 694 | * @{ |
||
| 695 | */ |
||
| 696 | #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */ |
||
| 697 | #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/ |
||
| 698 | #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */ |
||
| 699 | /** |
||
| 700 | * @} |
||
| 701 | */ |
||
| 702 | |||
| 703 | /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number |
||
| 704 | * @{ |
||
| 705 | */ |
||
| 706 | #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 . Channel different in bank A and bank B. */ |
||
| 707 | #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 . Channel different in bank A and bank B. */ |
||
| 708 | #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 . Channel different in bank A and bank B. */ |
||
| 709 | #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 . Channel different in bank A and bank B. */ |
||
| 710 | #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 . Direct (fast) channel. */ |
||
| 711 | #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 . Direct (fast) channel. */ |
||
| 712 | #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 . Channel different in bank A and bank B. */ |
||
| 713 | #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 . Channel different in bank A and bank B. */ |
||
| 714 | #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 . Channel different in bank A and bank B. */ |
||
| 715 | #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 . Channel different in bank A and bank B. */ |
||
| 716 | #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10. Channel different in bank A and bank B. */ |
||
| 717 | #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11. Channel different in bank A and bank B. */ |
||
| 718 | #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12. Channel different in bank A and bank B. */ |
||
| 719 | #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13. Channel common to both bank A and bank B. */ |
||
| 720 | #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14. Channel common to both bank A and bank B. */ |
||
| 721 | #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15. Channel common to both bank A and bank B. */ |
||
| 722 | #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16. Channel common to both bank A and bank B. */ |
||
| 723 | #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17. Channel common to both bank A and bank B. */ |
||
| 724 | #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18. Channel common to both bank A and bank B. */ |
||
| 725 | #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19. Channel common to both bank A and bank B. */ |
||
| 726 | #define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER | ADC_CHANNEL_20_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20. Channel common to both bank A and bank B. */ |
||
| 727 | #define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER | ADC_CHANNEL_21_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21. Channel common to both bank A and bank B. */ |
||
| 728 | #define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER | ADC_CHANNEL_22_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22. Direct (fast) channel. */ |
||
| 729 | #define LL_ADC_CHANNEL_23 (ADC_CHANNEL_23_NUMBER | ADC_CHANNEL_23_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN23. Direct (fast) channel. */ |
||
| 730 | #define LL_ADC_CHANNEL_24 (ADC_CHANNEL_24_NUMBER | ADC_CHANNEL_24_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN24. Direct (fast) channel. */ |
||
| 731 | #define LL_ADC_CHANNEL_25 (ADC_CHANNEL_25_NUMBER | ADC_CHANNEL_25_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN25. Direct (fast) channel. */ |
||
| 732 | #define LL_ADC_CHANNEL_26 (ADC_CHANNEL_26_NUMBER | ADC_CHANNEL_26_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN26. Direct (fast) channel. */ |
||
| 733 | #if defined(ADC_SMPR0_SMP31) |
||
| 734 | #define LL_ADC_CHANNEL_27 (ADC_CHANNEL_27_NUMBER | ADC_CHANNEL_27_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN27. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 735 | #define LL_ADC_CHANNEL_28 (ADC_CHANNEL_28_NUMBER | ADC_CHANNEL_28_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN28. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 736 | #define LL_ADC_CHANNEL_29 (ADC_CHANNEL_29_NUMBER | ADC_CHANNEL_29_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN29. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 737 | #define LL_ADC_CHANNEL_30 (ADC_CHANNEL_30_NUMBER | ADC_CHANNEL_30_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN30. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 738 | #define LL_ADC_CHANNEL_31 (ADC_CHANNEL_31_NUMBER | ADC_CHANNEL_31_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN31. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 739 | #endif /* ADC_SMPR0_SMP31 */ |
||
| 740 | #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. Channel common to both bank A and bank B. */ |
||
| 741 | #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. Channel common to both bank A and bank B. */ |
||
| 742 | #define LL_ADC_CHANNEL_VCOMP (LL_ADC_CHANNEL_26 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 743 | #if defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD) || defined (OPAMP_CSR_OPA3PD) |
||
| 744 | #define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 745 | #define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_8 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 746 | #if defined(OPAMP_CSR_OPA3PD) |
||
| 747 | #define LL_ADC_CHANNEL_VOPAMP3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 748 | #endif /* OPAMP_CSR_OPA3PD */ |
||
| 749 | #endif /* OPAMP_CSR_OPA1PD || OPAMP_CSR_OPA2PD || OPAMP_CSR_OPA3PD */ |
||
| 750 | /** |
||
| 751 | * @} |
||
| 752 | */ |
||
| 753 | |||
| 754 | /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source |
||
| 755 | * @{ |
||
| 756 | */ |
||
| 757 | #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */ |
||
| 758 | #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ |
||
| 759 | #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 760 | #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ |
||
| 761 | #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 762 | #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 763 | #define LL_ADC_REG_TRIG_EXT_TIM3_CH3 (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 764 | #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ |
||
| 765 | #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 766 | #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ |
||
| 767 | #define LL_ADC_REG_TRIG_EXT_TIM9_CH2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM9 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 768 | #define LL_ADC_REG_TRIG_EXT_TIM9_TRGO (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). */ |
||
| 769 | #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ |
||
| 770 | /** |
||
| 771 | * @} |
||
| 772 | */ |
||
| 773 | |||
| 774 | /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge |
||
| 775 | * @{ |
||
| 776 | */ |
||
| 777 | #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ |
||
| 778 | #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ |
||
| 779 | #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ |
||
| 780 | /** |
||
| 781 | * @} |
||
| 782 | */ |
||
| 783 | |||
| 784 | /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode |
||
| 785 | * @{ |
||
| 786 | */ |
||
| 787 | #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */ |
||
| 788 | #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ |
||
| 789 | /** |
||
| 790 | * @} |
||
| 791 | */ |
||
| 792 | |||
| 793 | /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data |
||
| 794 | * @{ |
||
| 795 | */ |
||
| 796 | #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */ |
||
| 797 | #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ |
||
| 798 | #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ |
||
| 799 | /** |
||
| 800 | * @} |
||
| 801 | */ |
||
| 802 | |||
| 803 | /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions) |
||
| 804 | * @{ |
||
| 805 | */ |
||
| 806 | #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */ |
||
| 807 | #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */ |
||
| 808 | /** |
||
| 809 | * @} |
||
| 810 | */ |
||
| 811 | |||
| 812 | /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length |
||
| 813 | * @{ |
||
| 814 | */ |
||
| 815 | #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ |
||
| 816 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ |
||
| 817 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ |
||
| 818 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ |
||
| 819 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ |
||
| 820 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ |
||
| 821 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ |
||
| 822 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ |
||
| 823 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS ( ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ |
||
| 824 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS ( ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ |
||
| 825 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS ( ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ |
||
| 826 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS ( ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ |
||
| 827 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS ( ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ |
||
| 828 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS ( ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ |
||
| 829 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS ( ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ |
||
| 830 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS ( ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ |
||
| 831 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS (ADC_SQR1_L_4 ) /*!< ADC group regular sequencer enable with 17 ranks in the sequence */ |
||
| 832 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_18RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 18 ranks in the sequence */ |
||
| 833 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_19RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 19 ranks in the sequence */ |
||
| 834 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_20RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 20 ranks in the sequence */ |
||
| 835 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_21RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 21 ranks in the sequence */ |
||
| 836 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_22RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 22 ranks in the sequence */ |
||
| 837 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_23RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 23 ranks in the sequence */ |
||
| 838 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_24RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 24 ranks in the sequence */ |
||
| 839 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_25RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 25 ranks in the sequence */ |
||
| 840 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_26RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 26 ranks in the sequence */ |
||
| 841 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_27RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 27 ranks in the sequence */ |
||
| 842 | #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
||
| 843 | #define LL_ADC_REG_SEQ_SCAN_ENABLE_28RANKS (ADC_SQR1_L_4 | ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 28 ranks in the sequence */ |
||
| 844 | #endif |
||
| 845 | /** |
||
| 846 | * @} |
||
| 847 | */ |
||
| 848 | |||
| 849 | /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode |
||
| 850 | * @{ |
||
| 851 | */ |
||
| 852 | #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */ |
||
| 853 | #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ |
||
| 854 | #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ |
||
| 855 | #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ |
||
| 856 | #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ |
||
| 857 | #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ |
||
| 858 | #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ |
||
| 859 | #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ |
||
| 860 | #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ |
||
| 861 | /** |
||
| 862 | * @} |
||
| 863 | */ |
||
| 864 | |||
| 865 | /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks |
||
| 866 | * @{ |
||
| 867 | */ |
||
| 868 | #define LL_ADC_REG_RANK_1 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ |
||
| 869 | #define LL_ADC_REG_RANK_2 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ |
||
| 870 | #define LL_ADC_REG_RANK_3 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ |
||
| 871 | #define LL_ADC_REG_RANK_4 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ |
||
| 872 | #define LL_ADC_REG_RANK_5 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ |
||
| 873 | #define LL_ADC_REG_RANK_6 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ |
||
| 874 | #define LL_ADC_REG_RANK_7 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ |
||
| 875 | #define LL_ADC_REG_RANK_8 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ |
||
| 876 | #define LL_ADC_REG_RANK_9 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ |
||
| 877 | #define LL_ADC_REG_RANK_10 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ |
||
| 878 | #define LL_ADC_REG_RANK_11 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ |
||
| 879 | #define LL_ADC_REG_RANK_12 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ |
||
| 880 | #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ |
||
| 881 | #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ |
||
| 882 | #define LL_ADC_REG_RANK_15 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ |
||
| 883 | #define LL_ADC_REG_RANK_16 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ |
||
| 884 | #define LL_ADC_REG_RANK_17 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_17_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 17 */ |
||
| 885 | #define LL_ADC_REG_RANK_18 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_18_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 18 */ |
||
| 886 | #define LL_ADC_REG_RANK_19 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_19_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 19 */ |
||
| 887 | #define LL_ADC_REG_RANK_20 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_20_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 20 */ |
||
| 888 | #define LL_ADC_REG_RANK_21 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_21_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 21 */ |
||
| 889 | #define LL_ADC_REG_RANK_22 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_22_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 22 */ |
||
| 890 | #define LL_ADC_REG_RANK_23 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_23_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 23 */ |
||
| 891 | #define LL_ADC_REG_RANK_24 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_24_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 24 */ |
||
| 892 | #define LL_ADC_REG_RANK_25 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_25_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 25 */ |
||
| 893 | #define LL_ADC_REG_RANK_26 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_26_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 26 */ |
||
| 894 | #define LL_ADC_REG_RANK_27 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_27_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 27 */ |
||
| 895 | #if defined(ADC_SQR1_SQ28) |
||
| 896 | #define LL_ADC_REG_RANK_28 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_28_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 28 */ |
||
| 897 | #endif |
||
| 898 | /** |
||
| 899 | * @} |
||
| 900 | */ |
||
| 901 | |||
| 902 | /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source |
||
| 903 | * @{ |
||
| 904 | */ |
||
| 905 | #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */ |
||
| 906 | #define LL_ADC_INJ_TRIG_EXT_TIM9_CH1 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM9 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 907 | #define LL_ADC_INJ_TRIG_EXT_TIM9_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). */ |
||
| 908 | #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ |
||
| 909 | #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 910 | #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 911 | #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ |
||
| 912 | #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 913 | #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 914 | #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 915 | #define LL_ADC_INJ_TRIG_EXT_TIM10_CH1 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM10 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ |
||
| 916 | #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ |
||
| 917 | #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ |
||
| 918 | /** |
||
| 919 | * @} |
||
| 920 | */ |
||
| 921 | |||
| 922 | /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge |
||
| 923 | * @{ |
||
| 924 | */ |
||
| 925 | #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ |
||
| 926 | #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ |
||
| 927 | #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ |
||
| 928 | /** |
||
| 929 | * @} |
||
| 930 | */ |
||
| 931 | |||
| 932 | /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode |
||
| 933 | * @{ |
||
| 934 | */ |
||
| 935 | #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ |
||
| 936 | #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ |
||
| 937 | /** |
||
| 938 | * @} |
||
| 939 | */ |
||
| 940 | |||
| 941 | |||
| 942 | /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length |
||
| 943 | * @{ |
||
| 944 | */ |
||
| 945 | #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ |
||
| 946 | #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ |
||
| 947 | #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ |
||
| 948 | #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ |
||
| 949 | /** |
||
| 950 | * @} |
||
| 951 | */ |
||
| 952 | |||
| 953 | /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode |
||
| 954 | * @{ |
||
| 955 | */ |
||
| 956 | #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */ |
||
| 957 | #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ |
||
| 958 | /** |
||
| 959 | * @} |
||
| 960 | */ |
||
| 961 | |||
| 962 | /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks |
||
| 963 | * @{ |
||
| 964 | */ |
||
| 965 | #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */ |
||
| 966 | #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */ |
||
| 967 | #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */ |
||
| 968 | #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */ |
||
| 969 | /** |
||
| 970 | * @} |
||
| 971 | */ |
||
| 972 | |||
| 973 | /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time |
||
| 974 | * @{ |
||
| 975 | */ |
||
| 976 | #define LL_ADC_SAMPLINGTIME_4CYCLES 0x00000000U /*!< Sampling time 4 ADC clock cycles */ |
||
| 977 | #define LL_ADC_SAMPLINGTIME_9CYCLES (ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */ |
||
| 978 | #define LL_ADC_SAMPLINGTIME_16CYCLES (ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */ |
||
| 979 | #define LL_ADC_SAMPLINGTIME_24CYCLES (ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0) /*!< Sampling time 24 ADC clock cycles */ |
||
| 980 | #define LL_ADC_SAMPLINGTIME_48CYCLES (ADC_SMPR3_SMP0_2) /*!< Sampling time 48 ADC clock cycles */ |
||
| 981 | #define LL_ADC_SAMPLINGTIME_96CYCLES (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0) /*!< Sampling time 96 ADC clock cycles */ |
||
| 982 | #define LL_ADC_SAMPLINGTIME_192CYCLES (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1) /*!< Sampling time 192 ADC clock cycles */ |
||
| 983 | #define LL_ADC_SAMPLINGTIME_384CYCLES (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0) /*!< Sampling time 384 ADC clock cycles */ |
||
| 984 | /** |
||
| 985 | * @} |
||
| 986 | */ |
||
| 987 | |||
| 988 | #if defined(COMP_CSR_FCH3) |
||
| 989 | /** @defgroup ADC_LL_EC_CHANNEL_ROUTING_LIST Channel - Routing channels list |
||
| 990 | * @{ |
||
| 991 | */ |
||
| 992 | #define LL_ADC_CHANNEL_3_ROUTING (COMP_CSR_FCH3) /*!< ADC channel 3 routing. Used as ADC direct channel (fast channel) if OPAMP1 is in power down mode. */ |
||
| 993 | #define LL_ADC_CHANNEL_8_ROUTING (COMP_CSR_FCH8) /*!< ADC channel 8 routing. Used as ADC direct channel (fast channel) if OPAMP2 is in power down mode. */ |
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| 994 | #define LL_ADC_CHANNEL_13_ROUTING (COMP_CSR_RCH13) /*!< ADC channel 13 routing. Used as ADC re-routed channel if OPAMP3 is in power down mode. Otherwise, channel 13 is connected to OPAMP3 output and routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. (Note: OPAMP3 is available on STM32L1 Cat.4 only). */ |
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| 995 | /** |
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| 996 | * @} |
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| 997 | */ |
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| 998 | |||
| 999 | /** @defgroup ADC_LL_EC_CHANNEL_ROUTING_SELECTION Channel - Routing selection |
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| 1000 | * @{ |
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| 1001 | */ |
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| 1002 | #define LL_ADC_CHANNEL_ROUTING_DEFAULT 0x00000000U /*!< ADC channel routing default: slow channel */ |
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| 1003 | #define LL_ADC_CHANNEL_ROUTING_DIRECT 0x00000001U /*!< ADC channel routing direct: fast channel. */ |
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| 1004 | /** |
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| 1005 | * @} |
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| 1006 | */ |
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| 1007 | #endif |
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| 1008 | |||
| 1009 | /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number |
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| 1010 | * @{ |
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| 1011 | */ |
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| 1012 | #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ |
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| 1013 | /** |
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| 1014 | * @} |
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| 1015 | */ |
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| 1016 | |||
| 1017 | /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels |
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| 1018 | * @{ |
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| 1019 | */ |
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| 1020 | #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */ |
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| 1021 | #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ |
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| 1022 | #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ |
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| 1023 | #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ |
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| 1024 | #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ |
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| 1025 | #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ |
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| 1026 | #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ |
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| 1027 | #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ |
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| 1028 | #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ |
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| 1029 | #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ |
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| 1030 | #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ |
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| 1031 | #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ |
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| 1032 | #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ |
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| 1033 | #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ |
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| 1034 | #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ |
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| 1035 | #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ |
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| 1036 | #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ |
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| 1037 | #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ |
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| 1038 | #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ |
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| 1039 | #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ |
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| 1040 | #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ |
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| 1041 | #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ |
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| 1042 | #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ |
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| 1043 | #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ |
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| 1044 | #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ |
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| 1045 | #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ |
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| 1046 | #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ |
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| 1047 | #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ |
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| 1048 | #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ |
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| 1049 | #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ |
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| 1050 | #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ |
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| 1051 | #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ |
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| 1052 | #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ |
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| 1053 | #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ |
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| 1054 | #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ |
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| 1055 | #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ |
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| 1056 | #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ |
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| 1057 | #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ |
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| 1058 | #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ |
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| 1059 | #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ |
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| 1060 | #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ |
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| 1061 | #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ |
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| 1062 | #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ |
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| 1063 | #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ |
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| 1064 | #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ |
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| 1065 | #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ |
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| 1066 | #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ |
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| 1067 | #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ |
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| 1068 | #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ |
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| 1069 | #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ |
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| 1070 | #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ |
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| 1071 | #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ |
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| 1072 | #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ |
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| 1073 | #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ |
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| 1074 | #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ |
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| 1075 | #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ |
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| 1076 | #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ |
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| 1077 | #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ |
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| 1078 | #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ |
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| 1079 | #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ |
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| 1080 | #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ |
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| 1081 | #define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */ |
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| 1082 | #define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */ |
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| 1083 | #define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */ |
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| 1084 | #define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by group regular only */ |
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| 1085 | #define LL_ADC_AWD_CHANNEL_20_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by group injected only */ |
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| 1086 | #define LL_ADC_AWD_CHANNEL_20_REG_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by either group regular or injected */ |
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| 1087 | #define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by group regular only */ |
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| 1088 | #define LL_ADC_AWD_CHANNEL_21_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by group injected only */ |
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| 1089 | #define LL_ADC_AWD_CHANNEL_21_REG_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by either group regular or injected */ |
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| 1090 | #define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by group regular only */ |
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| 1091 | #define LL_ADC_AWD_CHANNEL_22_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by group injected only */ |
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| 1092 | #define LL_ADC_AWD_CHANNEL_22_REG_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by either group regular or injected */ |
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| 1093 | #define LL_ADC_AWD_CHANNEL_23_REG ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by group regular only */ |
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| 1094 | #define LL_ADC_AWD_CHANNEL_23_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by group injected only */ |
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| 1095 | #define LL_ADC_AWD_CHANNEL_23_REG_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by either group regular or injected */ |
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| 1096 | #define LL_ADC_AWD_CHANNEL_24_REG ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by group regular only */ |
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| 1097 | #define LL_ADC_AWD_CHANNEL_24_INJ ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by group injected only */ |
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| 1098 | #define LL_ADC_AWD_CHANNEL_24_REG_INJ ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by either group regular or injected */ |
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| 1099 | #define LL_ADC_AWD_CHANNEL_25_REG ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by group regular only */ |
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| 1100 | #define LL_ADC_AWD_CHANNEL_25_INJ ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by group injected only */ |
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| 1101 | #define LL_ADC_AWD_CHANNEL_25_REG_INJ ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by either group regular or injected */ |
||
| 1102 | #define LL_ADC_AWD_CHANNEL_26_REG ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by group regular only */ |
||
| 1103 | #define LL_ADC_AWD_CHANNEL_26_INJ ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by group injected only */ |
||
| 1104 | #define LL_ADC_AWD_CHANNEL_26_REG_INJ ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by either group regular or injected */ |
||
| 1105 | #if defined(ADC_SMPR0_SMP31) |
||
| 1106 | #define LL_ADC_AWD_CHANNEL_27_REG ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1107 | #define LL_ADC_AWD_CHANNEL_27_INJ ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1108 | #define LL_ADC_AWD_CHANNEL_27_REG_INJ ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1109 | #define LL_ADC_AWD_CHANNEL_28_REG ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1110 | #define LL_ADC_AWD_CHANNEL_28_INJ ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1111 | #define LL_ADC_AWD_CHANNEL_28_REG_INJ ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1112 | #define LL_ADC_AWD_CHANNEL_29_REG ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1113 | #define LL_ADC_AWD_CHANNEL_29_INJ ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1114 | #define LL_ADC_AWD_CHANNEL_29_REG_INJ ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1115 | #define LL_ADC_AWD_CHANNEL_30_REG ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1116 | #define LL_ADC_AWD_CHANNEL_30_INJ ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1117 | #define LL_ADC_AWD_CHANNEL_30_REG_INJ ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1118 | #define LL_ADC_AWD_CHANNEL_31_REG ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1119 | #define LL_ADC_AWD_CHANNEL_31_INJ ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1120 | #define LL_ADC_AWD_CHANNEL_31_REG_INJ ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 1121 | #endif /* ADC_SMPR0_SMP31 */ |
||
| 1122 | #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only. Channel common to both bank A and bank B. */ |
||
| 1123 | #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only. Channel common to both bank A and bank B. */ |
||
| 1124 | #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected. Channel common to both bank A and bank B. */ |
||
| 1125 | #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. Channel common to both bank A and bank B. */ |
||
| 1126 | #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. Channel common to both bank A and bank B. */ |
||
| 1127 | #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. Channel common to both bank A and bank B. */ |
||
| 1128 | #define LL_ADC_AWD_CH_VCOMP_REG ((LL_ADC_CHANNEL_VCOMP & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1129 | #define LL_ADC_AWD_CH_VCOMP_INJ ((LL_ADC_CHANNEL_VCOMP & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1130 | #define LL_ADC_AWD_CH_VCOMP_REG_INJ ((LL_ADC_CHANNEL_VCOMP & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1131 | #if defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD) || defined (OPAMP_CSR_OPA3PD) |
||
| 1132 | #define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1133 | #define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1134 | #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1135 | #define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1136 | #define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1137 | #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1138 | #if defined(OPAMP_CSR_OPA3PD) |
||
| 1139 | #define LL_ADC_AWD_CH_VOPAMP3_REG ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1140 | #define LL_ADC_AWD_CH_VOPAMP3_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1141 | #define LL_ADC_AWD_CH_VOPAMP3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */ |
||
| 1142 | #endif /* OPAMP_CSR_OPA3PD */ |
||
| 1143 | #endif /* OPAMP_CSR_OPA1PD || OPAMP_CSR_OPA2PD || OPAMP_CSR_OPA3PD */ |
||
| 1144 | /** |
||
| 1145 | * @} |
||
| 1146 | */ |
||
| 1147 | |||
| 1148 | /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds |
||
| 1149 | * @{ |
||
| 1150 | */ |
||
| 1151 | #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ |
||
| 1152 | #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ |
||
| 1153 | /** |
||
| 1154 | * @} |
||
| 1155 | */ |
||
| 1156 | |||
| 1157 | |||
| 1158 | /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays |
||
| 1159 | * @note Only ADC IP HW delays are defined in ADC LL driver driver, |
||
| 1160 | * not timeout values. |
||
| 1161 | * For details on delays values, refer to descriptions in source code |
||
| 1162 | * above each literal definition. |
||
| 1163 | * @{ |
||
| 1164 | */ |
||
| 1165 | |||
| 1166 | /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ |
||
| 1167 | /* not timeout values. */ |
||
| 1168 | /* Timeout values for ADC operations are dependent to device clock */ |
||
| 1169 | /* configuration (system clock versus ADC clock), */ |
||
| 1170 | /* and therefore must be defined in user application. */ |
||
| 1171 | /* Indications for estimation of ADC timeout delays, for this */ |
||
| 1172 | /* STM32 series: */ |
||
| 1173 | /* - ADC enable time: maximum delay is 3.5us */ |
||
| 1174 | /* (refer to device datasheet, parameter "tSTAB") */ |
||
| 1175 | /* - ADC conversion time: duration depending on ADC clock and ADC */ |
||
| 1176 | /* configuration. */ |
||
| 1177 | /* (refer to device reference manual, section "Timing") */ |
||
| 1178 | |||
| 1179 | /* Delay for internal voltage reference stabilization time. */ |
||
| 1180 | /* Delay set to maximum value (refer to device datasheet, */ |
||
| 1181 | /* parameter "TADC_BUF"). */ |
||
| 1182 | /* Unit: us */ |
||
| 1183 | #define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ |
||
| 1184 | |||
| 1185 | /* Delay for temperature sensor stabilization time. */ |
||
| 1186 | /* Literal set to maximum value (refer to device datasheet, */ |
||
| 1187 | /* parameter "tSTART"). */ |
||
| 1188 | /* Unit: us */ |
||
| 1189 | #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ |
||
| 1190 | |||
| 1191 | /** |
||
| 1192 | * @} |
||
| 1193 | */ |
||
| 1194 | |||
| 1195 | /** |
||
| 1196 | * @} |
||
| 1197 | */ |
||
| 1198 | |||
| 1199 | |||
| 1200 | /* Exported macro ------------------------------------------------------------*/ |
||
| 1201 | /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros |
||
| 1202 | * @{ |
||
| 1203 | */ |
||
| 1204 | |||
| 1205 | /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros |
||
| 1206 | * @{ |
||
| 1207 | */ |
||
| 1208 | |||
| 1209 | /** |
||
| 1210 | * @brief Write a value in ADC register |
||
| 1211 | * @param __INSTANCE__ ADC Instance |
||
| 1212 | * @param __REG__ Register to be written |
||
| 1213 | * @param __VALUE__ Value to be written in the register |
||
| 1214 | * @retval None |
||
| 1215 | */ |
||
| 1216 | #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
||
| 1217 | |||
| 1218 | /** |
||
| 1219 | * @brief Read a value in ADC register |
||
| 1220 | * @param __INSTANCE__ ADC Instance |
||
| 1221 | * @param __REG__ Register to be read |
||
| 1222 | * @retval Register value |
||
| 1223 | */ |
||
| 1224 | #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
||
| 1225 | /** |
||
| 1226 | * @} |
||
| 1227 | */ |
||
| 1228 | |||
| 1229 | /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro |
||
| 1230 | * @{ |
||
| 1231 | */ |
||
| 1232 | |||
| 1233 | /** |
||
| 1234 | * @brief Helper macro to get ADC channel number in decimal format |
||
| 1235 | * from literals LL_ADC_CHANNEL_x. |
||
| 1236 | * @note Example: |
||
| 1237 | * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) |
||
| 1238 | * will return decimal number "4". |
||
| 1239 | * @note The input can be a value from functions where a channel |
||
| 1240 | * number is returned, either defined with number |
||
| 1241 | * or with bitfield (only one bit must be set). |
||
| 1242 | * @param __CHANNEL__ This parameter can be one of the following values: |
||
| 1243 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 1244 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 1245 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 1246 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 1247 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 1248 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 1249 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 1250 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 1251 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 1252 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 1253 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 1254 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 1255 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 1256 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 1257 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 1258 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 1259 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 1260 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 1261 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 1262 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 1263 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 1264 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 1265 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 1266 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 1267 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 1268 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 1269 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 1270 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 1271 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 1272 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 1273 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 1274 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 1275 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3) |
||
| 1276 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3) |
||
| 1277 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3) |
||
| 1278 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 1279 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 1280 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 1281 | * |
||
| 1282 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 1283 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 1284 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 1285 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 1286 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5 |
||
| 1287 | * @retval Value between Min_Data=0 and Max_Data=18 |
||
| 1288 | */ |
||
| 1289 | #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ |
||
| 1290 | (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) |
||
| 1291 | |||
| 1292 | /** |
||
| 1293 | * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x |
||
| 1294 | * from number in decimal format. |
||
| 1295 | * @note Example: |
||
| 1296 | * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) |
||
| 1297 | * will return a data equivalent to "LL_ADC_CHANNEL_4". |
||
| 1298 | * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 |
||
| 1299 | * @retval Returned value can be one of the following values: |
||
| 1300 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 1301 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 1302 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 1303 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 1304 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 1305 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 1306 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 1307 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 1308 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 1309 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 1310 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 1311 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 1312 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 1313 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 1314 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 1315 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 1316 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 1317 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 1318 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 1319 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 1320 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 1321 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 1322 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 1323 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 1324 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 1325 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 1326 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 1327 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 1328 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 1329 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 1330 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 1331 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 1332 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6) |
||
| 1333 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6) |
||
| 1334 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6) |
||
| 1335 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 1336 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 1337 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 1338 | * |
||
| 1339 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 1340 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 1341 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 1342 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 1343 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n |
||
| 1344 | * (6) For ADC channel read back from ADC register, |
||
| 1345 | * comparison with internal channel parameter to be done |
||
| 1346 | * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). |
||
| 1347 | */ |
||
| 1348 | #if defined(ADC_SMPR0_SMP31) |
||
| 1349 | #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ |
||
| 1350 | (((__DECIMAL_NB__) <= 9U) \ |
||
| 1351 | ? ( \ |
||
| 1352 | ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ |
||
| 1353 | (ADC_SMPR3_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ |
||
| 1354 | ) \ |
||
| 1355 | : \ |
||
| 1356 | (((__DECIMAL_NB__) <= 19U) \ |
||
| 1357 | ? ( \ |
||
| 1358 | ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ |
||
| 1359 | (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ |
||
| 1360 | ) \ |
||
| 1361 | : \ |
||
| 1362 | (((__DECIMAL_NB__) <= 28U) \ |
||
| 1363 | ? ( \ |
||
| 1364 | ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ |
||
| 1365 | (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -20U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ |
||
| 1366 | ) \ |
||
| 1367 | : \ |
||
| 1368 | ( \ |
||
| 1369 | ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ |
||
| 1370 | (ADC_SMPR0_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 30U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ |
||
| 1371 | ) \ |
||
| 1372 | ) \ |
||
| 1373 | ) \ |
||
| 1374 | ) |
||
| 1375 | #else |
||
| 1376 | #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ |
||
| 1377 | (((__DECIMAL_NB__) <= 9U) \ |
||
| 1378 | ? ( \ |
||
| 1379 | ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ |
||
| 1380 | (ADC_SMPR3_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ |
||
| 1381 | ) \ |
||
| 1382 | : \ |
||
| 1383 | (((__DECIMAL_NB__) <= 19U) \ |
||
| 1384 | ? ( \ |
||
| 1385 | ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ |
||
| 1386 | (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ |
||
| 1387 | ) \ |
||
| 1388 | : \ |
||
| 1389 | ( \ |
||
| 1390 | ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ |
||
| 1391 | (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -20U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ |
||
| 1392 | ) \ |
||
| 1393 | ) \ |
||
| 1394 | ) |
||
| 1395 | #endif /* ADC_SMPR0_SMP31 */ |
||
| 1396 | |||
| 1397 | /** |
||
| 1398 | * @brief Helper macro to determine whether the selected channel |
||
| 1399 | * corresponds to literal definitions of driver. |
||
| 1400 | * @note The different literal definitions of ADC channels are: |
||
| 1401 | * - ADC internal channel: |
||
| 1402 | * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... |
||
| 1403 | * - ADC external channel (channel connected to a GPIO pin): |
||
| 1404 | * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... |
||
| 1405 | * @note The channel parameter must be a value defined from literal |
||
| 1406 | * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, |
||
| 1407 | * LL_ADC_CHANNEL_TEMPSENSOR, ...), |
||
| 1408 | * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), |
||
| 1409 | * must not be a value from functions where a channel number is |
||
| 1410 | * returned from ADC registers, |
||
| 1411 | * because internal and external channels share the same channel |
||
| 1412 | * number in ADC registers. The differentiation is made only with |
||
| 1413 | * parameters definitions of driver. |
||
| 1414 | * @param __CHANNEL__ This parameter can be one of the following values: |
||
| 1415 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 1416 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 1417 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 1418 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 1419 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 1420 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 1421 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 1422 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 1423 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 1424 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 1425 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 1426 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 1427 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 1428 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 1429 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 1430 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 1431 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 1432 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 1433 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 1434 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 1435 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 1436 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 1437 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 1438 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 1439 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 1440 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 1441 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 1442 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 1443 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 1444 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 1445 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 1446 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 1447 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3) |
||
| 1448 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3) |
||
| 1449 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3) |
||
| 1450 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 1451 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 1452 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 1453 | * |
||
| 1454 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 1455 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 1456 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 1457 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 1458 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5 |
||
| 1459 | * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). |
||
| 1460 | * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. |
||
| 1461 | */ |
||
| 1462 | #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ |
||
| 1463 | (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) |
||
| 1464 | |||
| 1465 | /** |
||
| 1466 | * @brief Helper macro to convert a channel defined from parameter |
||
| 1467 | * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, |
||
| 1468 | * LL_ADC_CHANNEL_TEMPSENSOR, ...), |
||
| 1469 | * to its equivalent parameter definition of a ADC external channel |
||
| 1470 | * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). |
||
| 1471 | * @note The channel parameter can be, additionally to a value |
||
| 1472 | * defined from parameter definition of a ADC internal channel |
||
| 1473 | * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), |
||
| 1474 | * a value defined from parameter definition of |
||
| 1475 | * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) |
||
| 1476 | * or a value from functions where a channel number is returned |
||
| 1477 | * from ADC registers. |
||
| 1478 | * @param __CHANNEL__ This parameter can be one of the following values: |
||
| 1479 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 1480 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 1481 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 1482 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 1483 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 1484 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 1485 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 1486 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 1487 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 1488 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 1489 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 1490 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 1491 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 1492 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 1493 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 1494 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 1495 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 1496 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 1497 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 1498 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 1499 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 1500 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 1501 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 1502 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 1503 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 1504 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 1505 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 1506 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 1507 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 1508 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 1509 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 1510 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 1511 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3) |
||
| 1512 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3) |
||
| 1513 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3) |
||
| 1514 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 1515 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 1516 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 1517 | * |
||
| 1518 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 1519 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 1520 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 1521 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 1522 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5 |
||
| 1523 | * @retval Returned value can be one of the following values: |
||
| 1524 | * @arg @ref LL_ADC_CHANNEL_0 |
||
| 1525 | * @arg @ref LL_ADC_CHANNEL_1 |
||
| 1526 | * @arg @ref LL_ADC_CHANNEL_2 |
||
| 1527 | * @arg @ref LL_ADC_CHANNEL_3 |
||
| 1528 | * @arg @ref LL_ADC_CHANNEL_4 |
||
| 1529 | * @arg @ref LL_ADC_CHANNEL_5 |
||
| 1530 | * @arg @ref LL_ADC_CHANNEL_6 |
||
| 1531 | * @arg @ref LL_ADC_CHANNEL_7 |
||
| 1532 | * @arg @ref LL_ADC_CHANNEL_8 |
||
| 1533 | * @arg @ref LL_ADC_CHANNEL_9 |
||
| 1534 | * @arg @ref LL_ADC_CHANNEL_10 |
||
| 1535 | * @arg @ref LL_ADC_CHANNEL_11 |
||
| 1536 | * @arg @ref LL_ADC_CHANNEL_12 |
||
| 1537 | * @arg @ref LL_ADC_CHANNEL_13 |
||
| 1538 | * @arg @ref LL_ADC_CHANNEL_14 |
||
| 1539 | * @arg @ref LL_ADC_CHANNEL_15 |
||
| 1540 | * @arg @ref LL_ADC_CHANNEL_16 |
||
| 1541 | * @arg @ref LL_ADC_CHANNEL_17 |
||
| 1542 | * @arg @ref LL_ADC_CHANNEL_18 |
||
| 1543 | */ |
||
| 1544 | #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ |
||
| 1545 | ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) |
||
| 1546 | |||
| 1547 | /** |
||
| 1548 | * @brief Helper macro to determine whether the internal channel |
||
| 1549 | * selected is available on the ADC instance selected. |
||
| 1550 | * @note The channel parameter must be a value defined from parameter |
||
| 1551 | * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, |
||
| 1552 | * LL_ADC_CHANNEL_TEMPSENSOR, ...), |
||
| 1553 | * must not be a value defined from parameter definition of |
||
| 1554 | * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) |
||
| 1555 | * or a value from functions where a channel number is |
||
| 1556 | * returned from ADC registers, |
||
| 1557 | * because internal and external channels share the same channel |
||
| 1558 | * number in ADC registers. The differentiation is made only with |
||
| 1559 | * parameters definitions of driver. |
||
| 1560 | * @param __ADC_INSTANCE__ ADC instance |
||
| 1561 | * @param __CHANNEL__ This parameter can be one of the following values: |
||
| 1562 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3) |
||
| 1563 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3) |
||
| 1564 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3) |
||
| 1565 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 1566 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 1567 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 1568 | * |
||
| 1569 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 1570 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 1571 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 1572 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 1573 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5 |
||
| 1574 | * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. |
||
| 1575 | * Value "1" if the internal channel selected is available on the ADC instance selected. |
||
| 1576 | */ |
||
| 1577 | #if defined (OPAMP_CSR_OPA3PD) |
||
| 1578 | #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ |
||
| 1579 | ( \ |
||
| 1580 | ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ |
||
| 1581 | ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ |
||
| 1582 | ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP) || \ |
||
| 1583 | ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ |
||
| 1584 | ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ |
||
| 1585 | ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3) \ |
||
| 1586 | ) |
||
| 1587 | #elif defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD) |
||
| 1588 | #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ |
||
| 1589 | ( \ |
||
| 1590 | ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ |
||
| 1591 | ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ |
||
| 1592 | ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP) || \ |
||
| 1593 | ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ |
||
| 1594 | ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \ |
||
| 1595 | ) |
||
| 1596 | #else |
||
| 1597 | #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ |
||
| 1598 | ( \ |
||
| 1599 | ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ |
||
| 1600 | ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ |
||
| 1601 | ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP) \ |
||
| 1602 | ) |
||
| 1603 | #endif |
||
| 1604 | |||
| 1605 | /** |
||
| 1606 | * @brief Helper macro to define ADC analog watchdog parameter: |
||
| 1607 | * define a single channel to monitor with analog watchdog |
||
| 1608 | * from sequencer channel and groups definition. |
||
| 1609 | * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). |
||
| 1610 | * Example: |
||
| 1611 | * LL_ADC_SetAnalogWDMonitChannels( |
||
| 1612 | * ADC1, LL_ADC_AWD1, |
||
| 1613 | * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) |
||
| 1614 | * @param __CHANNEL__ This parameter can be one of the following values: |
||
| 1615 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 1616 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 1617 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 1618 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 1619 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 1620 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 1621 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 1622 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 1623 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 1624 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 1625 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 1626 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 1627 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 1628 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 1629 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 1630 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 1631 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 1632 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 1633 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 1634 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 1635 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 1636 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 1637 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 1638 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 1639 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 1640 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 1641 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 1642 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 1643 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 1644 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 1645 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 1646 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 1647 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6) |
||
| 1648 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6) |
||
| 1649 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6) |
||
| 1650 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 1651 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 1652 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 1653 | * |
||
| 1654 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 1655 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 1656 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 1657 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 1658 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n |
||
| 1659 | * (6) For ADC channel read back from ADC register, |
||
| 1660 | * comparison with internal channel parameter to be done |
||
| 1661 | * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). |
||
| 1662 | * @param __GROUP__ This parameter can be one of the following values: |
||
| 1663 | * @arg @ref LL_ADC_GROUP_REGULAR |
||
| 1664 | * @arg @ref LL_ADC_GROUP_INJECTED |
||
| 1665 | * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED |
||
| 1666 | * @retval Returned value can be one of the following values: |
||
| 1667 | * @arg @ref LL_ADC_AWD_DISABLE |
||
| 1668 | * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG |
||
| 1669 | * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ |
||
| 1670 | * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ |
||
| 1671 | * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (2) |
||
| 1672 | * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (2) |
||
| 1673 | * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (2) |
||
| 1674 | * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (2) |
||
| 1675 | * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (2) |
||
| 1676 | * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (2) |
||
| 1677 | * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (2) |
||
| 1678 | * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (2) |
||
| 1679 | * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (2) |
||
| 1680 | * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (2) |
||
| 1681 | * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (2) |
||
| 1682 | * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (2) |
||
| 1683 | * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (1) |
||
| 1684 | * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (1) |
||
| 1685 | * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1) |
||
| 1686 | * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (1) |
||
| 1687 | * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (1) |
||
| 1688 | * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1) |
||
| 1689 | * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (2) |
||
| 1690 | * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (2) |
||
| 1691 | * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (2) |
||
| 1692 | * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (2) |
||
| 1693 | * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (2) |
||
| 1694 | * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (2) |
||
| 1695 | * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (2) |
||
| 1696 | * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (2) |
||
| 1697 | * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (2) |
||
| 1698 | * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (2) |
||
| 1699 | * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (2) |
||
| 1700 | * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (2) |
||
| 1701 | * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (2) |
||
| 1702 | * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (2) |
||
| 1703 | * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (2) |
||
| 1704 | * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (2) |
||
| 1705 | * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (2) |
||
| 1706 | * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (2) |
||
| 1707 | * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (2) |
||
| 1708 | * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (2) |
||
| 1709 | * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (2) |
||
| 1710 | * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (3) |
||
| 1711 | * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (3) |
||
| 1712 | * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (3) |
||
| 1713 | * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (3) |
||
| 1714 | * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (3) |
||
| 1715 | * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (3) |
||
| 1716 | * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (3) |
||
| 1717 | * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (3) |
||
| 1718 | * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (3) |
||
| 1719 | * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (3) |
||
| 1720 | * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (3) |
||
| 1721 | * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (3) |
||
| 1722 | * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (3) |
||
| 1723 | * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (3) |
||
| 1724 | * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (3) |
||
| 1725 | * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (3) |
||
| 1726 | * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (3) |
||
| 1727 | * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (3) |
||
| 1728 | * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (3) |
||
| 1729 | * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (3) |
||
| 1730 | * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ (3) |
||
| 1731 | * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (3) |
||
| 1732 | * @arg @ref LL_ADC_AWD_CHANNEL_20_INJ (3) |
||
| 1733 | * @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ (3) |
||
| 1734 | * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (3) |
||
| 1735 | * @arg @ref LL_ADC_AWD_CHANNEL_21_INJ (3) |
||
| 1736 | * @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ (3) |
||
| 1737 | * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1) |
||
| 1738 | * @arg @ref LL_ADC_AWD_CHANNEL_22_INJ (1) |
||
| 1739 | * @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ (1) |
||
| 1740 | * @arg @ref LL_ADC_AWD_CHANNEL_23_REG (1) |
||
| 1741 | * @arg @ref LL_ADC_AWD_CHANNEL_23_INJ (1) |
||
| 1742 | * @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ (1) |
||
| 1743 | * @arg @ref LL_ADC_AWD_CHANNEL_24_REG (1) |
||
| 1744 | * @arg @ref LL_ADC_AWD_CHANNEL_24_INJ (1) |
||
| 1745 | * @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ (1) |
||
| 1746 | * @arg @ref LL_ADC_AWD_CHANNEL_25_REG (1) |
||
| 1747 | * @arg @ref LL_ADC_AWD_CHANNEL_25_INJ (1) |
||
| 1748 | * @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ (1) |
||
| 1749 | * @arg @ref LL_ADC_AWD_CHANNEL_26_REG (3) |
||
| 1750 | * @arg @ref LL_ADC_AWD_CHANNEL_26_INJ (3) |
||
| 1751 | * @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ (3) |
||
| 1752 | * @arg @ref LL_ADC_AWD_CHANNEL_27_REG (3)(4) |
||
| 1753 | * @arg @ref LL_ADC_AWD_CHANNEL_27_INJ (3)(4) |
||
| 1754 | * @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ (3)(4) |
||
| 1755 | * @arg @ref LL_ADC_AWD_CHANNEL_28_REG (3)(4) |
||
| 1756 | * @arg @ref LL_ADC_AWD_CHANNEL_28_INJ (3)(4) |
||
| 1757 | * @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ (3)(4) |
||
| 1758 | * @arg @ref LL_ADC_AWD_CHANNEL_29_REG (3)(4) |
||
| 1759 | * @arg @ref LL_ADC_AWD_CHANNEL_29_INJ (3)(4) |
||
| 1760 | * @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ (3)(4) |
||
| 1761 | * @arg @ref LL_ADC_AWD_CHANNEL_30_REG (3)(4) |
||
| 1762 | * @arg @ref LL_ADC_AWD_CHANNEL_30_INJ (3)(4) |
||
| 1763 | * @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ (3)(4) |
||
| 1764 | * @arg @ref LL_ADC_AWD_CHANNEL_31_REG (3)(4) |
||
| 1765 | * @arg @ref LL_ADC_AWD_CHANNEL_31_INJ (3)(4) |
||
| 1766 | * @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ (3)(4) |
||
| 1767 | * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (3) |
||
| 1768 | * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (3) |
||
| 1769 | * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (3) |
||
| 1770 | * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (3) |
||
| 1771 | * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (3) |
||
| 1772 | * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (3) |
||
| 1773 | * @arg @ref LL_ADC_AWD_CH_VCOMP_REG (3) |
||
| 1774 | * @arg @ref LL_ADC_AWD_CH_VCOMP_INJ (3) |
||
| 1775 | * @arg @ref LL_ADC_AWD_CH_VCOMP_REG_INJ (3) |
||
| 1776 | * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (3)(5) |
||
| 1777 | * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (3)(5) |
||
| 1778 | * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (3)(5) |
||
| 1779 | * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (3)(5) |
||
| 1780 | * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (3)(5) |
||
| 1781 | * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (3)(5) |
||
| 1782 | * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (3)(5) |
||
| 1783 | * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (3)(5) |
||
| 1784 | * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)(5) |
||
| 1785 | * |
||
| 1786 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 1787 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 1788 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 1789 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 1790 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5 |
||
| 1791 | */ |
||
| 1792 | #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ |
||
| 1793 | (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ |
||
| 1794 | ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ |
||
| 1795 | : \ |
||
| 1796 | ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ |
||
| 1797 | ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ |
||
| 1798 | : \ |
||
| 1799 | (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ |
||
| 1800 | ) |
||
| 1801 | |||
| 1802 | /** |
||
| 1803 | * @brief Helper macro to set the value of ADC analog watchdog threshold high |
||
| 1804 | * or low in function of ADC resolution, when ADC resolution is |
||
| 1805 | * different of 12 bits. |
||
| 1806 | * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). |
||
| 1807 | * Example, with a ADC resolution of 8 bits, to set the value of |
||
| 1808 | * analog watchdog threshold high (on 8 bits): |
||
| 1809 | * LL_ADC_SetAnalogWDThresholds |
||
| 1810 | * (< ADCx param >, |
||
| 1811 | * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) |
||
| 1812 | * ); |
||
| 1813 | * @param __ADC_RESOLUTION__ This parameter can be one of the following values: |
||
| 1814 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 1815 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 1816 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 1817 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 1818 | * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1819 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1820 | */ |
||
| 1821 | #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ |
||
| 1822 | ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) |
||
| 1823 | |||
| 1824 | /** |
||
| 1825 | * @brief Helper macro to get the value of ADC analog watchdog threshold high |
||
| 1826 | * or low in function of ADC resolution, when ADC resolution is |
||
| 1827 | * different of 12 bits. |
||
| 1828 | * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). |
||
| 1829 | * Example, with a ADC resolution of 8 bits, to get the value of |
||
| 1830 | * analog watchdog threshold high (on 8 bits): |
||
| 1831 | * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION |
||
| 1832 | * (LL_ADC_RESOLUTION_8B, |
||
| 1833 | * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) |
||
| 1834 | * ); |
||
| 1835 | * @param __ADC_RESOLUTION__ This parameter can be one of the following values: |
||
| 1836 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 1837 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 1838 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 1839 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 1840 | * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1841 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 1842 | */ |
||
| 1843 | #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ |
||
| 1844 | ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) |
||
| 1845 | |||
| 1846 | /** |
||
| 1847 | * @brief Helper macro to select the ADC common instance |
||
| 1848 | * to which is belonging the selected ADC instance. |
||
| 1849 | * @note ADC common register instance can be used for: |
||
| 1850 | * - Set parameters common to several ADC instances |
||
| 1851 | * - Multimode (for devices with several ADC instances) |
||
| 1852 | * Refer to functions having argument "ADCxy_COMMON" as parameter. |
||
| 1853 | * @param __ADCx__ ADC instance |
||
| 1854 | * @retval ADC common register instance |
||
| 1855 | */ |
||
| 1856 | #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ |
||
| 1857 | (ADC1_COMMON) |
||
| 1858 | |||
| 1859 | /** |
||
| 1860 | * @brief Helper macro to check if all ADC instances sharing the same |
||
| 1861 | * ADC common instance are disabled. |
||
| 1862 | * @note This check is required by functions with setting conditioned to |
||
| 1863 | * ADC state: |
||
| 1864 | * All ADC instances of the ADC common group must be disabled. |
||
| 1865 | * Refer to functions having argument "ADCxy_COMMON" as parameter. |
||
| 1866 | * @note On devices with only 1 ADC common instance, parameter of this macro |
||
| 1867 | * is useless and can be ignored (parameter kept for compatibility |
||
| 1868 | * with devices featuring several ADC common instances). |
||
| 1869 | * @param __ADCXY_COMMON__ ADC common instance |
||
| 1870 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
||
| 1871 | * @retval Value "0" if all ADC instances sharing the same ADC common instance |
||
| 1872 | * are disabled. |
||
| 1873 | * Value "1" if at least one ADC instance sharing the same ADC common instance |
||
| 1874 | * is enabled. |
||
| 1875 | */ |
||
| 1876 | #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ |
||
| 1877 | LL_ADC_IsEnabled(ADC1) |
||
| 1878 | |||
| 1879 | /** |
||
| 1880 | * @brief Helper macro to define the ADC conversion data full-scale digital |
||
| 1881 | * value corresponding to the selected ADC resolution. |
||
| 1882 | * @note ADC conversion data full-scale corresponds to voltage range |
||
| 1883 | * determined by analog voltage references Vref+ and Vref- |
||
| 1884 | * (refer to reference manual). |
||
| 1885 | * @param __ADC_RESOLUTION__ This parameter can be one of the following values: |
||
| 1886 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 1887 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 1888 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 1889 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 1890 | * @retval ADC conversion data equivalent voltage value (unit: mVolt) |
||
| 1891 | */ |
||
| 1892 | #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ |
||
| 1893 | (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) |
||
| 1894 | |||
| 1895 | /** |
||
| 1896 | * @brief Helper macro to convert the ADC conversion data from |
||
| 1897 | * a resolution to another resolution. |
||
| 1898 | * @param __DATA__ ADC conversion data to be converted |
||
| 1899 | * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted |
||
| 1900 | * This parameter can be one of the following values: |
||
| 1901 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 1902 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 1903 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 1904 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 1905 | * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion |
||
| 1906 | * This parameter can be one of the following values: |
||
| 1907 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 1908 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 1909 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 1910 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 1911 | * @retval ADC conversion data to the requested resolution |
||
| 1912 | */ |
||
| 1913 | #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \ |
||
| 1914 | (((__DATA__) \ |
||
| 1915 | << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \ |
||
| 1916 | >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \ |
||
| 1917 | ) |
||
| 1918 | |||
| 1919 | /** |
||
| 1920 | * @brief Helper macro to calculate the voltage (unit: mVolt) |
||
| 1921 | * corresponding to a ADC conversion data (unit: digital value). |
||
| 1922 | * @note Analog reference voltage (Vref+) must be either known from |
||
| 1923 | * user board environment or can be calculated using ADC measurement |
||
| 1924 | * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). |
||
| 1925 | * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) |
||
| 1926 | * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) |
||
| 1927 | * (unit: digital value). |
||
| 1928 | * @param __ADC_RESOLUTION__ This parameter can be one of the following values: |
||
| 1929 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 1930 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 1931 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 1932 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 1933 | * @retval ADC conversion data equivalent voltage value (unit: mVolt) |
||
| 1934 | */ |
||
| 1935 | #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ |
||
| 1936 | __ADC_DATA__,\ |
||
| 1937 | __ADC_RESOLUTION__) \ |
||
| 1938 | ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ |
||
| 1939 | / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ |
||
| 1940 | ) |
||
| 1941 | |||
| 1942 | /** |
||
| 1943 | * @brief Helper macro to calculate analog reference voltage (Vref+) |
||
| 1944 | * (unit: mVolt) from ADC conversion data of internal voltage |
||
| 1945 | * reference VrefInt. |
||
| 1946 | * @note Computation is using VrefInt calibration value |
||
| 1947 | * stored in system memory for each device during production. |
||
| 1948 | * @note This voltage depends on user board environment: voltage level |
||
| 1949 | * connected to pin Vref+. |
||
| 1950 | * On devices with small package, the pin Vref+ is not present |
||
| 1951 | * and internally bonded to pin Vdda. |
||
| 1952 | * @note On this STM32 series, calibration data of internal voltage reference |
||
| 1953 | * VrefInt corresponds to a resolution of 12 bits, |
||
| 1954 | * this is the recommended ADC resolution to convert voltage of |
||
| 1955 | * internal voltage reference VrefInt. |
||
| 1956 | * Otherwise, this macro performs the processing to scale |
||
| 1957 | * ADC conversion data to 12 bits. |
||
| 1958 | * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) |
||
| 1959 | * of internal voltage reference VrefInt (unit: digital value). |
||
| 1960 | * @param __ADC_RESOLUTION__ This parameter can be one of the following values: |
||
| 1961 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 1962 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 1963 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 1964 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 1965 | * @retval Analog reference voltage (unit: mV) |
||
| 1966 | */ |
||
| 1967 | #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ |
||
| 1968 | __ADC_RESOLUTION__) \ |
||
| 1969 | (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ |
||
| 1970 | / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ |
||
| 1971 | (__ADC_RESOLUTION__), \ |
||
| 1972 | LL_ADC_RESOLUTION_12B) \ |
||
| 1973 | ) |
||
| 1974 | |||
| 1975 | /* Note: On device STM32L100, calibration parameters TS_CAL1 and TS_CAL2 are not available. */ |
||
| 1976 | /* Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/ |
||
| 1977 | /* Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). */ |
||
| 1978 | #if defined(TEMPSENSOR_CAL1_ADDR_CMSIS) |
||
| 1979 | /** |
||
| 1980 | * @brief Helper macro to calculate the temperature (unit: degree Celsius) |
||
| 1981 | * from ADC conversion data of internal temperature sensor. |
||
| 1982 | * @note Computation is using temperature sensor calibration values |
||
| 1983 | * stored in system memory for each device during production. |
||
| 1984 | * @note Calculation formula: |
||
| 1985 | * Temperature = ((TS_ADC_DATA - TS_CAL1) |
||
| 1986 | * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) |
||
| 1987 | * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP |
||
| 1988 | * with TS_ADC_DATA = temperature sensor raw data measured by ADC |
||
| 1989 | * Avg_Slope = (TS_CAL2 - TS_CAL1) |
||
| 1990 | * / (TS_CAL2_TEMP - TS_CAL1_TEMP) |
||
| 1991 | * TS_CAL1 = equivalent TS_ADC_DATA at temperature |
||
| 1992 | * TEMP_DEGC_CAL1 (calibrated in factory) |
||
| 1993 | * TS_CAL2 = equivalent TS_ADC_DATA at temperature |
||
| 1994 | * TEMP_DEGC_CAL2 (calibrated in factory) |
||
| 1995 | * Caution: Calculation relevancy under reserve that calibration |
||
| 1996 | * parameters are correct (address and data). |
||
| 1997 | * To calculate temperature using temperature sensor |
||
| 1998 | * datasheet typical values (generic values less, therefore |
||
| 1999 | * less accurate than calibrated values), |
||
| 2000 | * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). |
||
| 2001 | * @note As calculation input, the analog reference voltage (Vref+) must be |
||
| 2002 | * defined as it impacts the ADC LSB equivalent voltage. |
||
| 2003 | * @note Analog reference voltage (Vref+) must be either known from |
||
| 2004 | * user board environment or can be calculated using ADC measurement |
||
| 2005 | * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). |
||
| 2006 | * @note On this STM32 series, calibration data of temperature sensor |
||
| 2007 | * corresponds to a resolution of 12 bits, |
||
| 2008 | * this is the recommended ADC resolution to convert voltage of |
||
| 2009 | * temperature sensor. |
||
| 2010 | * Otherwise, this macro performs the processing to scale |
||
| 2011 | * ADC conversion data to 12 bits. |
||
| 2012 | * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) |
||
| 2013 | * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal |
||
| 2014 | * temperature sensor (unit: digital value). |
||
| 2015 | * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature |
||
| 2016 | * sensor voltage has been measured. |
||
| 2017 | * This parameter can be one of the following values: |
||
| 2018 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 2019 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 2020 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 2021 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 2022 | * @retval Temperature (unit: degree Celsius) |
||
| 2023 | */ |
||
| 2024 | #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ |
||
| 2025 | __TEMPSENSOR_ADC_DATA__,\ |
||
| 2026 | __ADC_RESOLUTION__) \ |
||
| 2027 | (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ |
||
| 2028 | (__ADC_RESOLUTION__), \ |
||
| 2029 | LL_ADC_RESOLUTION_12B) \ |
||
| 2030 | * (__VREFANALOG_VOLTAGE__)) \ |
||
| 2031 | / TEMPSENSOR_CAL_VREFANALOG) \ |
||
| 2032 | - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ |
||
| 2033 | ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ |
||
| 2034 | ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ |
||
| 2035 | ) + TEMPSENSOR_CAL1_TEMP \ |
||
| 2036 | ) |
||
| 2037 | #endif /* TEMPSENSOR_CAL1_ADDR_CMSIS */ |
||
| 2038 | |||
| 2039 | /** |
||
| 2040 | * @brief Helper macro to calculate the temperature (unit: degree Celsius) |
||
| 2041 | * from ADC conversion data of internal temperature sensor. |
||
| 2042 | * @note Computation is using temperature sensor typical values |
||
| 2043 | * (refer to device datasheet). |
||
| 2044 | * @note Calculation formula: |
||
| 2045 | * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) |
||
| 2046 | * / Avg_Slope + CALx_TEMP |
||
| 2047 | * with TS_ADC_DATA = temperature sensor raw data measured by ADC |
||
| 2048 | * (unit: digital value) |
||
| 2049 | * Avg_Slope = temperature sensor slope |
||
| 2050 | * (unit: uV/Degree Celsius) |
||
| 2051 | * TS_TYP_CALx_VOLT = temperature sensor digital value at |
||
| 2052 | * temperature CALx_TEMP (unit: mV) |
||
| 2053 | * Caution: Calculation relevancy under reserve the temperature sensor |
||
| 2054 | * of the current device has characteristics in line with |
||
| 2055 | * datasheet typical values. |
||
| 2056 | * If temperature sensor calibration values are available on |
||
| 2057 | * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), |
||
| 2058 | * temperature calculation will be more accurate using |
||
| 2059 | * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). |
||
| 2060 | * @note As calculation input, the analog reference voltage (Vref+) must be |
||
| 2061 | * defined as it impacts the ADC LSB equivalent voltage. |
||
| 2062 | * @note Analog reference voltage (Vref+) must be either known from |
||
| 2063 | * user board environment or can be calculated using ADC measurement |
||
| 2064 | * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). |
||
| 2065 | * @note ADC measurement data must correspond to a resolution of 12bits |
||
| 2066 | * (full scale digital value 4095). If not the case, the data must be |
||
| 2067 | * preliminarily rescaled to an equivalent resolution of 12 bits. |
||
| 2068 | * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). |
||
| 2069 | * On STM32L1, refer to device datasheet parameter "Avg_Slope". |
||
| 2070 | * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). |
||
| 2071 | * On STM32L1, refer to device datasheet parameter "V110" (corresponding to TS_CAL2). |
||
| 2072 | * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) |
||
| 2073 | * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) |
||
| 2074 | * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). |
||
| 2075 | * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. |
||
| 2076 | * This parameter can be one of the following values: |
||
| 2077 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 2078 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 2079 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 2080 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 2081 | * @retval Temperature (unit: degree Celsius) |
||
| 2082 | */ |
||
| 2083 | #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ |
||
| 2084 | __TEMPSENSOR_TYP_CALX_V__,\ |
||
| 2085 | __TEMPSENSOR_CALX_TEMP__,\ |
||
| 2086 | __VREFANALOG_VOLTAGE__,\ |
||
| 2087 | __TEMPSENSOR_ADC_DATA__,\ |
||
| 2088 | __ADC_RESOLUTION__) \ |
||
| 2089 | ((( ( \ |
||
| 2090 | (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ |
||
| 2091 | / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ |
||
| 2092 | * 1000) \ |
||
| 2093 | - \ |
||
| 2094 | (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ |
||
| 2095 | * 1000) \ |
||
| 2096 | ) \ |
||
| 2097 | ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ |
||
| 2098 | ) + (__TEMPSENSOR_CALX_TEMP__) \ |
||
| 2099 | ) |
||
| 2100 | |||
| 2101 | /** |
||
| 2102 | * @} |
||
| 2103 | */ |
||
| 2104 | |||
| 2105 | /** |
||
| 2106 | * @} |
||
| 2107 | */ |
||
| 2108 | |||
| 2109 | |||
| 2110 | /* Exported functions --------------------------------------------------------*/ |
||
| 2111 | /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions |
||
| 2112 | * @{ |
||
| 2113 | */ |
||
| 2114 | |||
| 2115 | /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management |
||
| 2116 | * @{ |
||
| 2117 | */ |
||
| 2118 | /* Note: LL ADC functions to set DMA transfer are located into sections of */ |
||
| 2119 | /* configuration of ADC instance, groups and multimode (if available): */ |
||
| 2120 | /* @ref LL_ADC_REG_SetDMATransfer(), ... */ |
||
| 2121 | |||
| 2122 | /** |
||
| 2123 | * @brief Function to help to configure DMA transfer from ADC: retrieve the |
||
| 2124 | * ADC register address from ADC instance and a list of ADC registers |
||
| 2125 | * intended to be used (most commonly) with DMA transfer. |
||
| 2126 | * @note These ADC registers are data registers: |
||
| 2127 | * when ADC conversion data is available in ADC data registers, |
||
| 2128 | * ADC generates a DMA transfer request. |
||
| 2129 | * @note This macro is intended to be used with LL DMA driver, refer to |
||
| 2130 | * function "LL_DMA_ConfigAddresses()". |
||
| 2131 | * Example: |
||
| 2132 | * LL_DMA_ConfigAddresses(DMA1, |
||
| 2133 | * LL_DMA_CHANNEL_1, |
||
| 2134 | * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), |
||
| 2135 | * (uint32_t)&< array or variable >, |
||
| 2136 | * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); |
||
| 2137 | * @note For devices with several ADC: in multimode, some devices |
||
| 2138 | * use a different data register outside of ADC instance scope |
||
| 2139 | * (common data register). This macro manages this register difference, |
||
| 2140 | * only ADC instance has to be set as parameter. |
||
| 2141 | * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr |
||
| 2142 | * @param ADCx ADC instance |
||
| 2143 | * @param Register This parameter can be one of the following values: |
||
| 2144 | * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA |
||
| 2145 | * @retval ADC register address |
||
| 2146 | */ |
||
| 2147 | __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) |
||
| 2148 | { |
||
| 2149 | /* Retrieve address of register DR */ |
||
| 2150 | return (uint32_t)&(ADCx->DR); |
||
| 2151 | } |
||
| 2152 | |||
| 2153 | /** |
||
| 2154 | * @} |
||
| 2155 | */ |
||
| 2156 | |||
| 2157 | /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances |
||
| 2158 | * @{ |
||
| 2159 | */ |
||
| 2160 | |||
| 2161 | /** |
||
| 2162 | * @brief Set parameter common to several ADC: Clock source and prescaler. |
||
| 2163 | * @note On this STM32 series, HSI RC oscillator is the only clock source for ADC. |
||
| 2164 | * Therefore, HSI RC oscillator must be preliminarily enabled at RCC top level. |
||
| 2165 | * @note On this STM32 series, some clock ratio constraints between ADC clock and APB clock |
||
| 2166 | * must be respected: |
||
| 2167 | * - In all cases: if APB clock frequency is too low compared ADC clock frequency, a delay between conversions must be inserted. |
||
| 2168 | * - If ADC group injected is used: ADC clock frequency should be lower than APB clock frequency /4 for resolution 12 or 10 bits, APB clock frequency /3 for resolution 8 bits, APB clock frequency /2 for resolution 6 bits. |
||
| 2169 | * Refer to reference manual. |
||
| 2170 | * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock |
||
| 2171 | * @param ADCxy_COMMON ADC common instance |
||
| 2172 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
||
| 2173 | * @param CommonClock This parameter can be one of the following values: |
||
| 2174 | * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 |
||
| 2175 | * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 |
||
| 2176 | * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 |
||
| 2177 | * @retval None |
||
| 2178 | */ |
||
| 2179 | __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) |
||
| 2180 | { |
||
| 2181 | MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock); |
||
| 2182 | } |
||
| 2183 | |||
| 2184 | /** |
||
| 2185 | * @brief Get parameter common to several ADC: Clock source and prescaler. |
||
| 2186 | * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock |
||
| 2187 | * @param ADCxy_COMMON ADC common instance |
||
| 2188 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
||
| 2189 | * @retval Returned value can be one of the following values: |
||
| 2190 | * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 |
||
| 2191 | * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 |
||
| 2192 | * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 |
||
| 2193 | */ |
||
| 2194 | __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) |
||
| 2195 | { |
||
| 2196 | return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE)); |
||
| 2197 | } |
||
| 2198 | |||
| 2199 | /** |
||
| 2200 | * @brief Set parameter common to several ADC: measurement path to internal |
||
| 2201 | * channels (VrefInt, temperature sensor, ...). |
||
| 2202 | * @note One or several values can be selected. |
||
| 2203 | * Example: (LL_ADC_PATH_INTERNAL_VREFINT | |
||
| 2204 | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) |
||
| 2205 | * @note Stabilization time of measurement path to internal channel: |
||
| 2206 | * After enabling internal paths, before starting ADC conversion, |
||
| 2207 | * a delay is required for internal voltage reference and |
||
| 2208 | * temperature sensor stabilization time. |
||
| 2209 | * Refer to device datasheet. |
||
| 2210 | * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. |
||
| 2211 | * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. |
||
| 2212 | * @note ADC internal channel sampling time constraint: |
||
| 2213 | * For ADC conversion of internal channels, |
||
| 2214 | * a sampling time minimum value is required. |
||
| 2215 | * Refer to device datasheet. |
||
| 2216 | * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh |
||
| 2217 | * @param ADCxy_COMMON ADC common instance |
||
| 2218 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
||
| 2219 | * @param PathInternal This parameter can be a combination of the following values: |
||
| 2220 | * @arg @ref LL_ADC_PATH_INTERNAL_NONE |
||
| 2221 | * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT |
||
| 2222 | * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR |
||
| 2223 | * @retval None |
||
| 2224 | */ |
||
| 2225 | __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) |
||
| 2226 | { |
||
| 2227 | MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE, PathInternal); |
||
| 2228 | } |
||
| 2229 | |||
| 2230 | /** |
||
| 2231 | * @brief Get parameter common to several ADC: measurement path to internal |
||
| 2232 | * channels (VrefInt, temperature sensor, ...). |
||
| 2233 | * @note One or several values can be selected. |
||
| 2234 | * Example: (LL_ADC_PATH_INTERNAL_VREFINT | |
||
| 2235 | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) |
||
| 2236 | * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh |
||
| 2237 | * @param ADCxy_COMMON ADC common instance |
||
| 2238 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
||
| 2239 | * @retval Returned value can be a combination of the following values: |
||
| 2240 | * @arg @ref LL_ADC_PATH_INTERNAL_NONE |
||
| 2241 | * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT |
||
| 2242 | * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR |
||
| 2243 | */ |
||
| 2244 | __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) |
||
| 2245 | { |
||
| 2246 | return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE)); |
||
| 2247 | } |
||
| 2248 | |||
| 2249 | /** |
||
| 2250 | * @} |
||
| 2251 | */ |
||
| 2252 | |||
| 2253 | /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance |
||
| 2254 | * @{ |
||
| 2255 | */ |
||
| 2256 | |||
| 2257 | /** |
||
| 2258 | * @brief Set ADC resolution. |
||
| 2259 | * Refer to reference manual for alignments formats |
||
| 2260 | * dependencies to ADC resolutions. |
||
| 2261 | * @rmtoll CR1 RES LL_ADC_SetResolution |
||
| 2262 | * @param ADCx ADC instance |
||
| 2263 | * @param Resolution This parameter can be one of the following values: |
||
| 2264 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 2265 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 2266 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 2267 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 2268 | * @retval None |
||
| 2269 | */ |
||
| 2270 | __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) |
||
| 2271 | { |
||
| 2272 | MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution); |
||
| 2273 | } |
||
| 2274 | |||
| 2275 | /** |
||
| 2276 | * @brief Get ADC resolution. |
||
| 2277 | * Refer to reference manual for alignments formats |
||
| 2278 | * dependencies to ADC resolutions. |
||
| 2279 | * @rmtoll CR1 RES LL_ADC_GetResolution |
||
| 2280 | * @param ADCx ADC instance |
||
| 2281 | * @retval Returned value can be one of the following values: |
||
| 2282 | * @arg @ref LL_ADC_RESOLUTION_12B |
||
| 2283 | * @arg @ref LL_ADC_RESOLUTION_10B |
||
| 2284 | * @arg @ref LL_ADC_RESOLUTION_8B |
||
| 2285 | * @arg @ref LL_ADC_RESOLUTION_6B |
||
| 2286 | */ |
||
| 2287 | __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) |
||
| 2288 | { |
||
| 2289 | return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES)); |
||
| 2290 | } |
||
| 2291 | |||
| 2292 | /** |
||
| 2293 | * @brief Set ADC conversion data alignment. |
||
| 2294 | * @note Refer to reference manual for alignments formats |
||
| 2295 | * dependencies to ADC resolutions. |
||
| 2296 | * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment |
||
| 2297 | * @param ADCx ADC instance |
||
| 2298 | * @param DataAlignment This parameter can be one of the following values: |
||
| 2299 | * @arg @ref LL_ADC_DATA_ALIGN_RIGHT |
||
| 2300 | * @arg @ref LL_ADC_DATA_ALIGN_LEFT |
||
| 2301 | * @retval None |
||
| 2302 | */ |
||
| 2303 | __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) |
||
| 2304 | { |
||
| 2305 | MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); |
||
| 2306 | } |
||
| 2307 | |||
| 2308 | /** |
||
| 2309 | * @brief Get ADC conversion data alignment. |
||
| 2310 | * @note Refer to reference manual for alignments formats |
||
| 2311 | * dependencies to ADC resolutions. |
||
| 2312 | * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment |
||
| 2313 | * @param ADCx ADC instance |
||
| 2314 | * @retval Returned value can be one of the following values: |
||
| 2315 | * @arg @ref LL_ADC_DATA_ALIGN_RIGHT |
||
| 2316 | * @arg @ref LL_ADC_DATA_ALIGN_LEFT |
||
| 2317 | */ |
||
| 2318 | __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) |
||
| 2319 | { |
||
| 2320 | return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); |
||
| 2321 | } |
||
| 2322 | |||
| 2323 | /** |
||
| 2324 | * @brief Set ADC low power mode auto wait. |
||
| 2325 | * @note Description of ADC low power modes: |
||
| 2326 | * - ADC low power mode "auto wait": Dynamic low power mode, |
||
| 2327 | * ADC conversions occurrences are limited to the minimum necessary |
||
| 2328 | * in order to reduce power consumption. |
||
| 2329 | * New ADC conversion starts only when the previous |
||
| 2330 | * unitary conversion data (for ADC group regular) |
||
| 2331 | * or previous sequence conversions data (for ADC group injected) |
||
| 2332 | * has been retrieved by user software. |
||
| 2333 | * In the meantime, ADC remains idle: does not performs any |
||
| 2334 | * other conversion. |
||
| 2335 | * This mode allows to automatically adapt the ADC conversions |
||
| 2336 | * triggers to the speed of the software that reads the data. |
||
| 2337 | * Moreover, this avoids risk of overrun for low frequency |
||
| 2338 | * applications. |
||
| 2339 | * How to use this low power mode: |
||
| 2340 | * - Do not use with interruption or DMA since these modes |
||
| 2341 | * have to clear immediately the EOC flag to free the |
||
| 2342 | * IRQ vector sequencer. |
||
| 2343 | * - Do use with polling: 1. Start conversion, |
||
| 2344 | * 2. Later on, when conversion data is needed: poll for end of |
||
| 2345 | * conversion to ensure that conversion is completed and |
||
| 2346 | * retrieve ADC conversion data. This will trig another |
||
| 2347 | * ADC conversion start. |
||
| 2348 | * - ADC low power mode "auto power-off": |
||
| 2349 | * refer to function @ref LL_ADC_SetLowPowerModeAutoPowerOff(). |
||
| 2350 | * @note With ADC low power mode "auto wait", the ADC conversion data read |
||
| 2351 | * is corresponding to previous ADC conversion start, independently |
||
| 2352 | * of delay during which ADC was idle. |
||
| 2353 | * Therefore, the ADC conversion data may be outdated: does not |
||
| 2354 | * correspond to the current voltage level on the selected |
||
| 2355 | * ADC channel. |
||
| 2356 | * @rmtoll CR2 DELS LL_ADC_SetLowPowerModeAutoWait |
||
| 2357 | * @param ADCx ADC instance |
||
| 2358 | * @param LowPowerModeAutoWait This parameter can be one of the following values: |
||
| 2359 | * @arg @ref LL_ADC_LP_AUTOWAIT_NONE |
||
| 2360 | * @arg @ref LL_ADC_LP_AUTOWAIT |
||
| 2361 | * @arg @ref LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES |
||
| 2362 | * @arg @ref LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES |
||
| 2363 | * @arg @ref LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES |
||
| 2364 | * @arg @ref LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES |
||
| 2365 | * @arg @ref LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES |
||
| 2366 | * @arg @ref LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES |
||
| 2367 | * @retval None |
||
| 2368 | */ |
||
| 2369 | __STATIC_INLINE void LL_ADC_SetLowPowerModeAutoWait(ADC_TypeDef *ADCx, uint32_t LowPowerModeAutoWait) |
||
| 2370 | { |
||
| 2371 | MODIFY_REG(ADCx->CR2, ADC_CR2_DELS, LowPowerModeAutoWait); |
||
| 2372 | } |
||
| 2373 | |||
| 2374 | /** |
||
| 2375 | * @brief Get ADC low power mode auto wait. |
||
| 2376 | * @note Description of ADC low power modes: |
||
| 2377 | * - ADC low power mode "auto wait": Dynamic low power mode, |
||
| 2378 | * ADC conversions occurrences are limited to the minimum necessary |
||
| 2379 | * in order to reduce power consumption. |
||
| 2380 | * New ADC conversion starts only when the previous |
||
| 2381 | * unitary conversion data (for ADC group regular) |
||
| 2382 | * or previous sequence conversions data (for ADC group injected) |
||
| 2383 | * has been retrieved by user software. |
||
| 2384 | * In the meantime, ADC remains idle: does not performs any |
||
| 2385 | * other conversion. |
||
| 2386 | * This mode allows to automatically adapt the ADC conversions |
||
| 2387 | * triggers to the speed of the software that reads the data. |
||
| 2388 | * Moreover, this avoids risk of overrun for low frequency |
||
| 2389 | * applications. |
||
| 2390 | * How to use this low power mode: |
||
| 2391 | * - Do not use with interruption or DMA since these modes |
||
| 2392 | * have to clear immediately the EOC flag to free the |
||
| 2393 | * IRQ vector sequencer. |
||
| 2394 | * - Do use with polling: 1. Start conversion, |
||
| 2395 | * 2. Later on, when conversion data is needed: poll for end of |
||
| 2396 | * conversion to ensure that conversion is completed and |
||
| 2397 | * retrieve ADC conversion data. This will trig another |
||
| 2398 | * ADC conversion start. |
||
| 2399 | * - ADC low power mode "auto power-off": |
||
| 2400 | * refer to function @ref LL_ADC_SetLowPowerModeAutoPowerOff(). |
||
| 2401 | * @note With ADC low power mode "auto wait", the ADC conversion data read |
||
| 2402 | * is corresponding to previous ADC conversion start, independently |
||
| 2403 | * of delay during which ADC was idle. |
||
| 2404 | * Therefore, the ADC conversion data may be outdated: does not |
||
| 2405 | * correspond to the current voltage level on the selected |
||
| 2406 | * ADC channel. |
||
| 2407 | * @rmtoll CR2 DELS LL_ADC_GetLowPowerModeAutoWait |
||
| 2408 | * @param ADCx ADC instance |
||
| 2409 | * @retval Returned value can be one of the following values: |
||
| 2410 | * @arg @ref LL_ADC_LP_AUTOWAIT_NONE |
||
| 2411 | * @arg @ref LL_ADC_LP_AUTOWAIT |
||
| 2412 | * @arg @ref LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES |
||
| 2413 | * @arg @ref LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES |
||
| 2414 | * @arg @ref LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES |
||
| 2415 | * @arg @ref LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES |
||
| 2416 | * @arg @ref LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES |
||
| 2417 | * @arg @ref LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES |
||
| 2418 | */ |
||
| 2419 | __STATIC_INLINE uint32_t LL_ADC_GetLowPowerModeAutoWait(ADC_TypeDef *ADCx) |
||
| 2420 | { |
||
| 2421 | return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DELS)); |
||
| 2422 | } |
||
| 2423 | |||
| 2424 | /** |
||
| 2425 | * @brief Set ADC low power mode auto power-off. |
||
| 2426 | * @note Description of ADC low power modes: |
||
| 2427 | * - ADC low power mode "auto wait": |
||
| 2428 | * refer to function @ref LL_ADC_SetLowPowerModeAutoWait(). |
||
| 2429 | * - ADC low power mode "auto power-off": |
||
| 2430 | * the ADC automatically powers-off after a conversion and |
||
| 2431 | * automatically wakes up when a new conversion is triggered |
||
| 2432 | * (with startup time between trigger and start of sampling). |
||
| 2433 | * This feature can be combined with low power mode "auto wait". |
||
| 2434 | * @rmtoll CR1 PDI LL_ADC_GetLowPowerModeAutoPowerOff\n |
||
| 2435 | * CR1 PDD LL_ADC_GetLowPowerModeAutoPowerOff |
||
| 2436 | * @param ADCx ADC instance |
||
| 2437 | * @param LowPowerModeAutoPowerOff This parameter can be one of the following values: |
||
| 2438 | * @arg @ref LL_ADC_LP_AUTOPOWEROFF_NONE |
||
| 2439 | * @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE |
||
| 2440 | * @arg @ref LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE |
||
| 2441 | * @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES |
||
| 2442 | * @retval None |
||
| 2443 | */ |
||
| 2444 | __STATIC_INLINE void LL_ADC_SetLowPowerModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerModeAutoPowerOff) |
||
| 2445 | { |
||
| 2446 | MODIFY_REG(ADCx->CR1, (ADC_CR1_PDI | ADC_CR1_PDD), LowPowerModeAutoPowerOff); |
||
| 2447 | } |
||
| 2448 | |||
| 2449 | /** |
||
| 2450 | * @brief Get ADC low power mode auto power-off. |
||
| 2451 | * @note Description of ADC low power modes: |
||
| 2452 | * - ADC low power mode "auto wait": |
||
| 2453 | * refer to function @ref LL_ADC_SetLowPowerModeAutoWait(). |
||
| 2454 | * - ADC low power mode "auto power-off": |
||
| 2455 | * the ADC automatically powers-off after a conversion and |
||
| 2456 | * automatically wakes up when a new conversion is triggered |
||
| 2457 | * (with startup time between trigger and start of sampling). |
||
| 2458 | * This feature can be combined with low power mode "auto wait". |
||
| 2459 | * @rmtoll CR1 PDI LL_ADC_GetLowPowerModeAutoPowerOff\n |
||
| 2460 | * CR1 PDD LL_ADC_GetLowPowerModeAutoPowerOff |
||
| 2461 | * @param ADCx ADC instance |
||
| 2462 | * @retval Returned value can be one of the following values: |
||
| 2463 | * @arg @ref LL_ADC_LP_AUTOPOWEROFF_NONE |
||
| 2464 | * @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE |
||
| 2465 | * @arg @ref LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE |
||
| 2466 | * @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES |
||
| 2467 | */ |
||
| 2468 | __STATIC_INLINE uint32_t LL_ADC_GetLowPowerModeAutoPowerOff(ADC_TypeDef *ADCx) |
||
| 2469 | { |
||
| 2470 | return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_PDI | ADC_CR1_PDD))); |
||
| 2471 | } |
||
| 2472 | |||
| 2473 | /** |
||
| 2474 | * @brief Set ADC sequencers scan mode, for all ADC groups |
||
| 2475 | * (group regular, group injected). |
||
| 2476 | * @note According to sequencers scan mode : |
||
| 2477 | * - If disabled: ADC conversion is performed in unitary conversion |
||
| 2478 | * mode (one channel converted, that defined in rank 1). |
||
| 2479 | * Configuration of sequencers of all ADC groups |
||
| 2480 | * (sequencer scan length, ...) is discarded: equivalent to |
||
| 2481 | * scan length of 1 rank. |
||
| 2482 | * - If enabled: ADC conversions are performed in sequence conversions |
||
| 2483 | * mode, according to configuration of sequencers of |
||
| 2484 | * each ADC group (sequencer scan length, ...). |
||
| 2485 | * Refer to function @ref LL_ADC_REG_SetSequencerLength() |
||
| 2486 | * and to function @ref LL_ADC_INJ_SetSequencerLength(). |
||
| 2487 | * @note On this STM32 series, setting of this feature is conditioned to |
||
| 2488 | * ADC state: |
||
| 2489 | * ADC must be disabled or enabled without conversion on going |
||
| 2490 | * on either groups regular or injected. |
||
| 2491 | * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode |
||
| 2492 | * @param ADCx ADC instance |
||
| 2493 | * @param ScanMode This parameter can be one of the following values: |
||
| 2494 | * @arg @ref LL_ADC_SEQ_SCAN_DISABLE |
||
| 2495 | * @arg @ref LL_ADC_SEQ_SCAN_ENABLE |
||
| 2496 | * @retval None |
||
| 2497 | */ |
||
| 2498 | __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) |
||
| 2499 | { |
||
| 2500 | MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); |
||
| 2501 | } |
||
| 2502 | |||
| 2503 | /** |
||
| 2504 | * @brief Get ADC sequencers scan mode, for all ADC groups |
||
| 2505 | * (group regular, group injected). |
||
| 2506 | * @note According to sequencers scan mode : |
||
| 2507 | * - If disabled: ADC conversion is performed in unitary conversion |
||
| 2508 | * mode (one channel converted, that defined in rank 1). |
||
| 2509 | * Configuration of sequencers of all ADC groups |
||
| 2510 | * (sequencer scan length, ...) is discarded: equivalent to |
||
| 2511 | * scan length of 1 rank. |
||
| 2512 | * - If enabled: ADC conversions are performed in sequence conversions |
||
| 2513 | * mode, according to configuration of sequencers of |
||
| 2514 | * each ADC group (sequencer scan length, ...). |
||
| 2515 | * Refer to function @ref LL_ADC_REG_SetSequencerLength() |
||
| 2516 | * and to function @ref LL_ADC_INJ_SetSequencerLength(). |
||
| 2517 | * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode |
||
| 2518 | * @param ADCx ADC instance |
||
| 2519 | * @retval Returned value can be one of the following values: |
||
| 2520 | * @arg @ref LL_ADC_SEQ_SCAN_DISABLE |
||
| 2521 | * @arg @ref LL_ADC_SEQ_SCAN_ENABLE |
||
| 2522 | */ |
||
| 2523 | __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) |
||
| 2524 | { |
||
| 2525 | return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); |
||
| 2526 | } |
||
| 2527 | |||
| 2528 | #if defined(ADC_CR2_CFG) |
||
| 2529 | /** |
||
| 2530 | * @brief Set ADC channels bank. |
||
| 2531 | * @note Bank selected applies to ADC scope, on all channels |
||
| 2532 | * (independently of channel mapped on ADC group regular |
||
| 2533 | * or group injected). |
||
| 2534 | * @note Banks availability depends on devices categories. |
||
| 2535 | * @note On this STM32 series, setting of this feature is conditioned to |
||
| 2536 | * ADC state: |
||
| 2537 | * ADC must be disabled or enabled without conversion on going |
||
| 2538 | * on either groups regular or injected. |
||
| 2539 | * @rmtoll CR2 ADC_CFG LL_ADC_SetChannelsBank |
||
| 2540 | * @param ADCx ADC instance |
||
| 2541 | * @param ChannelsBank This parameter can be one of the following values: |
||
| 2542 | * @arg @ref LL_ADC_CHANNELS_BANK_A |
||
| 2543 | * @arg @ref LL_ADC_CHANNELS_BANK_B |
||
| 2544 | * @retval None |
||
| 2545 | */ |
||
| 2546 | __STATIC_INLINE void LL_ADC_SetChannelsBank(ADC_TypeDef *ADCx, uint32_t ChannelsBank) |
||
| 2547 | { |
||
| 2548 | MODIFY_REG(ADCx->CR2, ADC_CR2_CFG, ChannelsBank); |
||
| 2549 | } |
||
| 2550 | |||
| 2551 | /** |
||
| 2552 | * @brief Get ADC channels bank. |
||
| 2553 | * @note Bank selected applies to ADC scope, on all channels |
||
| 2554 | * (independently of channel mapped on ADC group regular |
||
| 2555 | * or group injected). |
||
| 2556 | * @note Banks availability depends on devices categories. |
||
| 2557 | * @rmtoll CR2 ADC_CFG LL_ADC_GetChannelsBank |
||
| 2558 | * @param ADCx ADC instance |
||
| 2559 | * @retval Returned value can be one of the following values: |
||
| 2560 | * @arg @ref LL_ADC_CHANNELS_BANK_A |
||
| 2561 | * @arg @ref LL_ADC_CHANNELS_BANK_B |
||
| 2562 | */ |
||
| 2563 | __STATIC_INLINE uint32_t LL_ADC_GetChannelsBank(ADC_TypeDef *ADCx) |
||
| 2564 | { |
||
| 2565 | return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CFG)); |
||
| 2566 | } |
||
| 2567 | #endif |
||
| 2568 | |||
| 2569 | /** |
||
| 2570 | * @} |
||
| 2571 | */ |
||
| 2572 | |||
| 2573 | /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular |
||
| 2574 | * @{ |
||
| 2575 | */ |
||
| 2576 | |||
| 2577 | /** |
||
| 2578 | * @brief Set ADC group regular conversion trigger source: |
||
| 2579 | * internal (SW start) or from external IP (timer event, |
||
| 2580 | * external interrupt line). |
||
| 2581 | * @note On this STM32 series, setting of external trigger edge is performed |
||
| 2582 | * using function @ref LL_ADC_REG_StartConversionExtTrig(). |
||
| 2583 | * @note Availability of parameters of trigger sources from timer |
||
| 2584 | * depends on timers availability on the selected device. |
||
| 2585 | * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n |
||
| 2586 | * CR2 EXTEN LL_ADC_REG_SetTriggerSource |
||
| 2587 | * @param ADCx ADC instance |
||
| 2588 | * @param TriggerSource This parameter can be one of the following values: |
||
| 2589 | * @arg @ref LL_ADC_REG_TRIG_SOFTWARE |
||
| 2590 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO |
||
| 2591 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 |
||
| 2592 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO |
||
| 2593 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 |
||
| 2594 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 |
||
| 2595 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH3 |
||
| 2596 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO |
||
| 2597 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 |
||
| 2598 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO |
||
| 2599 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH2 |
||
| 2600 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO |
||
| 2601 | * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 |
||
| 2602 | * @retval None |
||
| 2603 | */ |
||
| 2604 | __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) |
||
| 2605 | { |
||
| 2606 | /* Note: On this STM32 series, ADC group regular external trigger edge */ |
||
| 2607 | /* is used to perform a ADC conversion start. */ |
||
| 2608 | /* This function does not set external trigger edge. */ |
||
| 2609 | /* This feature is set using function */ |
||
| 2610 | /* @ref LL_ADC_REG_StartConversionExtTrig(). */ |
||
| 2611 | MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); |
||
| 2612 | } |
||
| 2613 | |||
| 2614 | /** |
||
| 2615 | * @brief Get ADC group regular conversion trigger source: |
||
| 2616 | * internal (SW start) or from external IP (timer event, |
||
| 2617 | * external interrupt line). |
||
| 2618 | * @note To determine whether group regular trigger source is |
||
| 2619 | * internal (SW start) or external, without detail |
||
| 2620 | * of which peripheral is selected as external trigger, |
||
| 2621 | * (equivalent to |
||
| 2622 | * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") |
||
| 2623 | * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. |
||
| 2624 | * @note Availability of parameters of trigger sources from timer |
||
| 2625 | * depends on timers availability on the selected device. |
||
| 2626 | * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n |
||
| 2627 | * CR2 EXTEN LL_ADC_REG_GetTriggerSource |
||
| 2628 | * @param ADCx ADC instance |
||
| 2629 | * @retval Returned value can be one of the following values: |
||
| 2630 | * @arg @ref LL_ADC_REG_TRIG_SOFTWARE |
||
| 2631 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO |
||
| 2632 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 |
||
| 2633 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO |
||
| 2634 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 |
||
| 2635 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 |
||
| 2636 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH3 |
||
| 2637 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO |
||
| 2638 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 |
||
| 2639 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO |
||
| 2640 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH2 |
||
| 2641 | * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO |
||
| 2642 | * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 |
||
| 2643 | */ |
||
| 2644 | __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) |
||
| 2645 | { |
||
| 2646 | uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); |
||
| 2647 | |||
| 2648 | /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ |
||
| 2649 | /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */ |
||
| 2650 | uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); |
||
| 2651 | |||
| 2652 | /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */ |
||
| 2653 | /* to match with triggers literals definition. */ |
||
| 2654 | return ((TriggerSource |
||
| 2655 | & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL) |
||
| 2656 | | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN) |
||
| 2657 | ); |
||
| 2658 | } |
||
| 2659 | |||
| 2660 | /** |
||
| 2661 | * @brief Get ADC group regular conversion trigger source internal (SW start) |
||
| 2662 | or external. |
||
| 2663 | * @note In case of group regular trigger source set to external trigger, |
||
| 2664 | * to determine which peripheral is selected as external trigger, |
||
| 2665 | * use function @ref LL_ADC_REG_GetTriggerSource(). |
||
| 2666 | * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart |
||
| 2667 | * @param ADCx ADC instance |
||
| 2668 | * @retval Value "0" if trigger source external trigger |
||
| 2669 | * Value "1" if trigger source SW start. |
||
| 2670 | */ |
||
| 2671 | __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) |
||
| 2672 | { |
||
| 2673 | return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN)); |
||
| 2674 | } |
||
| 2675 | |||
| 2676 | /** |
||
| 2677 | * @brief Get ADC group regular conversion trigger polarity. |
||
| 2678 | * @note Applicable only for trigger source set to external trigger. |
||
| 2679 | * @note On this STM32 series, setting of external trigger edge is performed |
||
| 2680 | * using function @ref LL_ADC_REG_StartConversionExtTrig(). |
||
| 2681 | * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge |
||
| 2682 | * @param ADCx ADC instance |
||
| 2683 | * @retval Returned value can be one of the following values: |
||
| 2684 | * @arg @ref LL_ADC_REG_TRIG_EXT_RISING |
||
| 2685 | * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING |
||
| 2686 | * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING |
||
| 2687 | */ |
||
| 2688 | __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) |
||
| 2689 | { |
||
| 2690 | return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN)); |
||
| 2691 | } |
||
| 2692 | |||
| 2693 | |||
| 2694 | /** |
||
| 2695 | * @brief Set ADC group regular sequencer length and scan direction. |
||
| 2696 | * @note Description of ADC group regular sequencer features: |
||
| 2697 | * - For devices with sequencer fully configurable |
||
| 2698 | * (function "LL_ADC_REG_SetSequencerRanks()" available): |
||
| 2699 | * sequencer length and each rank affectation to a channel |
||
| 2700 | * are configurable. |
||
| 2701 | * This function performs configuration of: |
||
| 2702 | * - Sequence length: Number of ranks in the scan sequence. |
||
| 2703 | * - Sequence direction: Unless specified in parameters, sequencer |
||
| 2704 | * scan direction is forward (from rank 1 to rank n). |
||
| 2705 | * Sequencer ranks are selected using |
||
| 2706 | * function "LL_ADC_REG_SetSequencerRanks()". |
||
| 2707 | * - For devices with sequencer not fully configurable |
||
| 2708 | * (function "LL_ADC_REG_SetSequencerChannels()" available): |
||
| 2709 | * sequencer length and each rank affectation to a channel |
||
| 2710 | * are defined by channel number. |
||
| 2711 | * This function performs configuration of: |
||
| 2712 | * - Sequence length: Number of ranks in the scan sequence is |
||
| 2713 | * defined by number of channels set in the sequence, |
||
| 2714 | * rank of each channel is fixed by channel HW number. |
||
| 2715 | * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). |
||
| 2716 | * - Sequence direction: Unless specified in parameters, sequencer |
||
| 2717 | * scan direction is forward (from lowest channel number to |
||
| 2718 | * highest channel number). |
||
| 2719 | * Sequencer ranks are selected using |
||
| 2720 | * function "LL_ADC_REG_SetSequencerChannels()". |
||
| 2721 | * @note On this STM32 series, group regular sequencer configuration |
||
| 2722 | * is conditioned to ADC instance sequencer mode. |
||
| 2723 | * If ADC instance sequencer mode is disabled, sequencers of |
||
| 2724 | * all groups (group regular, group injected) can be configured |
||
| 2725 | * but their execution is disabled (limited to rank 1). |
||
| 2726 | * Refer to function @ref LL_ADC_SetSequencersScanMode(). |
||
| 2727 | * @note Sequencer disabled is equivalent to sequencer of 1 rank: |
||
| 2728 | * ADC conversion on only 1 channel. |
||
| 2729 | * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength |
||
| 2730 | * @param ADCx ADC instance |
||
| 2731 | * @param SequencerNbRanks This parameter can be one of the following values: |
||
| 2732 | * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE |
||
| 2733 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS |
||
| 2734 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS |
||
| 2735 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS |
||
| 2736 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS |
||
| 2737 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS |
||
| 2738 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS |
||
| 2739 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS |
||
| 2740 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS |
||
| 2741 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS |
||
| 2742 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS |
||
| 2743 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS |
||
| 2744 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS |
||
| 2745 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS |
||
| 2746 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS |
||
| 2747 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS |
||
| 2748 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS |
||
| 2749 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_18ANKS |
||
| 2750 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_19RANKS |
||
| 2751 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_20RANKS |
||
| 2752 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_21RANKS |
||
| 2753 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_22RANKS |
||
| 2754 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_23RANKS |
||
| 2755 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_24RANKS |
||
| 2756 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_25RANKS |
||
| 2757 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_26RANKS |
||
| 2758 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_27RANKS |
||
| 2759 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_28RANKS (1) |
||
| 2760 | * |
||
| 2761 | * (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5. |
||
| 2762 | * @retval None |
||
| 2763 | */ |
||
| 2764 | __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) |
||
| 2765 | { |
||
| 2766 | MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); |
||
| 2767 | } |
||
| 2768 | |||
| 2769 | /** |
||
| 2770 | * @brief Get ADC group regular sequencer length and scan direction. |
||
| 2771 | * @note Description of ADC group regular sequencer features: |
||
| 2772 | * - For devices with sequencer fully configurable |
||
| 2773 | * (function "LL_ADC_REG_SetSequencerRanks()" available): |
||
| 2774 | * sequencer length and each rank affectation to a channel |
||
| 2775 | * are configurable. |
||
| 2776 | * This function retrieves: |
||
| 2777 | * - Sequence length: Number of ranks in the scan sequence. |
||
| 2778 | * - Sequence direction: Unless specified in parameters, sequencer |
||
| 2779 | * scan direction is forward (from rank 1 to rank n). |
||
| 2780 | * Sequencer ranks are selected using |
||
| 2781 | * function "LL_ADC_REG_SetSequencerRanks()". |
||
| 2782 | * - For devices with sequencer not fully configurable |
||
| 2783 | * (function "LL_ADC_REG_SetSequencerChannels()" available): |
||
| 2784 | * sequencer length and each rank affectation to a channel |
||
| 2785 | * are defined by channel number. |
||
| 2786 | * This function retrieves: |
||
| 2787 | * - Sequence length: Number of ranks in the scan sequence is |
||
| 2788 | * defined by number of channels set in the sequence, |
||
| 2789 | * rank of each channel is fixed by channel HW number. |
||
| 2790 | * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). |
||
| 2791 | * - Sequence direction: Unless specified in parameters, sequencer |
||
| 2792 | * scan direction is forward (from lowest channel number to |
||
| 2793 | * highest channel number). |
||
| 2794 | * Sequencer ranks are selected using |
||
| 2795 | * function "LL_ADC_REG_SetSequencerChannels()". |
||
| 2796 | * @note On this STM32 series, group regular sequencer configuration |
||
| 2797 | * is conditioned to ADC instance sequencer mode. |
||
| 2798 | * If ADC instance sequencer mode is disabled, sequencers of |
||
| 2799 | * all groups (group regular, group injected) can be configured |
||
| 2800 | * but their execution is disabled (limited to rank 1). |
||
| 2801 | * Refer to function @ref LL_ADC_SetSequencersScanMode(). |
||
| 2802 | * @note Sequencer disabled is equivalent to sequencer of 1 rank: |
||
| 2803 | * ADC conversion on only 1 channel. |
||
| 2804 | * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength |
||
| 2805 | * @param ADCx ADC instance |
||
| 2806 | * @retval Returned value can be one of the following values: |
||
| 2807 | * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE |
||
| 2808 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS |
||
| 2809 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS |
||
| 2810 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS |
||
| 2811 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS |
||
| 2812 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS |
||
| 2813 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS |
||
| 2814 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS |
||
| 2815 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS |
||
| 2816 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS |
||
| 2817 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS |
||
| 2818 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS |
||
| 2819 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS |
||
| 2820 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS |
||
| 2821 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS |
||
| 2822 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS |
||
| 2823 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS |
||
| 2824 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_18ANKS |
||
| 2825 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_19RANKS |
||
| 2826 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_20RANKS |
||
| 2827 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_21RANKS |
||
| 2828 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_22RANKS |
||
| 2829 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_23RANKS |
||
| 2830 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_24RANKS |
||
| 2831 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_25RANKS |
||
| 2832 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_26RANKS |
||
| 2833 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_27RANKS |
||
| 2834 | * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_28RANKS (1) |
||
| 2835 | * |
||
| 2836 | * (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5. |
||
| 2837 | */ |
||
| 2838 | __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) |
||
| 2839 | { |
||
| 2840 | return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); |
||
| 2841 | } |
||
| 2842 | |||
| 2843 | /** |
||
| 2844 | * @brief Set ADC group regular sequencer discontinuous mode: |
||
| 2845 | * sequence subdivided and scan conversions interrupted every selected |
||
| 2846 | * number of ranks. |
||
| 2847 | * @note It is not possible to enable both ADC group regular |
||
| 2848 | * continuous mode and sequencer discontinuous mode. |
||
| 2849 | * @note It is not possible to enable both ADC auto-injected mode |
||
| 2850 | * and ADC group regular sequencer discontinuous mode. |
||
| 2851 | * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n |
||
| 2852 | * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont |
||
| 2853 | * @param ADCx ADC instance |
||
| 2854 | * @param SeqDiscont This parameter can be one of the following values: |
||
| 2855 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE |
||
| 2856 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK |
||
| 2857 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS |
||
| 2858 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS |
||
| 2859 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS |
||
| 2860 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS |
||
| 2861 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS |
||
| 2862 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS |
||
| 2863 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS |
||
| 2864 | * @retval None |
||
| 2865 | */ |
||
| 2866 | __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) |
||
| 2867 | { |
||
| 2868 | MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); |
||
| 2869 | } |
||
| 2870 | |||
| 2871 | /** |
||
| 2872 | * @brief Get ADC group regular sequencer discontinuous mode: |
||
| 2873 | * sequence subdivided and scan conversions interrupted every selected |
||
| 2874 | * number of ranks. |
||
| 2875 | * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n |
||
| 2876 | * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont |
||
| 2877 | * @param ADCx ADC instance |
||
| 2878 | * @retval Returned value can be one of the following values: |
||
| 2879 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE |
||
| 2880 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK |
||
| 2881 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS |
||
| 2882 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS |
||
| 2883 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS |
||
| 2884 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS |
||
| 2885 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS |
||
| 2886 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS |
||
| 2887 | * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS |
||
| 2888 | */ |
||
| 2889 | __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) |
||
| 2890 | { |
||
| 2891 | return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); |
||
| 2892 | } |
||
| 2893 | |||
| 2894 | /** |
||
| 2895 | * @brief Set ADC group regular sequence: channel on the selected |
||
| 2896 | * scan sequence rank. |
||
| 2897 | * @note This function performs configuration of: |
||
| 2898 | * - Channels ordering into each rank of scan sequence: |
||
| 2899 | * whatever channel can be placed into whatever rank. |
||
| 2900 | * @note On this STM32 series, ADC group regular sequencer is |
||
| 2901 | * fully configurable: sequencer length and each rank |
||
| 2902 | * affectation to a channel are configurable. |
||
| 2903 | * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). |
||
| 2904 | * @note Depending on devices and packages, some channels may not be available. |
||
| 2905 | * Refer to device datasheet for channels availability. |
||
| 2906 | * @note On this STM32 series, to measure internal channels (VrefInt, |
||
| 2907 | * TempSensor, ...), measurement paths to internal channels must be |
||
| 2908 | * enabled separately. |
||
| 2909 | * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). |
||
| 2910 | * @rmtoll SQR5 SQ1 LL_ADC_REG_SetSequencerRanks\n |
||
| 2911 | * SQR5 SQ2 LL_ADC_REG_SetSequencerRanks\n |
||
| 2912 | * SQR5 SQ3 LL_ADC_REG_SetSequencerRanks\n |
||
| 2913 | * SQR5 SQ4 LL_ADC_REG_SetSequencerRanks\n |
||
| 2914 | * SQR5 SQ5 LL_ADC_REG_SetSequencerRanks\n |
||
| 2915 | * SQR5 SQ6 LL_ADC_REG_SetSequencerRanks\n |
||
| 2916 | * SQR4 SQ7 LL_ADC_REG_SetSequencerRanks\n |
||
| 2917 | * SQR4 SQ8 LL_ADC_REG_SetSequencerRanks\n |
||
| 2918 | * SQR4 SQ9 LL_ADC_REG_SetSequencerRanks\n |
||
| 2919 | * SQR4 SQ10 LL_ADC_REG_SetSequencerRanks\n |
||
| 2920 | * SQR4 SQ11 LL_ADC_REG_SetSequencerRanks\n |
||
| 2921 | * SQR4 SQ12 LL_ADC_REG_SetSequencerRanks\n |
||
| 2922 | * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n |
||
| 2923 | * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n |
||
| 2924 | * SQR3 SQ15 LL_ADC_REG_SetSequencerRanks\n |
||
| 2925 | * SQR3 SQ16 LL_ADC_REG_SetSequencerRanks\n |
||
| 2926 | * SQR3 SQ17 LL_ADC_REG_SetSequencerRanks\n |
||
| 2927 | * SQR3 SQ18 LL_ADC_REG_SetSequencerRanks\n |
||
| 2928 | * SQR2 SQ19 LL_ADC_REG_SetSequencerRanks\n |
||
| 2929 | * SQR2 SQ20 LL_ADC_REG_SetSequencerRanks\n |
||
| 2930 | * SQR2 SQ21 LL_ADC_REG_SetSequencerRanks\n |
||
| 2931 | * SQR2 SQ22 LL_ADC_REG_SetSequencerRanks\n |
||
| 2932 | * SQR2 SQ23 LL_ADC_REG_SetSequencerRanks\n |
||
| 2933 | * SQR2 SQ24 LL_ADC_REG_SetSequencerRanks\n |
||
| 2934 | * SQR1 SQ25 LL_ADC_REG_SetSequencerRanks\n |
||
| 2935 | * SQR1 SQ26 LL_ADC_REG_SetSequencerRanks\n |
||
| 2936 | * SQR1 SQ27 LL_ADC_REG_SetSequencerRanks\n |
||
| 2937 | * SQR1 SQ28 LL_ADC_REG_SetSequencerRanks |
||
| 2938 | * @param ADCx ADC instance |
||
| 2939 | * @param Rank This parameter can be one of the following values: |
||
| 2940 | * @arg @ref LL_ADC_REG_RANK_1 |
||
| 2941 | * @arg @ref LL_ADC_REG_RANK_2 |
||
| 2942 | * @arg @ref LL_ADC_REG_RANK_3 |
||
| 2943 | * @arg @ref LL_ADC_REG_RANK_4 |
||
| 2944 | * @arg @ref LL_ADC_REG_RANK_5 |
||
| 2945 | * @arg @ref LL_ADC_REG_RANK_6 |
||
| 2946 | * @arg @ref LL_ADC_REG_RANK_7 |
||
| 2947 | * @arg @ref LL_ADC_REG_RANK_8 |
||
| 2948 | * @arg @ref LL_ADC_REG_RANK_9 |
||
| 2949 | * @arg @ref LL_ADC_REG_RANK_10 |
||
| 2950 | * @arg @ref LL_ADC_REG_RANK_11 |
||
| 2951 | * @arg @ref LL_ADC_REG_RANK_12 |
||
| 2952 | * @arg @ref LL_ADC_REG_RANK_13 |
||
| 2953 | * @arg @ref LL_ADC_REG_RANK_14 |
||
| 2954 | * @arg @ref LL_ADC_REG_RANK_15 |
||
| 2955 | * @arg @ref LL_ADC_REG_RANK_16 |
||
| 2956 | * @arg @ref LL_ADC_REG_RANK_17 |
||
| 2957 | * @arg @ref LL_ADC_REG_RANK_18 |
||
| 2958 | * @arg @ref LL_ADC_REG_RANK_19 |
||
| 2959 | * @arg @ref LL_ADC_REG_RANK_20 |
||
| 2960 | * @arg @ref LL_ADC_REG_RANK_21 |
||
| 2961 | * @arg @ref LL_ADC_REG_RANK_22 |
||
| 2962 | * @arg @ref LL_ADC_REG_RANK_23 |
||
| 2963 | * @arg @ref LL_ADC_REG_RANK_24 |
||
| 2964 | * @arg @ref LL_ADC_REG_RANK_25 |
||
| 2965 | * @arg @ref LL_ADC_REG_RANK_26 |
||
| 2966 | * @arg @ref LL_ADC_REG_RANK_27 |
||
| 2967 | * @arg @ref LL_ADC_REG_RANK_28 (1) |
||
| 2968 | * |
||
| 2969 | * (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5. |
||
| 2970 | * @param Channel This parameter can be one of the following values: |
||
| 2971 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 2972 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 2973 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 2974 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 2975 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 2976 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 2977 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 2978 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 2979 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 2980 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 2981 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 2982 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 2983 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 2984 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 2985 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 2986 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 2987 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 2988 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 2989 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 2990 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 2991 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 2992 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 2993 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 2994 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 2995 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 2996 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 2997 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 2998 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 2999 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 3000 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 3001 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 3002 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 3003 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3) |
||
| 3004 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3) |
||
| 3005 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3) |
||
| 3006 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 3007 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 3008 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 3009 | * |
||
| 3010 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 3011 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 3012 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 3013 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 3014 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5 |
||
| 3015 | * @retval None |
||
| 3016 | */ |
||
| 3017 | __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) |
||
| 3018 | { |
||
| 3019 | /* Set bits with content of parameter "Channel" with bits position */ |
||
| 3020 | /* in register and register position depending on parameter "Rank". */ |
||
| 3021 | /* Parameters "Rank" and "Channel" are used with masks because containing */ |
||
| 3022 | /* other bits reserved for other purpose. */ |
||
| 3023 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); |
||
| 3024 | |||
| 3025 | MODIFY_REG(*preg, |
||
| 3026 | ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), |
||
| 3027 | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); |
||
| 3028 | } |
||
| 3029 | |||
| 3030 | /** |
||
| 3031 | * @brief Get ADC group regular sequence: channel on the selected |
||
| 3032 | * scan sequence rank. |
||
| 3033 | * @note On this STM32 series, ADC group regular sequencer is |
||
| 3034 | * fully configurable: sequencer length and each rank |
||
| 3035 | * affectation to a channel are configurable. |
||
| 3036 | * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). |
||
| 3037 | * @note Depending on devices and packages, some channels may not be available. |
||
| 3038 | * Refer to device datasheet for channels availability. |
||
| 3039 | * @note Usage of the returned channel number: |
||
| 3040 | * - To reinject this channel into another function LL_ADC_xxx: |
||
| 3041 | * the returned channel number is only partly formatted on definition |
||
| 3042 | * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared |
||
| 3043 | * with parts of literals LL_ADC_CHANNEL_x or using |
||
| 3044 | * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). |
||
| 3045 | * Then the selected literal LL_ADC_CHANNEL_x can be used |
||
| 3046 | * as parameter for another function. |
||
| 3047 | * - To get the channel number in decimal format: |
||
| 3048 | * process the returned value with the helper macro |
||
| 3049 | * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). |
||
| 3050 | * @rmtoll SQR5 SQ1 LL_ADC_REG_GetSequencerRanks\n |
||
| 3051 | * SQR5 SQ2 LL_ADC_REG_GetSequencerRanks\n |
||
| 3052 | * SQR5 SQ3 LL_ADC_REG_GetSequencerRanks\n |
||
| 3053 | * SQR5 SQ4 LL_ADC_REG_GetSequencerRanks\n |
||
| 3054 | * SQR5 SQ5 LL_ADC_REG_GetSequencerRanks\n |
||
| 3055 | * SQR5 SQ6 LL_ADC_REG_GetSequencerRanks\n |
||
| 3056 | * SQR4 SQ7 LL_ADC_REG_GetSequencerRanks\n |
||
| 3057 | * SQR4 SQ8 LL_ADC_REG_GetSequencerRanks\n |
||
| 3058 | * SQR4 SQ9 LL_ADC_REG_GetSequencerRanks\n |
||
| 3059 | * SQR4 SQ10 LL_ADC_REG_GetSequencerRanks\n |
||
| 3060 | * SQR4 SQ11 LL_ADC_REG_GetSequencerRanks\n |
||
| 3061 | * SQR4 SQ12 LL_ADC_REG_GetSequencerRanks\n |
||
| 3062 | * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n |
||
| 3063 | * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n |
||
| 3064 | * SQR3 SQ15 LL_ADC_REG_GetSequencerRanks\n |
||
| 3065 | * SQR3 SQ16 LL_ADC_REG_GetSequencerRanks\n |
||
| 3066 | * SQR3 SQ17 LL_ADC_REG_GetSequencerRanks\n |
||
| 3067 | * SQR3 SQ18 LL_ADC_REG_GetSequencerRanks\n |
||
| 3068 | * SQR2 SQ19 LL_ADC_REG_GetSequencerRanks\n |
||
| 3069 | * SQR2 SQ20 LL_ADC_REG_GetSequencerRanks\n |
||
| 3070 | * SQR2 SQ21 LL_ADC_REG_GetSequencerRanks\n |
||
| 3071 | * SQR2 SQ22 LL_ADC_REG_GetSequencerRanks\n |
||
| 3072 | * SQR2 SQ23 LL_ADC_REG_GetSequencerRanks\n |
||
| 3073 | * SQR2 SQ24 LL_ADC_REG_GetSequencerRanks\n |
||
| 3074 | * SQR1 SQ25 LL_ADC_REG_GetSequencerRanks\n |
||
| 3075 | * SQR1 SQ26 LL_ADC_REG_GetSequencerRanks\n |
||
| 3076 | * SQR1 SQ27 LL_ADC_REG_GetSequencerRanks\n |
||
| 3077 | * SQR1 SQ28 LL_ADC_REG_GetSequencerRanks |
||
| 3078 | * @param ADCx ADC instance |
||
| 3079 | * @param Rank This parameter can be one of the following values: |
||
| 3080 | * @arg @ref LL_ADC_REG_RANK_1 |
||
| 3081 | * @arg @ref LL_ADC_REG_RANK_2 |
||
| 3082 | * @arg @ref LL_ADC_REG_RANK_3 |
||
| 3083 | * @arg @ref LL_ADC_REG_RANK_4 |
||
| 3084 | * @arg @ref LL_ADC_REG_RANK_5 |
||
| 3085 | * @arg @ref LL_ADC_REG_RANK_6 |
||
| 3086 | * @arg @ref LL_ADC_REG_RANK_7 |
||
| 3087 | * @arg @ref LL_ADC_REG_RANK_8 |
||
| 3088 | * @arg @ref LL_ADC_REG_RANK_9 |
||
| 3089 | * @arg @ref LL_ADC_REG_RANK_10 |
||
| 3090 | * @arg @ref LL_ADC_REG_RANK_11 |
||
| 3091 | * @arg @ref LL_ADC_REG_RANK_12 |
||
| 3092 | * @arg @ref LL_ADC_REG_RANK_13 |
||
| 3093 | * @arg @ref LL_ADC_REG_RANK_14 |
||
| 3094 | * @arg @ref LL_ADC_REG_RANK_15 |
||
| 3095 | * @arg @ref LL_ADC_REG_RANK_16 |
||
| 3096 | * @arg @ref LL_ADC_REG_RANK_17 |
||
| 3097 | * @arg @ref LL_ADC_REG_RANK_18 |
||
| 3098 | * @arg @ref LL_ADC_REG_RANK_19 |
||
| 3099 | * @arg @ref LL_ADC_REG_RANK_20 |
||
| 3100 | * @arg @ref LL_ADC_REG_RANK_21 |
||
| 3101 | * @arg @ref LL_ADC_REG_RANK_22 |
||
| 3102 | * @arg @ref LL_ADC_REG_RANK_23 |
||
| 3103 | * @arg @ref LL_ADC_REG_RANK_24 |
||
| 3104 | * @arg @ref LL_ADC_REG_RANK_25 |
||
| 3105 | * @arg @ref LL_ADC_REG_RANK_26 |
||
| 3106 | * @arg @ref LL_ADC_REG_RANK_27 |
||
| 3107 | * @arg @ref LL_ADC_REG_RANK_28 (1) |
||
| 3108 | * |
||
| 3109 | * (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5. |
||
| 3110 | * @retval Returned value can be one of the following values: |
||
| 3111 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 3112 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 3113 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 3114 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 3115 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 3116 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 3117 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 3118 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 3119 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 3120 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 3121 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 3122 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 3123 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 3124 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 3125 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 3126 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 3127 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 3128 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 3129 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 3130 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 3131 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 3132 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 3133 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 3134 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 3135 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 3136 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 3137 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 3138 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 3139 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 3140 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 3141 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 3142 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 3143 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6) |
||
| 3144 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6) |
||
| 3145 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6) |
||
| 3146 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 3147 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 3148 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 3149 | * |
||
| 3150 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 3151 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 3152 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 3153 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 3154 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n |
||
| 3155 | * (6) For ADC channel read back from ADC register, |
||
| 3156 | * comparison with internal channel parameter to be done |
||
| 3157 | * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). |
||
| 3158 | */ |
||
| 3159 | __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) |
||
| 3160 | { |
||
| 3161 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); |
||
| 3162 | |||
| 3163 | return (uint32_t) (READ_BIT(*preg, |
||
| 3164 | ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) |
||
| 3165 | >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) |
||
| 3166 | ); |
||
| 3167 | } |
||
| 3168 | |||
| 3169 | /** |
||
| 3170 | * @brief Set ADC continuous conversion mode on ADC group regular. |
||
| 3171 | * @note Description of ADC continuous conversion mode: |
||
| 3172 | * - single mode: one conversion per trigger |
||
| 3173 | * - continuous mode: after the first trigger, following |
||
| 3174 | * conversions launched successively automatically. |
||
| 3175 | * @note It is not possible to enable both ADC group regular |
||
| 3176 | * continuous mode and sequencer discontinuous mode. |
||
| 3177 | * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode |
||
| 3178 | * @param ADCx ADC instance |
||
| 3179 | * @param Continuous This parameter can be one of the following values: |
||
| 3180 | * @arg @ref LL_ADC_REG_CONV_SINGLE |
||
| 3181 | * @arg @ref LL_ADC_REG_CONV_CONTINUOUS |
||
| 3182 | * @retval None |
||
| 3183 | */ |
||
| 3184 | __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) |
||
| 3185 | { |
||
| 3186 | MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); |
||
| 3187 | } |
||
| 3188 | |||
| 3189 | /** |
||
| 3190 | * @brief Get ADC continuous conversion mode on ADC group regular. |
||
| 3191 | * @note Description of ADC continuous conversion mode: |
||
| 3192 | * - single mode: one conversion per trigger |
||
| 3193 | * - continuous mode: after the first trigger, following |
||
| 3194 | * conversions launched successively automatically. |
||
| 3195 | * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode |
||
| 3196 | * @param ADCx ADC instance |
||
| 3197 | * @retval Returned value can be one of the following values: |
||
| 3198 | * @arg @ref LL_ADC_REG_CONV_SINGLE |
||
| 3199 | * @arg @ref LL_ADC_REG_CONV_CONTINUOUS |
||
| 3200 | */ |
||
| 3201 | __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) |
||
| 3202 | { |
||
| 3203 | return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); |
||
| 3204 | } |
||
| 3205 | |||
| 3206 | /** |
||
| 3207 | * @brief Set ADC group regular conversion data transfer: no transfer or |
||
| 3208 | * transfer by DMA, and DMA requests mode. |
||
| 3209 | * @note If transfer by DMA selected, specifies the DMA requests |
||
| 3210 | * mode: |
||
| 3211 | * - Limited mode (One shot mode): DMA transfer requests are stopped |
||
| 3212 | * when number of DMA data transfers (number of |
||
| 3213 | * ADC conversions) is reached. |
||
| 3214 | * This ADC mode is intended to be used with DMA mode non-circular. |
||
| 3215 | * - Unlimited mode: DMA transfer requests are unlimited, |
||
| 3216 | * whatever number of DMA data transfers (number of |
||
| 3217 | * ADC conversions). |
||
| 3218 | * This ADC mode is intended to be used with DMA mode circular. |
||
| 3219 | * @note If ADC DMA requests mode is set to unlimited and DMA is set to |
||
| 3220 | * mode non-circular: |
||
| 3221 | * when DMA transfers size will be reached, DMA will stop transfers of |
||
| 3222 | * ADC conversions data ADC will raise an overrun error |
||
| 3223 | * (overrun flag and interruption if enabled). |
||
| 3224 | * @note To configure DMA source address (peripheral address), |
||
| 3225 | * use function @ref LL_ADC_DMA_GetRegAddr(). |
||
| 3226 | * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n |
||
| 3227 | * CR2 DDS LL_ADC_REG_SetDMATransfer |
||
| 3228 | * @param ADCx ADC instance |
||
| 3229 | * @param DMATransfer This parameter can be one of the following values: |
||
| 3230 | * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE |
||
| 3231 | * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED |
||
| 3232 | * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED |
||
| 3233 | * @retval None |
||
| 3234 | */ |
||
| 3235 | __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) |
||
| 3236 | { |
||
| 3237 | MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer); |
||
| 3238 | } |
||
| 3239 | |||
| 3240 | /** |
||
| 3241 | * @brief Get ADC group regular conversion data transfer: no transfer or |
||
| 3242 | * transfer by DMA, and DMA requests mode. |
||
| 3243 | * @note If transfer by DMA selected, specifies the DMA requests |
||
| 3244 | * mode: |
||
| 3245 | * - Limited mode (One shot mode): DMA transfer requests are stopped |
||
| 3246 | * when number of DMA data transfers (number of |
||
| 3247 | * ADC conversions) is reached. |
||
| 3248 | * This ADC mode is intended to be used with DMA mode non-circular. |
||
| 3249 | * - Unlimited mode: DMA transfer requests are unlimited, |
||
| 3250 | * whatever number of DMA data transfers (number of |
||
| 3251 | * ADC conversions). |
||
| 3252 | * This ADC mode is intended to be used with DMA mode circular. |
||
| 3253 | * @note If ADC DMA requests mode is set to unlimited and DMA is set to |
||
| 3254 | * mode non-circular: |
||
| 3255 | * when DMA transfers size will be reached, DMA will stop transfers of |
||
| 3256 | * ADC conversions data ADC will raise an overrun error |
||
| 3257 | * (overrun flag and interruption if enabled). |
||
| 3258 | * @note To configure DMA source address (peripheral address), |
||
| 3259 | * use function @ref LL_ADC_DMA_GetRegAddr(). |
||
| 3260 | * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n |
||
| 3261 | * CR2 DDS LL_ADC_REG_GetDMATransfer |
||
| 3262 | * @param ADCx ADC instance |
||
| 3263 | * @retval Returned value can be one of the following values: |
||
| 3264 | * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE |
||
| 3265 | * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED |
||
| 3266 | * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED |
||
| 3267 | */ |
||
| 3268 | __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) |
||
| 3269 | { |
||
| 3270 | return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS)); |
||
| 3271 | } |
||
| 3272 | |||
| 3273 | /** |
||
| 3274 | * @brief Specify which ADC flag between EOC (end of unitary conversion) |
||
| 3275 | * or EOS (end of sequence conversions) is used to indicate |
||
| 3276 | * the end of conversion. |
||
| 3277 | * @note This feature is aimed to be set when using ADC with |
||
| 3278 | * programming model by polling or interruption |
||
| 3279 | * (programming model by DMA usually uses DMA interruptions |
||
| 3280 | * to indicate end of conversion and data transfer). |
||
| 3281 | * @note For ADC group injected, end of conversion (flag&IT) is raised |
||
| 3282 | * only at the end of the sequence. |
||
| 3283 | * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion |
||
| 3284 | * @param ADCx ADC instance |
||
| 3285 | * @param EocSelection This parameter can be one of the following values: |
||
| 3286 | * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV |
||
| 3287 | * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV |
||
| 3288 | * @retval None |
||
| 3289 | */ |
||
| 3290 | __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection) |
||
| 3291 | { |
||
| 3292 | MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection); |
||
| 3293 | } |
||
| 3294 | |||
| 3295 | /** |
||
| 3296 | * @brief Get which ADC flag between EOC (end of unitary conversion) |
||
| 3297 | * or EOS (end of sequence conversions) is used to indicate |
||
| 3298 | * the end of conversion. |
||
| 3299 | * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion |
||
| 3300 | * @param ADCx ADC instance |
||
| 3301 | * @retval Returned value can be one of the following values: |
||
| 3302 | * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV |
||
| 3303 | * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV |
||
| 3304 | */ |
||
| 3305 | __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) |
||
| 3306 | { |
||
| 3307 | return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS)); |
||
| 3308 | } |
||
| 3309 | |||
| 3310 | /** |
||
| 3311 | * @} |
||
| 3312 | */ |
||
| 3313 | |||
| 3314 | /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected |
||
| 3315 | * @{ |
||
| 3316 | */ |
||
| 3317 | |||
| 3318 | /** |
||
| 3319 | * @brief Set ADC group injected conversion trigger source: |
||
| 3320 | * internal (SW start) or from external IP (timer event, |
||
| 3321 | * external interrupt line). |
||
| 3322 | * @note On this STM32 series, setting of external trigger edge is performed |
||
| 3323 | * using function @ref LL_ADC_INJ_StartConversionExtTrig(). |
||
| 3324 | * @note Availability of parameters of trigger sources from timer |
||
| 3325 | * depends on timers availability on the selected device. |
||
| 3326 | * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n |
||
| 3327 | * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource |
||
| 3328 | * @param ADCx ADC instance |
||
| 3329 | * @param TriggerSource This parameter can be one of the following values: |
||
| 3330 | * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE |
||
| 3331 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1 |
||
| 3332 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO |
||
| 3333 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO |
||
| 3334 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 |
||
| 3335 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 |
||
| 3336 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO |
||
| 3337 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1 |
||
| 3338 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2 |
||
| 3339 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 |
||
| 3340 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM10_CH1 |
||
| 3341 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO |
||
| 3342 | * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 |
||
| 3343 | * @retval None |
||
| 3344 | */ |
||
| 3345 | __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) |
||
| 3346 | { |
||
| 3347 | /* Note: On this STM32 series, ADC group injected external trigger edge */ |
||
| 3348 | /* is used to perform a ADC conversion start. */ |
||
| 3349 | /* This function does not set external trigger edge. */ |
||
| 3350 | /* This feature is set using function */ |
||
| 3351 | /* @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
||
| 3352 | MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); |
||
| 3353 | } |
||
| 3354 | |||
| 3355 | /** |
||
| 3356 | * @brief Get ADC group injected conversion trigger source: |
||
| 3357 | * internal (SW start) or from external IP (timer event, |
||
| 3358 | * external interrupt line). |
||
| 3359 | * @note To determine whether group injected trigger source is |
||
| 3360 | * internal (SW start) or external, without detail |
||
| 3361 | * of which peripheral is selected as external trigger, |
||
| 3362 | * (equivalent to |
||
| 3363 | * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") |
||
| 3364 | * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. |
||
| 3365 | * @note Availability of parameters of trigger sources from timer |
||
| 3366 | * depends on timers availability on the selected device. |
||
| 3367 | * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n |
||
| 3368 | * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource |
||
| 3369 | * @param ADCx ADC instance |
||
| 3370 | * @retval Returned value can be one of the following values: |
||
| 3371 | * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE |
||
| 3372 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1 |
||
| 3373 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO |
||
| 3374 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO |
||
| 3375 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 |
||
| 3376 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 |
||
| 3377 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO |
||
| 3378 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1 |
||
| 3379 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2 |
||
| 3380 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 |
||
| 3381 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM10_CH1 |
||
| 3382 | * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO |
||
| 3383 | * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 |
||
| 3384 | */ |
||
| 3385 | __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) |
||
| 3386 | { |
||
| 3387 | uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); |
||
| 3388 | |||
| 3389 | /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ |
||
| 3390 | /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */ |
||
| 3391 | uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); |
||
| 3392 | |||
| 3393 | /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */ |
||
| 3394 | /* to match with triggers literals definition. */ |
||
| 3395 | return ((TriggerSource |
||
| 3396 | & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL) |
||
| 3397 | | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN) |
||
| 3398 | ); |
||
| 3399 | } |
||
| 3400 | |||
| 3401 | /** |
||
| 3402 | * @brief Get ADC group injected conversion trigger source internal (SW start) |
||
| 3403 | or external |
||
| 3404 | * @note In case of group injected trigger source set to external trigger, |
||
| 3405 | * to determine which peripheral is selected as external trigger, |
||
| 3406 | * use function @ref LL_ADC_INJ_GetTriggerSource. |
||
| 3407 | * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart |
||
| 3408 | * @param ADCx ADC instance |
||
| 3409 | * @retval Value "0" if trigger source external trigger |
||
| 3410 | * Value "1" if trigger source SW start. |
||
| 3411 | */ |
||
| 3412 | __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) |
||
| 3413 | { |
||
| 3414 | return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN)); |
||
| 3415 | } |
||
| 3416 | |||
| 3417 | /** |
||
| 3418 | * @brief Get ADC group injected conversion trigger polarity. |
||
| 3419 | * Applicable only for trigger source set to external trigger. |
||
| 3420 | * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge |
||
| 3421 | * @param ADCx ADC instance |
||
| 3422 | * @retval Returned value can be one of the following values: |
||
| 3423 | * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING |
||
| 3424 | * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING |
||
| 3425 | * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING |
||
| 3426 | */ |
||
| 3427 | __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) |
||
| 3428 | { |
||
| 3429 | return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN)); |
||
| 3430 | } |
||
| 3431 | |||
| 3432 | /** |
||
| 3433 | * @brief Set ADC group injected sequencer length and scan direction. |
||
| 3434 | * @note This function performs configuration of: |
||
| 3435 | * - Sequence length: Number of ranks in the scan sequence. |
||
| 3436 | * - Sequence direction: Unless specified in parameters, sequencer |
||
| 3437 | * scan direction is forward (from rank 1 to rank n). |
||
| 3438 | * @note On this STM32 series, group injected sequencer configuration |
||
| 3439 | * is conditioned to ADC instance sequencer mode. |
||
| 3440 | * If ADC instance sequencer mode is disabled, sequencers of |
||
| 3441 | * all groups (group regular, group injected) can be configured |
||
| 3442 | * but their execution is disabled (limited to rank 1). |
||
| 3443 | * Refer to function @ref LL_ADC_SetSequencersScanMode(). |
||
| 3444 | * @note Sequencer disabled is equivalent to sequencer of 1 rank: |
||
| 3445 | * ADC conversion on only 1 channel. |
||
| 3446 | * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength |
||
| 3447 | * @param ADCx ADC instance |
||
| 3448 | * @param SequencerNbRanks This parameter can be one of the following values: |
||
| 3449 | * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE |
||
| 3450 | * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS |
||
| 3451 | * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS |
||
| 3452 | * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS |
||
| 3453 | * @retval None |
||
| 3454 | */ |
||
| 3455 | __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) |
||
| 3456 | { |
||
| 3457 | MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); |
||
| 3458 | } |
||
| 3459 | |||
| 3460 | /** |
||
| 3461 | * @brief Get ADC group injected sequencer length and scan direction. |
||
| 3462 | * @note This function retrieves: |
||
| 3463 | * - Sequence length: Number of ranks in the scan sequence. |
||
| 3464 | * - Sequence direction: Unless specified in parameters, sequencer |
||
| 3465 | * scan direction is forward (from rank 1 to rank n). |
||
| 3466 | * @note On this STM32 series, group injected sequencer configuration |
||
| 3467 | * is conditioned to ADC instance sequencer mode. |
||
| 3468 | * If ADC instance sequencer mode is disabled, sequencers of |
||
| 3469 | * all groups (group regular, group injected) can be configured |
||
| 3470 | * but their execution is disabled (limited to rank 1). |
||
| 3471 | * Refer to function @ref LL_ADC_SetSequencersScanMode(). |
||
| 3472 | * @note Sequencer disabled is equivalent to sequencer of 1 rank: |
||
| 3473 | * ADC conversion on only 1 channel. |
||
| 3474 | * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength |
||
| 3475 | * @param ADCx ADC instance |
||
| 3476 | * @retval Returned value can be one of the following values: |
||
| 3477 | * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE |
||
| 3478 | * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS |
||
| 3479 | * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS |
||
| 3480 | * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS |
||
| 3481 | */ |
||
| 3482 | __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) |
||
| 3483 | { |
||
| 3484 | return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); |
||
| 3485 | } |
||
| 3486 | |||
| 3487 | /** |
||
| 3488 | * @brief Set ADC group injected sequencer discontinuous mode: |
||
| 3489 | * sequence subdivided and scan conversions interrupted every selected |
||
| 3490 | * number of ranks. |
||
| 3491 | * @note It is not possible to enable both ADC group injected |
||
| 3492 | * auto-injected mode and sequencer discontinuous mode. |
||
| 3493 | * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont |
||
| 3494 | * @param ADCx ADC instance |
||
| 3495 | * @param SeqDiscont This parameter can be one of the following values: |
||
| 3496 | * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE |
||
| 3497 | * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK |
||
| 3498 | * @retval None |
||
| 3499 | */ |
||
| 3500 | __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) |
||
| 3501 | { |
||
| 3502 | MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); |
||
| 3503 | } |
||
| 3504 | |||
| 3505 | /** |
||
| 3506 | * @brief Get ADC group injected sequencer discontinuous mode: |
||
| 3507 | * sequence subdivided and scan conversions interrupted every selected |
||
| 3508 | * number of ranks. |
||
| 3509 | * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont |
||
| 3510 | * @param ADCx ADC instance |
||
| 3511 | * @retval Returned value can be one of the following values: |
||
| 3512 | * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE |
||
| 3513 | * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK |
||
| 3514 | */ |
||
| 3515 | __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) |
||
| 3516 | { |
||
| 3517 | return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); |
||
| 3518 | } |
||
| 3519 | |||
| 3520 | /** |
||
| 3521 | * @brief Set ADC group injected sequence: channel on the selected |
||
| 3522 | * sequence rank. |
||
| 3523 | * @note Depending on devices and packages, some channels may not be available. |
||
| 3524 | * Refer to device datasheet for channels availability. |
||
| 3525 | * @note On this STM32 series, to measure internal channels (VrefInt, |
||
| 3526 | * TempSensor, ...), measurement paths to internal channels must be |
||
| 3527 | * enabled separately. |
||
| 3528 | * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). |
||
| 3529 | * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n |
||
| 3530 | * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n |
||
| 3531 | * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n |
||
| 3532 | * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks |
||
| 3533 | * @param ADCx ADC instance |
||
| 3534 | * @param Rank This parameter can be one of the following values: |
||
| 3535 | * @arg @ref LL_ADC_INJ_RANK_1 |
||
| 3536 | * @arg @ref LL_ADC_INJ_RANK_2 |
||
| 3537 | * @arg @ref LL_ADC_INJ_RANK_3 |
||
| 3538 | * @arg @ref LL_ADC_INJ_RANK_4 |
||
| 3539 | * @param Channel This parameter can be one of the following values: |
||
| 3540 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 3541 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 3542 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 3543 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 3544 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 3545 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 3546 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 3547 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 3548 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 3549 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 3550 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 3551 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 3552 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 3553 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 3554 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 3555 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 3556 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 3557 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 3558 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 3559 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 3560 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 3561 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 3562 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 3563 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 3564 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 3565 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 3566 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 3567 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 3568 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 3569 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 3570 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 3571 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 3572 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3) |
||
| 3573 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3) |
||
| 3574 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3) |
||
| 3575 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 3576 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 3577 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 3578 | * |
||
| 3579 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 3580 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 3581 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 3582 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 3583 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5 |
||
| 3584 | * @retval None |
||
| 3585 | */ |
||
| 3586 | __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) |
||
| 3587 | { |
||
| 3588 | /* Set bits with content of parameter "Channel" with bits position */ |
||
| 3589 | /* in register depending on parameter "Rank". */ |
||
| 3590 | /* Parameters "Rank" and "Channel" are used with masks because containing */ |
||
| 3591 | /* other bits reserved for other purpose. */ |
||
| 3592 | MODIFY_REG(ADCx->JSQR, |
||
| 3593 | ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), |
||
| 3594 | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); |
||
| 3595 | } |
||
| 3596 | |||
| 3597 | /** |
||
| 3598 | * @brief Get ADC group injected sequence: channel on the selected |
||
| 3599 | * sequence rank. |
||
| 3600 | * @note Depending on devices and packages, some channels may not be available. |
||
| 3601 | * Refer to device datasheet for channels availability. |
||
| 3602 | * @note Usage of the returned channel number: |
||
| 3603 | * - To reinject this channel into another function LL_ADC_xxx: |
||
| 3604 | * the returned channel number is only partly formatted on definition |
||
| 3605 | * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared |
||
| 3606 | * with parts of literals LL_ADC_CHANNEL_x or using |
||
| 3607 | * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). |
||
| 3608 | * Then the selected literal LL_ADC_CHANNEL_x can be used |
||
| 3609 | * as parameter for another function. |
||
| 3610 | * - To get the channel number in decimal format: |
||
| 3611 | * process the returned value with the helper macro |
||
| 3612 | * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). |
||
| 3613 | * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n |
||
| 3614 | * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n |
||
| 3615 | * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n |
||
| 3616 | * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks |
||
| 3617 | * @param ADCx ADC instance |
||
| 3618 | * @param Rank This parameter can be one of the following values: |
||
| 3619 | * @arg @ref LL_ADC_INJ_RANK_1 |
||
| 3620 | * @arg @ref LL_ADC_INJ_RANK_2 |
||
| 3621 | * @arg @ref LL_ADC_INJ_RANK_3 |
||
| 3622 | * @arg @ref LL_ADC_INJ_RANK_4 |
||
| 3623 | * @retval Returned value can be one of the following values: |
||
| 3624 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 3625 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 3626 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 3627 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 3628 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 3629 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 3630 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 3631 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 3632 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 3633 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 3634 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 3635 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 3636 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 3637 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 3638 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 3639 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 3640 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 3641 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 3642 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 3643 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 3644 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 3645 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 3646 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 3647 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 3648 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 3649 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 3650 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 3651 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 3652 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 3653 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 3654 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 3655 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 3656 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6) |
||
| 3657 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6) |
||
| 3658 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6) |
||
| 3659 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 3660 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 3661 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 3662 | * |
||
| 3663 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 3664 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 3665 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 3666 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 3667 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n |
||
| 3668 | * (6) For ADC channel read back from ADC register, |
||
| 3669 | * comparison with internal channel parameter to be done |
||
| 3670 | * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). |
||
| 3671 | */ |
||
| 3672 | __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) |
||
| 3673 | { |
||
| 3674 | return (uint32_t)(READ_BIT(ADCx->JSQR, |
||
| 3675 | ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) |
||
| 3676 | >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK) |
||
| 3677 | ); |
||
| 3678 | } |
||
| 3679 | |||
| 3680 | /** |
||
| 3681 | * @brief Set ADC group injected conversion trigger: |
||
| 3682 | * independent or from ADC group regular. |
||
| 3683 | * @note This mode can be used to extend number of data registers |
||
| 3684 | * updated after one ADC conversion trigger and with data |
||
| 3685 | * permanently kept (not erased by successive conversions of scan of |
||
| 3686 | * ADC sequencer ranks), up to 5 data registers: |
||
| 3687 | * 1 data register on ADC group regular, 4 data registers |
||
| 3688 | * on ADC group injected. |
||
| 3689 | * @note If ADC group injected injected trigger source is set to an |
||
| 3690 | * external trigger, this feature must be must be set to |
||
| 3691 | * independent trigger. |
||
| 3692 | * ADC group injected automatic trigger is compliant only with |
||
| 3693 | * group injected trigger source set to SW start, without any |
||
| 3694 | * further action on ADC group injected conversion start or stop: |
||
| 3695 | * in this case, ADC group injected is controlled only |
||
| 3696 | * from ADC group regular. |
||
| 3697 | * @note It is not possible to enable both ADC group injected |
||
| 3698 | * auto-injected mode and sequencer discontinuous mode. |
||
| 3699 | * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto |
||
| 3700 | * @param ADCx ADC instance |
||
| 3701 | * @param TrigAuto This parameter can be one of the following values: |
||
| 3702 | * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT |
||
| 3703 | * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR |
||
| 3704 | * @retval None |
||
| 3705 | */ |
||
| 3706 | __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) |
||
| 3707 | { |
||
| 3708 | MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); |
||
| 3709 | } |
||
| 3710 | |||
| 3711 | /** |
||
| 3712 | * @brief Get ADC group injected conversion trigger: |
||
| 3713 | * independent or from ADC group regular. |
||
| 3714 | * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto |
||
| 3715 | * @param ADCx ADC instance |
||
| 3716 | * @retval Returned value can be one of the following values: |
||
| 3717 | * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT |
||
| 3718 | * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR |
||
| 3719 | */ |
||
| 3720 | __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) |
||
| 3721 | { |
||
| 3722 | return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); |
||
| 3723 | } |
||
| 3724 | |||
| 3725 | /** |
||
| 3726 | * @brief Set ADC group injected offset. |
||
| 3727 | * @note It sets: |
||
| 3728 | * - ADC group injected rank to which the offset programmed |
||
| 3729 | * will be applied |
||
| 3730 | * - Offset level (offset to be subtracted from the raw |
||
| 3731 | * converted data). |
||
| 3732 | * Caution: Offset format is dependent to ADC resolution: |
||
| 3733 | * offset has to be left-aligned on bit 11, the LSB (right bits) |
||
| 3734 | * are set to 0. |
||
| 3735 | * @note Offset cannot be enabled or disabled. |
||
| 3736 | * To emulate offset disabled, set an offset value equal to 0. |
||
| 3737 | * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n |
||
| 3738 | * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n |
||
| 3739 | * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n |
||
| 3740 | * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset |
||
| 3741 | * @param ADCx ADC instance |
||
| 3742 | * @param Rank This parameter can be one of the following values: |
||
| 3743 | * @arg @ref LL_ADC_INJ_RANK_1 |
||
| 3744 | * @arg @ref LL_ADC_INJ_RANK_2 |
||
| 3745 | * @arg @ref LL_ADC_INJ_RANK_3 |
||
| 3746 | * @arg @ref LL_ADC_INJ_RANK_4 |
||
| 3747 | * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 3748 | * @retval None |
||
| 3749 | */ |
||
| 3750 | __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) |
||
| 3751 | { |
||
| 3752 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); |
||
| 3753 | |||
| 3754 | MODIFY_REG(*preg, |
||
| 3755 | ADC_JOFR1_JOFFSET1, |
||
| 3756 | OffsetLevel); |
||
| 3757 | } |
||
| 3758 | |||
| 3759 | /** |
||
| 3760 | * @brief Get ADC group injected offset. |
||
| 3761 | * @note It gives offset level (offset to be subtracted from the raw converted data). |
||
| 3762 | * Caution: Offset format is dependent to ADC resolution: |
||
| 3763 | * offset has to be left-aligned on bit 11, the LSB (right bits) |
||
| 3764 | * are set to 0. |
||
| 3765 | * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n |
||
| 3766 | * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n |
||
| 3767 | * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n |
||
| 3768 | * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset |
||
| 3769 | * @param ADCx ADC instance |
||
| 3770 | * @param Rank This parameter can be one of the following values: |
||
| 3771 | * @arg @ref LL_ADC_INJ_RANK_1 |
||
| 3772 | * @arg @ref LL_ADC_INJ_RANK_2 |
||
| 3773 | * @arg @ref LL_ADC_INJ_RANK_3 |
||
| 3774 | * @arg @ref LL_ADC_INJ_RANK_4 |
||
| 3775 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 3776 | */ |
||
| 3777 | __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) |
||
| 3778 | { |
||
| 3779 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); |
||
| 3780 | |||
| 3781 | return (uint32_t)(READ_BIT(*preg, |
||
| 3782 | ADC_JOFR1_JOFFSET1) |
||
| 3783 | ); |
||
| 3784 | } |
||
| 3785 | |||
| 3786 | /** |
||
| 3787 | * @} |
||
| 3788 | */ |
||
| 3789 | |||
| 3790 | /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels |
||
| 3791 | * @{ |
||
| 3792 | */ |
||
| 3793 | |||
| 3794 | /** |
||
| 3795 | * @brief Set sampling time of the selected ADC channel |
||
| 3796 | * Unit: ADC clock cycles. |
||
| 3797 | * @note On this device, sampling time is on channel scope: independently |
||
| 3798 | * of channel mapped on ADC group regular or injected. |
||
| 3799 | * @note In case of internal channel (VrefInt, TempSensor, ...) to be |
||
| 3800 | * converted: |
||
| 3801 | * sampling time constraints must be respected (sampling time can be |
||
| 3802 | * adjusted in function of ADC clock frequency and sampling time |
||
| 3803 | * setting). |
||
| 3804 | * Refer to device datasheet for timings values (parameters TS_vrefint, |
||
| 3805 | * TS_temp, ...). |
||
| 3806 | * @note Conversion time is the addition of sampling time and processing time. |
||
| 3807 | * Refer to reference manual for ADC processing time of |
||
| 3808 | * this STM32 series. |
||
| 3809 | * @note In case of ADC conversion of internal channel (VrefInt, |
||
| 3810 | * temperature sensor, ...), a sampling time minimum value |
||
| 3811 | * is required. |
||
| 3812 | * Refer to device datasheet. |
||
| 3813 | * @rmtoll SMPR0 SMP31 LL_ADC_SetChannelSamplingTime\n |
||
| 3814 | * SMPR0 SMP30 LL_ADC_SetChannelSamplingTime\n |
||
| 3815 | * SMPR1 SMP29 LL_ADC_SetChannelSamplingTime\n |
||
| 3816 | * SMPR1 SMP28 LL_ADC_SetChannelSamplingTime\n |
||
| 3817 | * SMPR1 SMP27 LL_ADC_SetChannelSamplingTime\n |
||
| 3818 | * SMPR1 SMP26 LL_ADC_SetChannelSamplingTime\n |
||
| 3819 | * SMPR1 SMP25 LL_ADC_SetChannelSamplingTime\n |
||
| 3820 | * SMPR1 SMP24 LL_ADC_SetChannelSamplingTime\n |
||
| 3821 | * SMPR1 SMP23 LL_ADC_SetChannelSamplingTime\n |
||
| 3822 | * SMPR1 SMP22 LL_ADC_SetChannelSamplingTime\n |
||
| 3823 | * SMPR1 SMP21 LL_ADC_SetChannelSamplingTime\n |
||
| 3824 | * SMPR1 SMP20 LL_ADC_SetChannelSamplingTime\n |
||
| 3825 | * SMPR2 SMP19 LL_ADC_SetChannelSamplingTime\n |
||
| 3826 | * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime\n |
||
| 3827 | * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n |
||
| 3828 | * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n |
||
| 3829 | * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n |
||
| 3830 | * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n |
||
| 3831 | * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n |
||
| 3832 | * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n |
||
| 3833 | * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n |
||
| 3834 | * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n |
||
| 3835 | * SMPR3 SMP9 LL_ADC_SetChannelSamplingTime\n |
||
| 3836 | * SMPR3 SMP8 LL_ADC_SetChannelSamplingTime\n |
||
| 3837 | * SMPR3 SMP7 LL_ADC_SetChannelSamplingTime\n |
||
| 3838 | * SMPR3 SMP6 LL_ADC_SetChannelSamplingTime\n |
||
| 3839 | * SMPR3 SMP5 LL_ADC_SetChannelSamplingTime\n |
||
| 3840 | * SMPR3 SMP4 LL_ADC_SetChannelSamplingTime\n |
||
| 3841 | * SMPR3 SMP3 LL_ADC_SetChannelSamplingTime\n |
||
| 3842 | * SMPR3 SMP2 LL_ADC_SetChannelSamplingTime\n |
||
| 3843 | * SMPR3 SMP1 LL_ADC_SetChannelSamplingTime\n |
||
| 3844 | * SMPR3 SMP0 LL_ADC_SetChannelSamplingTime |
||
| 3845 | * @param ADCx ADC instance |
||
| 3846 | * @param Channel This parameter can be one of the following values: |
||
| 3847 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 3848 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 3849 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 3850 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 3851 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 3852 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 3853 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 3854 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 3855 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 3856 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 3857 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 3858 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 3859 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 3860 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 3861 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 3862 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 3863 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 3864 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 3865 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 3866 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 3867 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 3868 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 3869 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 3870 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 3871 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 3872 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 3873 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 3874 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 3875 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 3876 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 3877 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 3878 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 3879 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3) |
||
| 3880 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3) |
||
| 3881 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3) |
||
| 3882 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 3883 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 3884 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 3885 | * |
||
| 3886 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 3887 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 3888 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 3889 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 3890 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5 |
||
| 3891 | * @param SamplingTime This parameter can be one of the following values: |
||
| 3892 | * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES |
||
| 3893 | * @arg @ref LL_ADC_SAMPLINGTIME_9CYCLES |
||
| 3894 | * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES |
||
| 3895 | * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES |
||
| 3896 | * @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES |
||
| 3897 | * @arg @ref LL_ADC_SAMPLINGTIME_96CYCLES |
||
| 3898 | * @arg @ref LL_ADC_SAMPLINGTIME_192CYCLES |
||
| 3899 | * @arg @ref LL_ADC_SAMPLINGTIME_384CYCLES |
||
| 3900 | * @retval None |
||
| 3901 | */ |
||
| 3902 | __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) |
||
| 3903 | { |
||
| 3904 | /* Set bits with content of parameter "SamplingTime" with bits position */ |
||
| 3905 | /* in register and register position depending on parameter "Channel". */ |
||
| 3906 | /* Parameter "Channel" is used with masks because containing */ |
||
| 3907 | /* other bits reserved for other purpose. */ |
||
| 3908 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); |
||
| 3909 | |||
| 3910 | MODIFY_REG(*preg, |
||
| 3911 | ADC_SMPR3_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), |
||
| 3912 | SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); |
||
| 3913 | } |
||
| 3914 | |||
| 3915 | /** |
||
| 3916 | * @brief Get sampling time of the selected ADC channel |
||
| 3917 | * Unit: ADC clock cycles. |
||
| 3918 | * @note On this device, sampling time is on channel scope: independently |
||
| 3919 | * of channel mapped on ADC group regular or injected. |
||
| 3920 | * @note Conversion time is the addition of sampling time and processing time. |
||
| 3921 | * Refer to reference manual for ADC processing time of |
||
| 3922 | * this STM32 series. |
||
| 3923 | * @rmtoll SMPR0 SMP31 LL_ADC_GetChannelSamplingTime\n |
||
| 3924 | * SMPR0 SMP30 LL_ADC_GetChannelSamplingTime\n |
||
| 3925 | * SMPR1 SMP29 LL_ADC_GetChannelSamplingTime\n |
||
| 3926 | * SMPR1 SMP28 LL_ADC_GetChannelSamplingTime\n |
||
| 3927 | * SMPR1 SMP27 LL_ADC_GetChannelSamplingTime\n |
||
| 3928 | * SMPR1 SMP26 LL_ADC_GetChannelSamplingTime\n |
||
| 3929 | * SMPR1 SMP25 LL_ADC_GetChannelSamplingTime\n |
||
| 3930 | * SMPR1 SMP24 LL_ADC_GetChannelSamplingTime\n |
||
| 3931 | * SMPR1 SMP23 LL_ADC_GetChannelSamplingTime\n |
||
| 3932 | * SMPR1 SMP22 LL_ADC_GetChannelSamplingTime\n |
||
| 3933 | * SMPR1 SMP21 LL_ADC_GetChannelSamplingTime\n |
||
| 3934 | * SMPR1 SMP20 LL_ADC_GetChannelSamplingTime\n |
||
| 3935 | * SMPR2 SMP19 LL_ADC_GetChannelSamplingTime\n |
||
| 3936 | * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime\n |
||
| 3937 | * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n |
||
| 3938 | * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n |
||
| 3939 | * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n |
||
| 3940 | * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n |
||
| 3941 | * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n |
||
| 3942 | * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n |
||
| 3943 | * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n |
||
| 3944 | * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n |
||
| 3945 | * SMPR3 SMP9 LL_ADC_GetChannelSamplingTime\n |
||
| 3946 | * SMPR3 SMP8 LL_ADC_GetChannelSamplingTime\n |
||
| 3947 | * SMPR3 SMP7 LL_ADC_GetChannelSamplingTime\n |
||
| 3948 | * SMPR3 SMP6 LL_ADC_GetChannelSamplingTime\n |
||
| 3949 | * SMPR3 SMP5 LL_ADC_GetChannelSamplingTime\n |
||
| 3950 | * SMPR3 SMP4 LL_ADC_GetChannelSamplingTime\n |
||
| 3951 | * SMPR3 SMP3 LL_ADC_GetChannelSamplingTime\n |
||
| 3952 | * SMPR3 SMP2 LL_ADC_GetChannelSamplingTime\n |
||
| 3953 | * SMPR3 SMP1 LL_ADC_GetChannelSamplingTime\n |
||
| 3954 | * SMPR3 SMP0 LL_ADC_GetChannelSamplingTime |
||
| 3955 | * @param ADCx ADC instance |
||
| 3956 | * @param Channel This parameter can be one of the following values: |
||
| 3957 | * @arg @ref LL_ADC_CHANNEL_0 (2) |
||
| 3958 | * @arg @ref LL_ADC_CHANNEL_1 (2) |
||
| 3959 | * @arg @ref LL_ADC_CHANNEL_2 (2) |
||
| 3960 | * @arg @ref LL_ADC_CHANNEL_3 (2) |
||
| 3961 | * @arg @ref LL_ADC_CHANNEL_4 (1) |
||
| 3962 | * @arg @ref LL_ADC_CHANNEL_5 (1) |
||
| 3963 | * @arg @ref LL_ADC_CHANNEL_6 (2) |
||
| 3964 | * @arg @ref LL_ADC_CHANNEL_7 (2) |
||
| 3965 | * @arg @ref LL_ADC_CHANNEL_8 (2) |
||
| 3966 | * @arg @ref LL_ADC_CHANNEL_9 (2) |
||
| 3967 | * @arg @ref LL_ADC_CHANNEL_10 (2) |
||
| 3968 | * @arg @ref LL_ADC_CHANNEL_11 (2) |
||
| 3969 | * @arg @ref LL_ADC_CHANNEL_12 (2) |
||
| 3970 | * @arg @ref LL_ADC_CHANNEL_13 (3) |
||
| 3971 | * @arg @ref LL_ADC_CHANNEL_14 (3) |
||
| 3972 | * @arg @ref LL_ADC_CHANNEL_15 (3) |
||
| 3973 | * @arg @ref LL_ADC_CHANNEL_16 (3) |
||
| 3974 | * @arg @ref LL_ADC_CHANNEL_17 (3) |
||
| 3975 | * @arg @ref LL_ADC_CHANNEL_18 (3) |
||
| 3976 | * @arg @ref LL_ADC_CHANNEL_19 (3) |
||
| 3977 | * @arg @ref LL_ADC_CHANNEL_20 (3) |
||
| 3978 | * @arg @ref LL_ADC_CHANNEL_21 (3) |
||
| 3979 | * @arg @ref LL_ADC_CHANNEL_22 (1) |
||
| 3980 | * @arg @ref LL_ADC_CHANNEL_23 (1) |
||
| 3981 | * @arg @ref LL_ADC_CHANNEL_24 (1) |
||
| 3982 | * @arg @ref LL_ADC_CHANNEL_25 (1) |
||
| 3983 | * @arg @ref LL_ADC_CHANNEL_26 (3) |
||
| 3984 | * @arg @ref LL_ADC_CHANNEL_27 (3)(4) |
||
| 3985 | * @arg @ref LL_ADC_CHANNEL_28 (3)(4) |
||
| 3986 | * @arg @ref LL_ADC_CHANNEL_29 (3)(4) |
||
| 3987 | * @arg @ref LL_ADC_CHANNEL_30 (3)(4) |
||
| 3988 | * @arg @ref LL_ADC_CHANNEL_31 (3)(4) |
||
| 3989 | * @arg @ref LL_ADC_CHANNEL_VREFINT (3) |
||
| 3990 | * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3) |
||
| 3991 | * @arg @ref LL_ADC_CHANNEL_VCOMP (3) |
||
| 3992 | * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5) |
||
| 3993 | * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5) |
||
| 3994 | * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5) |
||
| 3995 | * |
||
| 3996 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 3997 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 3998 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 3999 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 4000 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5 |
||
| 4001 | * @retval Returned value can be one of the following values: |
||
| 4002 | * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES |
||
| 4003 | * @arg @ref LL_ADC_SAMPLINGTIME_9CYCLES |
||
| 4004 | * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES |
||
| 4005 | * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES |
||
| 4006 | * @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES |
||
| 4007 | * @arg @ref LL_ADC_SAMPLINGTIME_96CYCLES |
||
| 4008 | * @arg @ref LL_ADC_SAMPLINGTIME_192CYCLES |
||
| 4009 | * @arg @ref LL_ADC_SAMPLINGTIME_384CYCLES |
||
| 4010 | */ |
||
| 4011 | __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) |
||
| 4012 | { |
||
| 4013 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); |
||
| 4014 | |||
| 4015 | return (uint32_t)(READ_BIT(*preg, |
||
| 4016 | ADC_SMPR3_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) |
||
| 4017 | >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) |
||
| 4018 | ); |
||
| 4019 | } |
||
| 4020 | |||
| 4021 | #if defined(COMP_CSR_FCH3) |
||
| 4022 | /** |
||
| 4023 | * @brief Set ADC channels routing. |
||
| 4024 | * @note Channel routing set configuration between ADC IP and GPIO pads, |
||
| 4025 | * it is used to increase ADC channels speed (setting of |
||
| 4026 | * direct channel). |
||
| 4027 | * @note This feature is specific to STM32L1, on devices |
||
| 4028 | * category Cat.3, Cat.4, Cat.5. |
||
| 4029 | * To use this function, COMP RCC clock domain must be enabled. |
||
| 4030 | * Refer to @ref LL_APB1_GRP1_PERIPH_COMP. |
||
| 4031 | * @rmtoll CSR FCH3 LL_ADC_SetChannelRouting |
||
| 4032 | * @rmtoll CSR FCH8 LL_ADC_SetChannelRouting |
||
| 4033 | * @rmtoll CSR RCH13 LL_ADC_SetChannelRouting |
||
| 4034 | * @param ADCx ADC instance |
||
| 4035 | * @param Channel This parameter can be one of the following values: |
||
| 4036 | * @arg @ref LL_ADC_CHANNEL_3_ROUTING (1) |
||
| 4037 | * @arg @ref LL_ADC_CHANNEL_8_ROUTING (2) |
||
| 4038 | * @arg @ref LL_ADC_CHANNEL_13_ROUTING (3) |
||
| 4039 | * |
||
| 4040 | * (1) Used as ADC direct channel (fast channel) if OPAMP1 is |
||
| 4041 | * in power down mode.\n |
||
| 4042 | * (2) Used as ADC direct channel (fast channel) if OPAMP2 is |
||
| 4043 | * in power down mode.\n |
||
| 4044 | * (3) Used as ADC re-routed channel if OPAMP3 is |
||
| 4045 | * in power down mode. |
||
| 4046 | * Otherwise, channel 13 is connected to OPAMP3 output and routed |
||
| 4047 | * through switches COMP1_SW1 and VCOMP to ADC switch matrix. |
||
| 4048 | * (Note: OPAMP3 is available on STM32L1 Cat.4 only). |
||
| 4049 | * @param Routing This parameter can be one of the following values: |
||
| 4050 | * @arg @ref LL_ADC_CHANNEL_ROUTING_DEFAULT |
||
| 4051 | * @arg @ref LL_ADC_CHANNEL_ROUTING_DIRECT |
||
| 4052 | */ |
||
| 4053 | __STATIC_INLINE void LL_ADC_SetChannelRouting(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t Routing) |
||
| 4054 | { |
||
| 4055 | /* Note: Bit is located in comparator IP, but dedicated to ADC */ |
||
| 4056 | MODIFY_REG(COMP->CSR, Channel, (Routing << POSITION_VAL(Channel))); |
||
| 4057 | } |
||
| 4058 | |||
| 4059 | /** |
||
| 4060 | * @brief Get ADC channels speed. |
||
| 4061 | * @note Channel routing set configuration between ADC IP and GPIO pads, |
||
| 4062 | * it is used to increase ADC channels speed (setting of |
||
| 4063 | * direct channel). |
||
| 4064 | * @note This feature is specific to STM32L1, on devices |
||
| 4065 | * category Cat.3, Cat.4, Cat.5. |
||
| 4066 | * To use this function, COMP RCC clock domain must be enabled. |
||
| 4067 | * Refer to @ref LL_APB1_GRP1_PERIPH_COMP. |
||
| 4068 | * @rmtoll CSR FCH3 LL_ADC_GetChannelRouting |
||
| 4069 | * @rmtoll CSR FCH8 LL_ADC_GetChannelRouting |
||
| 4070 | * @rmtoll CSR RCH13 LL_ADC_GetChannelRouting |
||
| 4071 | * @param ADCx ADC instance |
||
| 4072 | * @param Channel This parameter can be one of the following values: |
||
| 4073 | * @arg @ref LL_ADC_CHANNEL_3_ROUTING (1) |
||
| 4074 | * @arg @ref LL_ADC_CHANNEL_8_ROUTING (2) |
||
| 4075 | * @arg @ref LL_ADC_CHANNEL_13_ROUTING (3) |
||
| 4076 | * |
||
| 4077 | * (1) Used as ADC direct channel (fast channel) if OPAMP1 is |
||
| 4078 | * in power down mode.\n |
||
| 4079 | * (2) Used as ADC direct channel (fast channel) if OPAMP2 is |
||
| 4080 | * in power down mode.\n |
||
| 4081 | * (3) Used as ADC re-routed channel if OPAMP3 is |
||
| 4082 | * in power down mode. |
||
| 4083 | * Otherwise, channel 13 is connected to OPAMP3 output and routed |
||
| 4084 | * through switches COMP1_SW1 and VCOMP to ADC switch matrix. |
||
| 4085 | * (Note: OPAMP3 is available on STM32L1 Cat.4 only). |
||
| 4086 | * @retval Returned value can be one of the following values: |
||
| 4087 | * @arg @ref LL_ADC_CHANNEL_ROUTING_DEFAULT |
||
| 4088 | * @arg @ref LL_ADC_CHANNEL_ROUTING_DIRECT |
||
| 4089 | */ |
||
| 4090 | __STATIC_INLINE uint32_t LL_ADC_GetChannelRouting(ADC_TypeDef *ADCx, uint32_t Channel) |
||
| 4091 | { |
||
| 4092 | /* Note: Bit is located in comparator IP, but dedicated to ADC */ |
||
| 4093 | return (uint32_t)(READ_BIT(COMP->CSR, Channel) >> POSITION_VAL(Channel)); |
||
| 4094 | } |
||
| 4095 | #endif |
||
| 4096 | |||
| 4097 | /** |
||
| 4098 | * @} |
||
| 4099 | */ |
||
| 4100 | |||
| 4101 | /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog |
||
| 4102 | * @{ |
||
| 4103 | */ |
||
| 4104 | |||
| 4105 | /** |
||
| 4106 | * @brief Set ADC analog watchdog monitored channels: |
||
| 4107 | * a single channel or all channels, |
||
| 4108 | * on ADC groups regular and-or injected. |
||
| 4109 | * @note Once monitored channels are selected, analog watchdog |
||
| 4110 | * is enabled. |
||
| 4111 | * @note In case of need to define a single channel to monitor |
||
| 4112 | * with analog watchdog from sequencer channel definition, |
||
| 4113 | * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). |
||
| 4114 | * @note On this STM32 series, there is only 1 kind of analog watchdog |
||
| 4115 | * instance: |
||
| 4116 | * - AWD standard (instance AWD1): |
||
| 4117 | * - channels monitored: can monitor 1 channel or all channels. |
||
| 4118 | * - groups monitored: ADC groups regular and-or injected. |
||
| 4119 | * - resolution: resolution is not limited (corresponds to |
||
| 4120 | * ADC resolution configured). |
||
| 4121 | * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n |
||
| 4122 | * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n |
||
| 4123 | * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels |
||
| 4124 | * @param ADCx ADC instance |
||
| 4125 | * @param AWDChannelGroup This parameter can be one of the following values: |
||
| 4126 | * @arg @ref LL_ADC_AWD_DISABLE |
||
| 4127 | * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG |
||
| 4128 | * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ |
||
| 4129 | * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ |
||
| 4130 | * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (2) |
||
| 4131 | * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (2) |
||
| 4132 | * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (2) |
||
| 4133 | * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (2) |
||
| 4134 | * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (2) |
||
| 4135 | * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (2) |
||
| 4136 | * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (2) |
||
| 4137 | * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (2) |
||
| 4138 | * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (2) |
||
| 4139 | * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (2) |
||
| 4140 | * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (2) |
||
| 4141 | * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (2) |
||
| 4142 | * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (1) |
||
| 4143 | * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (1) |
||
| 4144 | * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1) |
||
| 4145 | * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (1) |
||
| 4146 | * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (1) |
||
| 4147 | * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1) |
||
| 4148 | * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (2) |
||
| 4149 | * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (2) |
||
| 4150 | * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (2) |
||
| 4151 | * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (2) |
||
| 4152 | * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (2) |
||
| 4153 | * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (2) |
||
| 4154 | * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (2) |
||
| 4155 | * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (2) |
||
| 4156 | * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (2) |
||
| 4157 | * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (2) |
||
| 4158 | * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (2) |
||
| 4159 | * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (2) |
||
| 4160 | * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (2) |
||
| 4161 | * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (2) |
||
| 4162 | * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (2) |
||
| 4163 | * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (2) |
||
| 4164 | * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (2) |
||
| 4165 | * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (2) |
||
| 4166 | * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (2) |
||
| 4167 | * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (2) |
||
| 4168 | * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (2) |
||
| 4169 | * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (3) |
||
| 4170 | * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (3) |
||
| 4171 | * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (3) |
||
| 4172 | * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (3) |
||
| 4173 | * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (3) |
||
| 4174 | * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (3) |
||
| 4175 | * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (3) |
||
| 4176 | * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (3) |
||
| 4177 | * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (3) |
||
| 4178 | * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (3) |
||
| 4179 | * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (3) |
||
| 4180 | * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (3) |
||
| 4181 | * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (3) |
||
| 4182 | * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (3) |
||
| 4183 | * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (3) |
||
| 4184 | * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (3) |
||
| 4185 | * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (3) |
||
| 4186 | * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (3) |
||
| 4187 | * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (3) |
||
| 4188 | * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (3) |
||
| 4189 | * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ (3) |
||
| 4190 | * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (3) |
||
| 4191 | * @arg @ref LL_ADC_AWD_CHANNEL_20_INJ (3) |
||
| 4192 | * @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ (3) |
||
| 4193 | * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (3) |
||
| 4194 | * @arg @ref LL_ADC_AWD_CHANNEL_21_INJ (3) |
||
| 4195 | * @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ (3) |
||
| 4196 | * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1) |
||
| 4197 | * @arg @ref LL_ADC_AWD_CHANNEL_22_INJ (1) |
||
| 4198 | * @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ (1) |
||
| 4199 | * @arg @ref LL_ADC_AWD_CHANNEL_23_REG (1) |
||
| 4200 | * @arg @ref LL_ADC_AWD_CHANNEL_23_INJ (1) |
||
| 4201 | * @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ (1) |
||
| 4202 | * @arg @ref LL_ADC_AWD_CHANNEL_24_REG (1) |
||
| 4203 | * @arg @ref LL_ADC_AWD_CHANNEL_24_INJ (1) |
||
| 4204 | * @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ (1) |
||
| 4205 | * @arg @ref LL_ADC_AWD_CHANNEL_25_REG (1) |
||
| 4206 | * @arg @ref LL_ADC_AWD_CHANNEL_25_INJ (1) |
||
| 4207 | * @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ (1) |
||
| 4208 | * @arg @ref LL_ADC_AWD_CHANNEL_26_REG (3) |
||
| 4209 | * @arg @ref LL_ADC_AWD_CHANNEL_26_INJ (3) |
||
| 4210 | * @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ (3) |
||
| 4211 | * @arg @ref LL_ADC_AWD_CHANNEL_27_REG (3)(4) |
||
| 4212 | * @arg @ref LL_ADC_AWD_CHANNEL_27_INJ (3)(4) |
||
| 4213 | * @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ (3)(4) |
||
| 4214 | * @arg @ref LL_ADC_AWD_CHANNEL_28_REG (3)(4) |
||
| 4215 | * @arg @ref LL_ADC_AWD_CHANNEL_28_INJ (3)(4) |
||
| 4216 | * @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ (3)(4) |
||
| 4217 | * @arg @ref LL_ADC_AWD_CHANNEL_29_REG (3)(4) |
||
| 4218 | * @arg @ref LL_ADC_AWD_CHANNEL_29_INJ (3)(4) |
||
| 4219 | * @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ (3)(4) |
||
| 4220 | * @arg @ref LL_ADC_AWD_CHANNEL_30_REG (3)(4) |
||
| 4221 | * @arg @ref LL_ADC_AWD_CHANNEL_30_INJ (3)(4) |
||
| 4222 | * @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ (3)(4) |
||
| 4223 | * @arg @ref LL_ADC_AWD_CHANNEL_31_REG (3)(4) |
||
| 4224 | * @arg @ref LL_ADC_AWD_CHANNEL_31_INJ (3)(4) |
||
| 4225 | * @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ (3)(4) |
||
| 4226 | * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (3) |
||
| 4227 | * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (3) |
||
| 4228 | * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (3) |
||
| 4229 | * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (3) |
||
| 4230 | * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (3) |
||
| 4231 | * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (3) |
||
| 4232 | * @arg @ref LL_ADC_AWD_CH_VCOMP_REG (3) |
||
| 4233 | * @arg @ref LL_ADC_AWD_CH_VCOMP_INJ (3) |
||
| 4234 | * @arg @ref LL_ADC_AWD_CH_VCOMP_REG_INJ (3) |
||
| 4235 | * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (3)(5) |
||
| 4236 | * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (3)(5) |
||
| 4237 | * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (3)(5) |
||
| 4238 | * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (3)(5) |
||
| 4239 | * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (3)(5) |
||
| 4240 | * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (3)(5) |
||
| 4241 | * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (3)(5) |
||
| 4242 | * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (3)(5) |
||
| 4243 | * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)(5) |
||
| 4244 | * |
||
| 4245 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 4246 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 4247 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 4248 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n |
||
| 4249 | * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5 |
||
| 4250 | * @retval None |
||
| 4251 | */ |
||
| 4252 | __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) |
||
| 4253 | { |
||
| 4254 | MODIFY_REG(ADCx->CR1, |
||
| 4255 | (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), |
||
| 4256 | AWDChannelGroup); |
||
| 4257 | } |
||
| 4258 | |||
| 4259 | /** |
||
| 4260 | * @brief Get ADC analog watchdog monitored channel. |
||
| 4261 | * @note Usage of the returned channel number: |
||
| 4262 | * - To reinject this channel into another function LL_ADC_xxx: |
||
| 4263 | * the returned channel number is only partly formatted on definition |
||
| 4264 | * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared |
||
| 4265 | * with parts of literals LL_ADC_CHANNEL_x or using |
||
| 4266 | * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). |
||
| 4267 | * Then the selected literal LL_ADC_CHANNEL_x can be used |
||
| 4268 | * as parameter for another function. |
||
| 4269 | * - To get the channel number in decimal format: |
||
| 4270 | * process the returned value with the helper macro |
||
| 4271 | * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). |
||
| 4272 | * Applicable only when the analog watchdog is set to monitor |
||
| 4273 | * one channel. |
||
| 4274 | * @note On this STM32 series, there is only 1 kind of analog watchdog |
||
| 4275 | * instance: |
||
| 4276 | * - AWD standard (instance AWD1): |
||
| 4277 | * - channels monitored: can monitor 1 channel or all channels. |
||
| 4278 | * - groups monitored: ADC groups regular and-or injected. |
||
| 4279 | * - resolution: resolution is not limited (corresponds to |
||
| 4280 | * ADC resolution configured). |
||
| 4281 | * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n |
||
| 4282 | * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n |
||
| 4283 | * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels |
||
| 4284 | * @param ADCx ADC instance |
||
| 4285 | * @retval Returned value can be one of the following values: |
||
| 4286 | * @arg @ref LL_ADC_AWD_DISABLE |
||
| 4287 | * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG |
||
| 4288 | * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ |
||
| 4289 | * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ |
||
| 4290 | * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (2) |
||
| 4291 | * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (2) |
||
| 4292 | * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (2) |
||
| 4293 | * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (2) |
||
| 4294 | * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (2) |
||
| 4295 | * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (2) |
||
| 4296 | * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (2) |
||
| 4297 | * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (2) |
||
| 4298 | * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (2) |
||
| 4299 | * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (2) |
||
| 4300 | * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (2) |
||
| 4301 | * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (2) |
||
| 4302 | * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (1) |
||
| 4303 | * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (1) |
||
| 4304 | * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1) |
||
| 4305 | * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (1) |
||
| 4306 | * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (1) |
||
| 4307 | * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1) |
||
| 4308 | * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (2) |
||
| 4309 | * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (2) |
||
| 4310 | * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (2) |
||
| 4311 | * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (2) |
||
| 4312 | * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (2) |
||
| 4313 | * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (2) |
||
| 4314 | * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (2) |
||
| 4315 | * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (2) |
||
| 4316 | * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (2) |
||
| 4317 | * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (2) |
||
| 4318 | * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (2) |
||
| 4319 | * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (2) |
||
| 4320 | * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (2) |
||
| 4321 | * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (2) |
||
| 4322 | * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (2) |
||
| 4323 | * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (2) |
||
| 4324 | * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (2) |
||
| 4325 | * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (2) |
||
| 4326 | * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (2) |
||
| 4327 | * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (2) |
||
| 4328 | * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (2) |
||
| 4329 | * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (3) |
||
| 4330 | * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (3) |
||
| 4331 | * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (3) |
||
| 4332 | * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (3) |
||
| 4333 | * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (3) |
||
| 4334 | * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (3) |
||
| 4335 | * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (3) |
||
| 4336 | * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (3) |
||
| 4337 | * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (3) |
||
| 4338 | * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (3) |
||
| 4339 | * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (3) |
||
| 4340 | * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (3) |
||
| 4341 | * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (3) |
||
| 4342 | * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (3) |
||
| 4343 | * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (3) |
||
| 4344 | * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (3) |
||
| 4345 | * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (3) |
||
| 4346 | * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (3) |
||
| 4347 | * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (3) |
||
| 4348 | * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (3) |
||
| 4349 | * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ (3) |
||
| 4350 | * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (3) |
||
| 4351 | * @arg @ref LL_ADC_AWD_CHANNEL_20_INJ (3) |
||
| 4352 | * @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ (3) |
||
| 4353 | * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (3) |
||
| 4354 | * @arg @ref LL_ADC_AWD_CHANNEL_21_INJ (3) |
||
| 4355 | * @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ (3) |
||
| 4356 | * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1) |
||
| 4357 | * @arg @ref LL_ADC_AWD_CHANNEL_22_INJ (1) |
||
| 4358 | * @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ (1) |
||
| 4359 | * @arg @ref LL_ADC_AWD_CHANNEL_23_REG (1) |
||
| 4360 | * @arg @ref LL_ADC_AWD_CHANNEL_23_INJ (1) |
||
| 4361 | * @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ (1) |
||
| 4362 | * @arg @ref LL_ADC_AWD_CHANNEL_24_REG (1) |
||
| 4363 | * @arg @ref LL_ADC_AWD_CHANNEL_24_INJ (1) |
||
| 4364 | * @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ (1) |
||
| 4365 | * @arg @ref LL_ADC_AWD_CHANNEL_25_REG (1) |
||
| 4366 | * @arg @ref LL_ADC_AWD_CHANNEL_25_INJ (1) |
||
| 4367 | * @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ (1) |
||
| 4368 | * @arg @ref LL_ADC_AWD_CHANNEL_26_REG (3) |
||
| 4369 | * @arg @ref LL_ADC_AWD_CHANNEL_26_INJ (3) |
||
| 4370 | * @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ (3) |
||
| 4371 | * @arg @ref LL_ADC_AWD_CHANNEL_27_REG (3)(4) |
||
| 4372 | * @arg @ref LL_ADC_AWD_CHANNEL_27_INJ (3)(4) |
||
| 4373 | * @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ (3)(4) |
||
| 4374 | * @arg @ref LL_ADC_AWD_CHANNEL_28_REG (3)(4) |
||
| 4375 | * @arg @ref LL_ADC_AWD_CHANNEL_28_INJ (3)(4) |
||
| 4376 | * @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ (3)(4) |
||
| 4377 | * @arg @ref LL_ADC_AWD_CHANNEL_29_REG (3)(4) |
||
| 4378 | * @arg @ref LL_ADC_AWD_CHANNEL_29_INJ (3)(4) |
||
| 4379 | * @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ (3)(4) |
||
| 4380 | * @arg @ref LL_ADC_AWD_CHANNEL_30_REG (3)(4) |
||
| 4381 | * @arg @ref LL_ADC_AWD_CHANNEL_30_INJ (3)(4) |
||
| 4382 | * @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ (3)(4) |
||
| 4383 | * @arg @ref LL_ADC_AWD_CHANNEL_31_REG (3)(4) |
||
| 4384 | * @arg @ref LL_ADC_AWD_CHANNEL_31_INJ (3)(4) |
||
| 4385 | * @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ (3)(4) |
||
| 4386 | * |
||
| 4387 | * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n |
||
| 4388 | * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n |
||
| 4389 | * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n |
||
| 4390 | * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. |
||
| 4391 | */ |
||
| 4392 | __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) |
||
| 4393 | { |
||
| 4394 | return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); |
||
| 4395 | } |
||
| 4396 | |||
| 4397 | /** |
||
| 4398 | * @brief Set ADC analog watchdog threshold value of threshold |
||
| 4399 | * high or low. |
||
| 4400 | * @note In case of ADC resolution different of 12 bits, |
||
| 4401 | * analog watchdog thresholds data require a specific shift. |
||
| 4402 | * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). |
||
| 4403 | * @note On this STM32 series, there is only 1 kind of analog watchdog |
||
| 4404 | * instance: |
||
| 4405 | * - AWD standard (instance AWD1): |
||
| 4406 | * - channels monitored: can monitor 1 channel or all channels. |
||
| 4407 | * - groups monitored: ADC groups regular and-or injected. |
||
| 4408 | * - resolution: resolution is not limited (corresponds to |
||
| 4409 | * ADC resolution configured). |
||
| 4410 | * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n |
||
| 4411 | * LTR LT LL_ADC_SetAnalogWDThresholds |
||
| 4412 | * @param ADCx ADC instance |
||
| 4413 | * @param AWDThresholdsHighLow This parameter can be one of the following values: |
||
| 4414 | * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH |
||
| 4415 | * @arg @ref LL_ADC_AWD_THRESHOLD_LOW |
||
| 4416 | * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 4417 | * @retval None |
||
| 4418 | */ |
||
| 4419 | __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) |
||
| 4420 | { |
||
| 4421 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); |
||
| 4422 | |||
| 4423 | MODIFY_REG(*preg, |
||
| 4424 | ADC_HTR_HT, |
||
| 4425 | AWDThresholdValue); |
||
| 4426 | } |
||
| 4427 | |||
| 4428 | /** |
||
| 4429 | * @brief Get ADC analog watchdog threshold value of threshold high or |
||
| 4430 | * threshold low. |
||
| 4431 | * @note In case of ADC resolution different of 12 bits, |
||
| 4432 | * analog watchdog thresholds data require a specific shift. |
||
| 4433 | * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). |
||
| 4434 | * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n |
||
| 4435 | * LTR LT LL_ADC_GetAnalogWDThresholds |
||
| 4436 | * @param ADCx ADC instance |
||
| 4437 | * @param AWDThresholdsHighLow This parameter can be one of the following values: |
||
| 4438 | * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH |
||
| 4439 | * @arg @ref LL_ADC_AWD_THRESHOLD_LOW |
||
| 4440 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 4441 | */ |
||
| 4442 | __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) |
||
| 4443 | { |
||
| 4444 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); |
||
| 4445 | |||
| 4446 | return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); |
||
| 4447 | } |
||
| 4448 | |||
| 4449 | /** |
||
| 4450 | * @} |
||
| 4451 | */ |
||
| 4452 | |||
| 4453 | /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance |
||
| 4454 | * @{ |
||
| 4455 | */ |
||
| 4456 | |||
| 4457 | /** |
||
| 4458 | * @brief Enable the selected ADC instance. |
||
| 4459 | * @note On this STM32 series, after ADC enable, a delay for |
||
| 4460 | * ADC internal analog stabilization is required before performing a |
||
| 4461 | * ADC conversion start. |
||
| 4462 | * Refer to device datasheet, parameter tSTAB. |
||
| 4463 | * @note Due to the latency introduced by the synchronization between |
||
| 4464 | * two clock domains (ADC clock source asynchronous), |
||
| 4465 | * some hardware constraints must be respected: |
||
| 4466 | * - ADC must be enabled (@ref LL_ADC_Enable() ) only |
||
| 4467 | * when ADC is not ready to convert. |
||
| 4468 | * - ADC must be disabled (@ref LL_ADC_Disable() ) only |
||
| 4469 | * when ADC is ready to convert. |
||
| 4470 | * Status of ADC ready to convert can be checked using function |
||
| 4471 | * @ref LL_ADC_IsActiveFlag_ADRDY(). |
||
| 4472 | * @rmtoll CR2 ADON LL_ADC_Enable |
||
| 4473 | * @param ADCx ADC instance |
||
| 4474 | * @retval None |
||
| 4475 | */ |
||
| 4476 | __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) |
||
| 4477 | { |
||
| 4478 | SET_BIT(ADCx->CR2, ADC_CR2_ADON); |
||
| 4479 | } |
||
| 4480 | |||
| 4481 | /** |
||
| 4482 | * @brief Disable the selected ADC instance. |
||
| 4483 | * @note Due to the latency introduced by the synchronization between |
||
| 4484 | * two clock domains (ADC clock source asynchronous), |
||
| 4485 | * some hardware constraints must be respected: |
||
| 4486 | * - ADC must be enabled (@ref LL_ADC_Enable() ) only |
||
| 4487 | * when ADC is not ready to convert. |
||
| 4488 | * - ADC must be disabled (@ref LL_ADC_Disable() ) only |
||
| 4489 | * when ADC is ready to convert. |
||
| 4490 | * Status of ADC ready to convert can be checked using function |
||
| 4491 | * @ref LL_ADC_IsActiveFlag_ADRDY(). |
||
| 4492 | * @rmtoll CR2 ADON LL_ADC_Disable |
||
| 4493 | * @param ADCx ADC instance |
||
| 4494 | * @retval None |
||
| 4495 | */ |
||
| 4496 | __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) |
||
| 4497 | { |
||
| 4498 | CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); |
||
| 4499 | } |
||
| 4500 | |||
| 4501 | /** |
||
| 4502 | * @brief Get the selected ADC instance enable state. |
||
| 4503 | * @rmtoll CR2 ADON LL_ADC_IsEnabled |
||
| 4504 | * @param ADCx ADC instance |
||
| 4505 | * @retval 0: ADC is disabled, 1: ADC is enabled. |
||
| 4506 | */ |
||
| 4507 | __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) |
||
| 4508 | { |
||
| 4509 | return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); |
||
| 4510 | } |
||
| 4511 | |||
| 4512 | /** |
||
| 4513 | * @} |
||
| 4514 | */ |
||
| 4515 | |||
| 4516 | /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular |
||
| 4517 | * @{ |
||
| 4518 | */ |
||
| 4519 | |||
| 4520 | /** |
||
| 4521 | * @brief Start ADC group regular conversion. |
||
| 4522 | * @note On this STM32 series, this function is relevant only for |
||
| 4523 | * internal trigger (SW start), not for external trigger: |
||
| 4524 | * - If ADC trigger has been set to software start, ADC conversion |
||
| 4525 | * starts immediately. |
||
| 4526 | * - If ADC trigger has been set to external trigger, ADC conversion |
||
| 4527 | * start must be performed using function |
||
| 4528 | * @ref LL_ADC_REG_StartConversionExtTrig(). |
||
| 4529 | * (if external trigger edge would have been set during ADC other |
||
| 4530 | * settings, ADC conversion would start at trigger event |
||
| 4531 | * as soon as ADC is enabled). |
||
| 4532 | * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart |
||
| 4533 | * @param ADCx ADC instance |
||
| 4534 | * @retval None |
||
| 4535 | */ |
||
| 4536 | __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) |
||
| 4537 | { |
||
| 4538 | SET_BIT(ADCx->CR2, ADC_CR2_SWSTART); |
||
| 4539 | } |
||
| 4540 | |||
| 4541 | /** |
||
| 4542 | * @brief Start ADC group regular conversion from external trigger. |
||
| 4543 | * @note ADC conversion will start at next trigger event (on the selected |
||
| 4544 | * trigger edge) following the ADC start conversion command. |
||
| 4545 | * @note On this STM32 series, this function is relevant for |
||
| 4546 | * ADC conversion start from external trigger. |
||
| 4547 | * If internal trigger (SW start) is needed, perform ADC conversion |
||
| 4548 | * start using function @ref LL_ADC_REG_StartConversionSWStart(). |
||
| 4549 | * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig |
||
| 4550 | * @param ExternalTriggerEdge This parameter can be one of the following values: |
||
| 4551 | * @arg @ref LL_ADC_REG_TRIG_EXT_RISING |
||
| 4552 | * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING |
||
| 4553 | * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING |
||
| 4554 | * @param ADCx ADC instance |
||
| 4555 | * @retval None |
||
| 4556 | */ |
||
| 4557 | __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) |
||
| 4558 | { |
||
| 4559 | SET_BIT(ADCx->CR2, ExternalTriggerEdge); |
||
| 4560 | } |
||
| 4561 | |||
| 4562 | /** |
||
| 4563 | * @brief Stop ADC group regular conversion from external trigger. |
||
| 4564 | * @note No more ADC conversion will start at next trigger event |
||
| 4565 | * following the ADC stop conversion command. |
||
| 4566 | * If a conversion is on-going, it will be completed. |
||
| 4567 | * @note On this STM32 series, there is no specific command |
||
| 4568 | * to stop a conversion on-going or to stop ADC converting |
||
| 4569 | * in continuous mode. These actions can be performed |
||
| 4570 | * using function @ref LL_ADC_Disable(). |
||
| 4571 | * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig |
||
| 4572 | * @param ADCx ADC instance |
||
| 4573 | * @retval None |
||
| 4574 | */ |
||
| 4575 | __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) |
||
| 4576 | { |
||
| 4577 | CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN); |
||
| 4578 | } |
||
| 4579 | |||
| 4580 | /** |
||
| 4581 | * @brief Get ADC group regular conversion data, range fit for |
||
| 4582 | * all ADC configurations: all ADC resolutions and |
||
| 4583 | * all oversampling increased data width (for devices |
||
| 4584 | * with feature oversampling). |
||
| 4585 | * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 |
||
| 4586 | * @param ADCx ADC instance |
||
| 4587 | * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF |
||
| 4588 | */ |
||
| 4589 | __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) |
||
| 4590 | { |
||
| 4591 | return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); |
||
| 4592 | } |
||
| 4593 | |||
| 4594 | /** |
||
| 4595 | * @brief Get ADC group regular conversion data, range fit for |
||
| 4596 | * ADC resolution 12 bits. |
||
| 4597 | * @note For devices with feature oversampling: Oversampling |
||
| 4598 | * can increase data width, function for extended range |
||
| 4599 | * may be needed: @ref LL_ADC_REG_ReadConversionData32. |
||
| 4600 | * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 |
||
| 4601 | * @param ADCx ADC instance |
||
| 4602 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 4603 | */ |
||
| 4604 | __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) |
||
| 4605 | { |
||
| 4606 | return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); |
||
| 4607 | } |
||
| 4608 | |||
| 4609 | /** |
||
| 4610 | * @brief Get ADC group regular conversion data, range fit for |
||
| 4611 | * ADC resolution 10 bits. |
||
| 4612 | * @note For devices with feature oversampling: Oversampling |
||
| 4613 | * can increase data width, function for extended range |
||
| 4614 | * may be needed: @ref LL_ADC_REG_ReadConversionData32. |
||
| 4615 | * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 |
||
| 4616 | * @param ADCx ADC instance |
||
| 4617 | * @retval Value between Min_Data=0x000 and Max_Data=0x3FF |
||
| 4618 | */ |
||
| 4619 | __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) |
||
| 4620 | { |
||
| 4621 | return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); |
||
| 4622 | } |
||
| 4623 | |||
| 4624 | /** |
||
| 4625 | * @brief Get ADC group regular conversion data, range fit for |
||
| 4626 | * ADC resolution 8 bits. |
||
| 4627 | * @note For devices with feature oversampling: Oversampling |
||
| 4628 | * can increase data width, function for extended range |
||
| 4629 | * may be needed: @ref LL_ADC_REG_ReadConversionData32. |
||
| 4630 | * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 |
||
| 4631 | * @param ADCx ADC instance |
||
| 4632 | * @retval Value between Min_Data=0x00 and Max_Data=0xFF |
||
| 4633 | */ |
||
| 4634 | __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) |
||
| 4635 | { |
||
| 4636 | return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); |
||
| 4637 | } |
||
| 4638 | |||
| 4639 | /** |
||
| 4640 | * @brief Get ADC group regular conversion data, range fit for |
||
| 4641 | * ADC resolution 6 bits. |
||
| 4642 | * @note For devices with feature oversampling: Oversampling |
||
| 4643 | * can increase data width, function for extended range |
||
| 4644 | * may be needed: @ref LL_ADC_REG_ReadConversionData32. |
||
| 4645 | * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 |
||
| 4646 | * @param ADCx ADC instance |
||
| 4647 | * @retval Value between Min_Data=0x00 and Max_Data=0x3F |
||
| 4648 | */ |
||
| 4649 | __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) |
||
| 4650 | { |
||
| 4651 | return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); |
||
| 4652 | } |
||
| 4653 | |||
| 4654 | /** |
||
| 4655 | * @} |
||
| 4656 | */ |
||
| 4657 | |||
| 4658 | /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected |
||
| 4659 | * @{ |
||
| 4660 | */ |
||
| 4661 | |||
| 4662 | /** |
||
| 4663 | * @brief Start ADC group injected conversion. |
||
| 4664 | * @note On this STM32 series, this function is relevant only for |
||
| 4665 | * internal trigger (SW start), not for external trigger: |
||
| 4666 | * - If ADC trigger has been set to software start, ADC conversion |
||
| 4667 | * starts immediately. |
||
| 4668 | * - If ADC trigger has been set to external trigger, ADC conversion |
||
| 4669 | * start must be performed using function |
||
| 4670 | * @ref LL_ADC_INJ_StartConversionExtTrig(). |
||
| 4671 | * (if external trigger edge would have been set during ADC other |
||
| 4672 | * settings, ADC conversion would start at trigger event |
||
| 4673 | * as soon as ADC is enabled). |
||
| 4674 | * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart |
||
| 4675 | * @param ADCx ADC instance |
||
| 4676 | * @retval None |
||
| 4677 | */ |
||
| 4678 | __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) |
||
| 4679 | { |
||
| 4680 | SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART); |
||
| 4681 | } |
||
| 4682 | |||
| 4683 | /** |
||
| 4684 | * @brief Start ADC group injected conversion from external trigger. |
||
| 4685 | * @note ADC conversion will start at next trigger event (on the selected |
||
| 4686 | * trigger edge) following the ADC start conversion command. |
||
| 4687 | * @note On this STM32 series, this function is relevant for |
||
| 4688 | * ADC conversion start from external trigger. |
||
| 4689 | * If internal trigger (SW start) is needed, perform ADC conversion |
||
| 4690 | * start using function @ref LL_ADC_INJ_StartConversionSWStart(). |
||
| 4691 | * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig |
||
| 4692 | * @param ExternalTriggerEdge This parameter can be one of the following values: |
||
| 4693 | * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING |
||
| 4694 | * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING |
||
| 4695 | * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING |
||
| 4696 | * @param ADCx ADC instance |
||
| 4697 | * @retval None |
||
| 4698 | */ |
||
| 4699 | __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) |
||
| 4700 | { |
||
| 4701 | SET_BIT(ADCx->CR2, ExternalTriggerEdge); |
||
| 4702 | } |
||
| 4703 | |||
| 4704 | /** |
||
| 4705 | * @brief Stop ADC group injected conversion from external trigger. |
||
| 4706 | * @note No more ADC conversion will start at next trigger event |
||
| 4707 | * following the ADC stop conversion command. |
||
| 4708 | * If a conversion is on-going, it will be completed. |
||
| 4709 | * @note On this STM32 series, there is no specific command |
||
| 4710 | * to stop a conversion on-going or to stop ADC converting |
||
| 4711 | * in continuous mode. These actions can be performed |
||
| 4712 | * using function @ref LL_ADC_Disable(). |
||
| 4713 | * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig |
||
| 4714 | * @param ADCx ADC instance |
||
| 4715 | * @retval None |
||
| 4716 | */ |
||
| 4717 | __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) |
||
| 4718 | { |
||
| 4719 | CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN); |
||
| 4720 | } |
||
| 4721 | |||
| 4722 | /** |
||
| 4723 | * @brief Get ADC group regular conversion data, range fit for |
||
| 4724 | * all ADC configurations: all ADC resolutions and |
||
| 4725 | * all oversampling increased data width (for devices |
||
| 4726 | * with feature oversampling). |
||
| 4727 | * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n |
||
| 4728 | * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n |
||
| 4729 | * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n |
||
| 4730 | * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 |
||
| 4731 | * @param ADCx ADC instance |
||
| 4732 | * @param Rank This parameter can be one of the following values: |
||
| 4733 | * @arg @ref LL_ADC_INJ_RANK_1 |
||
| 4734 | * @arg @ref LL_ADC_INJ_RANK_2 |
||
| 4735 | * @arg @ref LL_ADC_INJ_RANK_3 |
||
| 4736 | * @arg @ref LL_ADC_INJ_RANK_4 |
||
| 4737 | * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF |
||
| 4738 | */ |
||
| 4739 | __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) |
||
| 4740 | { |
||
| 4741 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); |
||
| 4742 | |||
| 4743 | return (uint32_t)(READ_BIT(*preg, |
||
| 4744 | ADC_JDR1_JDATA) |
||
| 4745 | ); |
||
| 4746 | } |
||
| 4747 | |||
| 4748 | /** |
||
| 4749 | * @brief Get ADC group injected conversion data, range fit for |
||
| 4750 | * ADC resolution 12 bits. |
||
| 4751 | * @note For devices with feature oversampling: Oversampling |
||
| 4752 | * can increase data width, function for extended range |
||
| 4753 | * may be needed: @ref LL_ADC_INJ_ReadConversionData32. |
||
| 4754 | * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n |
||
| 4755 | * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n |
||
| 4756 | * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n |
||
| 4757 | * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 |
||
| 4758 | * @param ADCx ADC instance |
||
| 4759 | * @param Rank This parameter can be one of the following values: |
||
| 4760 | * @arg @ref LL_ADC_INJ_RANK_1 |
||
| 4761 | * @arg @ref LL_ADC_INJ_RANK_2 |
||
| 4762 | * @arg @ref LL_ADC_INJ_RANK_3 |
||
| 4763 | * @arg @ref LL_ADC_INJ_RANK_4 |
||
| 4764 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
||
| 4765 | */ |
||
| 4766 | __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) |
||
| 4767 | { |
||
| 4768 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); |
||
| 4769 | |||
| 4770 | return (uint16_t)(READ_BIT(*preg, |
||
| 4771 | ADC_JDR1_JDATA) |
||
| 4772 | ); |
||
| 4773 | } |
||
| 4774 | |||
| 4775 | /** |
||
| 4776 | * @brief Get ADC group injected conversion data, range fit for |
||
| 4777 | * ADC resolution 10 bits. |
||
| 4778 | * @note For devices with feature oversampling: Oversampling |
||
| 4779 | * can increase data width, function for extended range |
||
| 4780 | * may be needed: @ref LL_ADC_INJ_ReadConversionData32. |
||
| 4781 | * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n |
||
| 4782 | * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n |
||
| 4783 | * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n |
||
| 4784 | * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 |
||
| 4785 | * @param ADCx ADC instance |
||
| 4786 | * @param Rank This parameter can be one of the following values: |
||
| 4787 | * @arg @ref LL_ADC_INJ_RANK_1 |
||
| 4788 | * @arg @ref LL_ADC_INJ_RANK_2 |
||
| 4789 | * @arg @ref LL_ADC_INJ_RANK_3 |
||
| 4790 | * @arg @ref LL_ADC_INJ_RANK_4 |
||
| 4791 | * @retval Value between Min_Data=0x000 and Max_Data=0x3FF |
||
| 4792 | */ |
||
| 4793 | __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) |
||
| 4794 | { |
||
| 4795 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); |
||
| 4796 | |||
| 4797 | return (uint16_t)(READ_BIT(*preg, |
||
| 4798 | ADC_JDR1_JDATA) |
||
| 4799 | ); |
||
| 4800 | } |
||
| 4801 | |||
| 4802 | /** |
||
| 4803 | * @brief Get ADC group injected conversion data, range fit for |
||
| 4804 | * ADC resolution 8 bits. |
||
| 4805 | * @note For devices with feature oversampling: Oversampling |
||
| 4806 | * can increase data width, function for extended range |
||
| 4807 | * may be needed: @ref LL_ADC_INJ_ReadConversionData32. |
||
| 4808 | * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n |
||
| 4809 | * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n |
||
| 4810 | * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n |
||
| 4811 | * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 |
||
| 4812 | * @param ADCx ADC instance |
||
| 4813 | * @param Rank This parameter can be one of the following values: |
||
| 4814 | * @arg @ref LL_ADC_INJ_RANK_1 |
||
| 4815 | * @arg @ref LL_ADC_INJ_RANK_2 |
||
| 4816 | * @arg @ref LL_ADC_INJ_RANK_3 |
||
| 4817 | * @arg @ref LL_ADC_INJ_RANK_4 |
||
| 4818 | * @retval Value between Min_Data=0x00 and Max_Data=0xFF |
||
| 4819 | */ |
||
| 4820 | __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) |
||
| 4821 | { |
||
| 4822 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); |
||
| 4823 | |||
| 4824 | return (uint8_t)(READ_BIT(*preg, |
||
| 4825 | ADC_JDR1_JDATA) |
||
| 4826 | ); |
||
| 4827 | } |
||
| 4828 | |||
| 4829 | /** |
||
| 4830 | * @brief Get ADC group injected conversion data, range fit for |
||
| 4831 | * ADC resolution 6 bits. |
||
| 4832 | * @note For devices with feature oversampling: Oversampling |
||
| 4833 | * can increase data width, function for extended range |
||
| 4834 | * may be needed: @ref LL_ADC_INJ_ReadConversionData32. |
||
| 4835 | * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n |
||
| 4836 | * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n |
||
| 4837 | * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n |
||
| 4838 | * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 |
||
| 4839 | * @param ADCx ADC instance |
||
| 4840 | * @param Rank This parameter can be one of the following values: |
||
| 4841 | * @arg @ref LL_ADC_INJ_RANK_1 |
||
| 4842 | * @arg @ref LL_ADC_INJ_RANK_2 |
||
| 4843 | * @arg @ref LL_ADC_INJ_RANK_3 |
||
| 4844 | * @arg @ref LL_ADC_INJ_RANK_4 |
||
| 4845 | * @retval Value between Min_Data=0x00 and Max_Data=0x3F |
||
| 4846 | */ |
||
| 4847 | __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) |
||
| 4848 | { |
||
| 4849 | uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); |
||
| 4850 | |||
| 4851 | return (uint8_t)(READ_BIT(*preg, |
||
| 4852 | ADC_JDR1_JDATA) |
||
| 4853 | ); |
||
| 4854 | } |
||
| 4855 | |||
| 4856 | /** |
||
| 4857 | * @} |
||
| 4858 | */ |
||
| 4859 | |||
| 4860 | /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management |
||
| 4861 | * @{ |
||
| 4862 | */ |
||
| 4863 | |||
| 4864 | /** |
||
| 4865 | * @brief Get flag ADC ready. |
||
| 4866 | * @rmtoll SR ADONS LL_ADC_IsActiveFlag_ADRDY |
||
| 4867 | * @param ADCx ADC instance |
||
| 4868 | * @retval State of bit (1 or 0). |
||
| 4869 | */ |
||
| 4870 | __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) |
||
| 4871 | { |
||
| 4872 | return (READ_BIT(ADCx->SR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)); |
||
| 4873 | } |
||
| 4874 | |||
| 4875 | /** |
||
| 4876 | * @brief Get flag ADC group regular end of unitary conversion |
||
| 4877 | * or end of sequence conversions, depending on |
||
| 4878 | * ADC configuration. |
||
| 4879 | * @note To configure flag of end of conversion, |
||
| 4880 | * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). |
||
| 4881 | * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS |
||
| 4882 | * @param ADCx ADC instance |
||
| 4883 | * @retval State of bit (1 or 0). |
||
| 4884 | */ |
||
| 4885 | __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx) |
||
| 4886 | { |
||
| 4887 | return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); |
||
| 4888 | } |
||
| 4889 | |||
| 4890 | /** |
||
| 4891 | * @brief Get flag ADC group regular overrun. |
||
| 4892 | * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR |
||
| 4893 | * @param ADCx ADC instance |
||
| 4894 | * @retval State of bit (1 or 0). |
||
| 4895 | */ |
||
| 4896 | __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) |
||
| 4897 | { |
||
| 4898 | return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); |
||
| 4899 | } |
||
| 4900 | |||
| 4901 | |||
| 4902 | /** |
||
| 4903 | * @brief Get flag ADC group injected end of sequence conversions. |
||
| 4904 | * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS |
||
| 4905 | * @param ADCx ADC instance |
||
| 4906 | * @retval State of bit (1 or 0). |
||
| 4907 | */ |
||
| 4908 | __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) |
||
| 4909 | { |
||
| 4910 | /* Note: on this STM32 series, there is no flag ADC group injected */ |
||
| 4911 | /* end of unitary conversion. */ |
||
| 4912 | /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ |
||
| 4913 | /* in other STM32 families). */ |
||
| 4914 | return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); |
||
| 4915 | } |
||
| 4916 | |||
| 4917 | /** |
||
| 4918 | * @brief Get flag ADC analog watchdog 1 flag |
||
| 4919 | * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 |
||
| 4920 | * @param ADCx ADC instance |
||
| 4921 | * @retval State of bit (1 or 0). |
||
| 4922 | */ |
||
| 4923 | __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) |
||
| 4924 | { |
||
| 4925 | return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); |
||
| 4926 | } |
||
| 4927 | |||
| 4928 | /** |
||
| 4929 | * @brief Clear flag ADC group regular end of unitary conversion |
||
| 4930 | * or end of sequence conversions, depending on |
||
| 4931 | * ADC configuration. |
||
| 4932 | * @note To configure flag of end of conversion, |
||
| 4933 | * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). |
||
| 4934 | * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS |
||
| 4935 | * @param ADCx ADC instance |
||
| 4936 | * @retval None |
||
| 4937 | */ |
||
| 4938 | __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx) |
||
| 4939 | { |
||
| 4940 | WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS); |
||
| 4941 | } |
||
| 4942 | |||
| 4943 | /** |
||
| 4944 | * @brief Clear flag ADC group regular overrun. |
||
| 4945 | * @rmtoll SR OVR LL_ADC_ClearFlag_OVR |
||
| 4946 | * @param ADCx ADC instance |
||
| 4947 | * @retval None |
||
| 4948 | */ |
||
| 4949 | __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) |
||
| 4950 | { |
||
| 4951 | WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR); |
||
| 4952 | } |
||
| 4953 | |||
| 4954 | |||
| 4955 | /** |
||
| 4956 | * @brief Clear flag ADC group injected end of sequence conversions. |
||
| 4957 | * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS |
||
| 4958 | * @param ADCx ADC instance |
||
| 4959 | * @retval None |
||
| 4960 | */ |
||
| 4961 | __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) |
||
| 4962 | { |
||
| 4963 | /* Note: on this STM32 series, there is no flag ADC group injected */ |
||
| 4964 | /* end of unitary conversion. */ |
||
| 4965 | /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ |
||
| 4966 | /* in other STM32 families). */ |
||
| 4967 | WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); |
||
| 4968 | } |
||
| 4969 | |||
| 4970 | /** |
||
| 4971 | * @brief Clear flag ADC analog watchdog 1. |
||
| 4972 | * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 |
||
| 4973 | * @param ADCx ADC instance |
||
| 4974 | * @retval None |
||
| 4975 | */ |
||
| 4976 | __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) |
||
| 4977 | { |
||
| 4978 | WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); |
||
| 4979 | } |
||
| 4980 | |||
| 4981 | /** |
||
| 4982 | * @} |
||
| 4983 | */ |
||
| 4984 | |||
| 4985 | /** @defgroup ADC_LL_EF_IT_Management ADC IT management |
||
| 4986 | * @{ |
||
| 4987 | */ |
||
| 4988 | |||
| 4989 | /** |
||
| 4990 | * @brief Enable interruption ADC group regular end of unitary conversion |
||
| 4991 | * or end of sequence conversions, depending on |
||
| 4992 | * ADC configuration. |
||
| 4993 | * @note To configure flag of end of conversion, |
||
| 4994 | * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). |
||
| 4995 | * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS |
||
| 4996 | * @param ADCx ADC instance |
||
| 4997 | * @retval None |
||
| 4998 | */ |
||
| 4999 | __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx) |
||
| 5000 | { |
||
| 5001 | SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS); |
||
| 5002 | } |
||
| 5003 | |||
| 5004 | /** |
||
| 5005 | * @brief Enable ADC group regular interruption overrun. |
||
| 5006 | * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR |
||
| 5007 | * @param ADCx ADC instance |
||
| 5008 | * @retval None |
||
| 5009 | */ |
||
| 5010 | __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) |
||
| 5011 | { |
||
| 5012 | SET_BIT(ADCx->CR1, LL_ADC_IT_OVR); |
||
| 5013 | } |
||
| 5014 | |||
| 5015 | |||
| 5016 | /** |
||
| 5017 | * @brief Enable interruption ADC group injected end of sequence conversions. |
||
| 5018 | * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS |
||
| 5019 | * @param ADCx ADC instance |
||
| 5020 | * @retval None |
||
| 5021 | */ |
||
| 5022 | __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) |
||
| 5023 | { |
||
| 5024 | /* Note: on this STM32 series, there is no flag ADC group injected */ |
||
| 5025 | /* end of unitary conversion. */ |
||
| 5026 | /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ |
||
| 5027 | /* in other STM32 families). */ |
||
| 5028 | SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); |
||
| 5029 | } |
||
| 5030 | |||
| 5031 | /** |
||
| 5032 | * @brief Enable interruption ADC analog watchdog 1. |
||
| 5033 | * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 |
||
| 5034 | * @param ADCx ADC instance |
||
| 5035 | * @retval None |
||
| 5036 | */ |
||
| 5037 | __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) |
||
| 5038 | { |
||
| 5039 | SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); |
||
| 5040 | } |
||
| 5041 | |||
| 5042 | /** |
||
| 5043 | * @brief Disable interruption ADC group regular end of unitary conversion |
||
| 5044 | * or end of sequence conversions, depending on |
||
| 5045 | * ADC configuration. |
||
| 5046 | * @note To configure flag of end of conversion, |
||
| 5047 | * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). |
||
| 5048 | * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS |
||
| 5049 | * @param ADCx ADC instance |
||
| 5050 | * @retval None |
||
| 5051 | */ |
||
| 5052 | __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx) |
||
| 5053 | { |
||
| 5054 | CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS); |
||
| 5055 | } |
||
| 5056 | |||
| 5057 | /** |
||
| 5058 | * @brief Disable interruption ADC group regular overrun. |
||
| 5059 | * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR |
||
| 5060 | * @param ADCx ADC instance |
||
| 5061 | * @retval None |
||
| 5062 | */ |
||
| 5063 | __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) |
||
| 5064 | { |
||
| 5065 | CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR); |
||
| 5066 | } |
||
| 5067 | |||
| 5068 | |||
| 5069 | /** |
||
| 5070 | * @brief Disable interruption ADC group injected end of sequence conversions. |
||
| 5071 | * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS |
||
| 5072 | * @param ADCx ADC instance |
||
| 5073 | * @retval None |
||
| 5074 | */ |
||
| 5075 | __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) |
||
| 5076 | { |
||
| 5077 | /* Note: on this STM32 series, there is no flag ADC group injected */ |
||
| 5078 | /* end of unitary conversion. */ |
||
| 5079 | /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ |
||
| 5080 | /* in other STM32 families). */ |
||
| 5081 | CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); |
||
| 5082 | } |
||
| 5083 | |||
| 5084 | /** |
||
| 5085 | * @brief Disable interruption ADC analog watchdog 1. |
||
| 5086 | * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 |
||
| 5087 | * @param ADCx ADC instance |
||
| 5088 | * @retval None |
||
| 5089 | */ |
||
| 5090 | __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) |
||
| 5091 | { |
||
| 5092 | CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); |
||
| 5093 | } |
||
| 5094 | |||
| 5095 | /** |
||
| 5096 | * @brief Get state of interruption ADC group regular end of unitary conversion |
||
| 5097 | * or end of sequence conversions, depending on |
||
| 5098 | * ADC configuration. |
||
| 5099 | * @note To configure flag of end of conversion, |
||
| 5100 | * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). |
||
| 5101 | * (0: interrupt disabled, 1: interrupt enabled) |
||
| 5102 | * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS |
||
| 5103 | * @param ADCx ADC instance |
||
| 5104 | * @retval State of bit (1 or 0). |
||
| 5105 | */ |
||
| 5106 | __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx) |
||
| 5107 | { |
||
| 5108 | return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS)); |
||
| 5109 | } |
||
| 5110 | |||
| 5111 | /** |
||
| 5112 | * @brief Get state of interruption ADC group regular overrun |
||
| 5113 | * (0: interrupt disabled, 1: interrupt enabled). |
||
| 5114 | * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR |
||
| 5115 | * @param ADCx ADC instance |
||
| 5116 | * @retval State of bit (1 or 0). |
||
| 5117 | */ |
||
| 5118 | __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) |
||
| 5119 | { |
||
| 5120 | return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); |
||
| 5121 | } |
||
| 5122 | |||
| 5123 | |||
| 5124 | /** |
||
| 5125 | * @brief Get state of interruption ADC group injected end of sequence conversions |
||
| 5126 | * (0: interrupt disabled, 1: interrupt enabled). |
||
| 5127 | * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS |
||
| 5128 | * @param ADCx ADC instance |
||
| 5129 | * @retval State of bit (1 or 0). |
||
| 5130 | */ |
||
| 5131 | __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) |
||
| 5132 | { |
||
| 5133 | /* Note: on this STM32 series, there is no flag ADC group injected */ |
||
| 5134 | /* end of unitary conversion. */ |
||
| 5135 | /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ |
||
| 5136 | /* in other STM32 families). */ |
||
| 5137 | return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); |
||
| 5138 | } |
||
| 5139 | |||
| 5140 | /** |
||
| 5141 | * @brief Get state of interruption ADC analog watchdog 1 |
||
| 5142 | * (0: interrupt disabled, 1: interrupt enabled). |
||
| 5143 | * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 |
||
| 5144 | * @param ADCx ADC instance |
||
| 5145 | * @retval State of bit (1 or 0). |
||
| 5146 | */ |
||
| 5147 | __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) |
||
| 5148 | { |
||
| 5149 | return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); |
||
| 5150 | } |
||
| 5151 | |||
| 5152 | /** |
||
| 5153 | * @} |
||
| 5154 | */ |
||
| 5155 | |||
| 5156 | #if defined(USE_FULL_LL_DRIVER) |
||
| 5157 | /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions |
||
| 5158 | * @{ |
||
| 5159 | */ |
||
| 5160 | |||
| 5161 | /* Initialization of some features of ADC common parameters and multimode */ |
||
| 5162 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); |
||
| 5163 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); |
||
| 5164 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); |
||
| 5165 | |||
| 5166 | /* De-initialization of ADC instance, ADC group regular and ADC group injected */ |
||
| 5167 | /* (availability of ADC group injected depends on STM32 families) */ |
||
| 5168 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); |
||
| 5169 | |||
| 5170 | /* Initialization of some features of ADC instance */ |
||
| 5171 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); |
||
| 5172 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); |
||
| 5173 | |||
| 5174 | /* Initialization of some features of ADC instance and ADC group regular */ |
||
| 5175 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); |
||
| 5176 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); |
||
| 5177 | |||
| 5178 | /* Initialization of some features of ADC instance and ADC group injected */ |
||
| 5179 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); |
||
| 5180 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); |
||
| 5181 | |||
| 5182 | /** |
||
| 5183 | * @} |
||
| 5184 | */ |
||
| 5185 | #endif /* USE_FULL_LL_DRIVER */ |
||
| 5186 | |||
| 5187 | /** |
||
| 5188 | * @} |
||
| 5189 | */ |
||
| 5190 | |||
| 5191 | /** |
||
| 5192 | * @} |
||
| 5193 | */ |
||
| 5194 | |||
| 5195 | #endif /* ADC1 */ |
||
| 5196 | |||
| 5197 | /** |
||
| 5198 | * @} |
||
| 5199 | */ |
||
| 5200 | |||
| 5201 | #ifdef __cplusplus |
||
| 5202 | } |
||
| 5203 | #endif |
||
| 5204 | |||
| 5205 | #endif /* __STM32L1xx_LL_ADC_H */ |