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/**
2
  ******************************************************************************
3
  * @file    stm32l1xx_hal_pwr.h
4
  * @author  MCD Application Team
5
  * @version V1.2.0
6
  * @date    01-July-2016
7
  * @brief   Header file of PWR HAL module.
8
  ******************************************************************************
9
  * @attention
10
  *
11
  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12
  *
13
  * Redistribution and use in source and binary forms, with or without modification,
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  * are permitted provided that the following conditions are met:
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  *   1. Redistributions of source code must retain the above copyright notice,
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  *      this list of conditions and the following disclaimer.
17
  *   2. Redistributions in binary form must reproduce the above copyright notice,
18
  *      this list of conditions and the following disclaimer in the documentation
19
  *      and/or other materials provided with the distribution.
20
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
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  *      may be used to endorse or promote products derived from this software
22
  *      without specific prior written permission.
23
  *
24
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34
  *
35
  ******************************************************************************
36
  */
37
 
38
/* Define to prevent recursive inclusion -------------------------------------*/
39
#ifndef __STM32L1xx_HAL_PWR_H
40
#define __STM32L1xx_HAL_PWR_H
41
 
42
#ifdef __cplusplus
43
 extern "C" {
44
#endif
45
 
46
/* Includes ------------------------------------------------------------------*/
47
#include "stm32l1xx_hal_def.h"
48
 
49
/** @addtogroup STM32L1xx_HAL_Driver
50
  * @{
51
  */
52
 
53
/** @addtogroup PWR
54
  * @{
55
  */
56
 
57
/* Exported types ------------------------------------------------------------*/
58
 
59
/** @defgroup PWR_Exported_Types PWR Exported Types
60
  * @{
61
  */
62
 
63
/**
64
  * @brief  PWR PVD configuration structure definition
65
  */
66
typedef struct
67
{
68
  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
69
                            This parameter can be a value of @ref PWR_PVD_detection_level */
70
 
71
  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
72
                           This parameter can be a value of @ref PWR_PVD_Mode */
73
}PWR_PVDTypeDef;
74
 
75
/**
76
  * @}
77
  */
78
 
79
/* Internal constants --------------------------------------------------------*/
80
 
81
/** @addtogroup PWR_Private_Constants
82
  * @{
83
  */
84
#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
85
 
86
/**
87
  * @}
88
  */
89
 
90
 
91
 
92
/* Exported constants --------------------------------------------------------*/
93
 
94
/** @defgroup PWR_Exported_Constants PWR Exported Constants
95
  * @{
96
  */
97
 
98
/** @defgroup PWR_register_alias_address PWR Register alias address
99
  * @{
100
  */
101
/* ------------- PWR registers bit address in the alias region ---------------*/
102
#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
103
#define PWR_CR_OFFSET            0x00
104
#define PWR_CSR_OFFSET           0x04
105
#define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
106
#define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
107
/**
108
  * @}
109
  */
110
 
111
/** @defgroup PWR_CR_register_alias PWR CR Register alias address
112
  * @{
113
  */  
114
/* --- CR Register ---*/
115
/* Alias word address of LPSDSR bit */
116
#define LPSDSR_BIT_NUMBER        POSITION_VAL(PWR_CR_LPSDSR)
117
#define CR_LPSDSR_BB             ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
118
 
119
/* Alias word address of DBP bit */
120
#define DBP_BIT_NUMBER           POSITION_VAL(PWR_CR_DBP)
121
#define CR_DBP_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
122
 
123
/* Alias word address of LPRUN bit */
124
#define LPRUN_BIT_NUMBER         POSITION_VAL(PWR_CR_LPRUN)
125
#define CR_LPRUN_BB              ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4)))
126
 
127
/* Alias word address of PVDE bit */
128
#define PVDE_BIT_NUMBER          POSITION_VAL(PWR_CR_PVDE)
129
#define CR_PVDE_BB               ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
130
 
131
/* Alias word address of FWU bit */
132
#define FWU_BIT_NUMBER           POSITION_VAL(PWR_CR_FWU)
133
#define CR_FWU_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4)))
134
 
135
/* Alias word address of ULP bit */
136
#define ULP_BIT_NUMBER           POSITION_VAL(PWR_CR_ULP)
137
#define CR_ULP_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4)))
138
/**
139
  * @}
140
  */
141
 
142
/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
143
  * @{
144
  */
145
 
146
/* --- CSR Register ---*/
147
/* Alias word address of EWUP1, EWUP2 and EWUP3 bits */
148
#define CSR_EWUP_BB(VAL)         ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
149
/**
150
  * @}
151
  */
152
 
153
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
154
  * @{
155
  */
156
#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0
157
#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1
158
#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2
159
#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3
160
#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4
161
#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5
162
#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6
163
#define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7  /* External input analog voltage 
164
                                                            (Compare internally to VREFINT) */
165
 
166
/**
167
  * @}
168
  */
169
 
170
/** @defgroup PWR_PVD_Mode PWR PVD Mode
171
  * @{
172
  */
173
#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
174
#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
175
#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
176
#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
177
#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
178
#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
179
#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
180
 
181
 /**
182
 * @}
183
  */
184
 
185
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
186
  * @{
187
  */
188
#define PWR_MAINREGULATOR_ON           ((uint32_t)0x00000000)
189
#define PWR_LOWPOWERREGULATOR_ON       PWR_CR_LPSDSR
190
 
191
/**
192
  * @}
193
  */
194
 
195
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
196
  * @{
197
  */
198
#define PWR_SLEEPENTRY_WFI             ((uint8_t)0x01)
199
#define PWR_SLEEPENTRY_WFE             ((uint8_t)0x02)
200
 
201
/**
202
  * @}
203
  */
204
 
205
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
206
  * @{
207
  */
208
#define PWR_STOPENTRY_WFI              ((uint8_t)0x01)
209
#define PWR_STOPENTRY_WFE              ((uint8_t)0x02)
210
 
211
/**
212
  * @}
213
  */
214
 
215
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
216
  * @{
217
  */
218
 
219
#define PWR_REGULATOR_VOLTAGE_SCALE1       PWR_CR_VOS_0
220
#define PWR_REGULATOR_VOLTAGE_SCALE2       PWR_CR_VOS_1
221
#define PWR_REGULATOR_VOLTAGE_SCALE3       PWR_CR_VOS
222
 
223
 
224
/**
225
  * @}
226
  */
227
 
228
/** @defgroup PWR_Flag PWR Flag
229
  * @{
230
  */
231
#define PWR_FLAG_WU                    PWR_CSR_WUF
232
#define PWR_FLAG_SB                    PWR_CSR_SBF
233
#define PWR_FLAG_PVDO                  PWR_CSR_PVDO
234
#define PWR_FLAG_VREFINTRDY            PWR_CSR_VREFINTRDYF
235
#define PWR_FLAG_VOS                   PWR_CSR_VOSF
236
#define PWR_FLAG_REGLP                 PWR_CSR_REGLPF
237
 
238
/**
239
  * @}
240
  */
241
 
242
/**
243
  * @}
244
  */
245
 
246
/* Exported macro ------------------------------------------------------------*/
247
/** @defgroup PWR_Exported_Macros PWR Exported Macros
248
  * @{
249
  */
250
 
251
/** @brief  macros configure the main internal regulator output voltage.
252
  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
253
  *         a tradeoff between performance and power consumption when the device does
254
  *         not operate at the maximum frequency (refer to the datasheets for more details).
255
  *          This parameter can be one of the following values:
256
  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
257
  *                                                System frequency up to 32 MHz.
258
  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
259
  *                                                System frequency up to 16 MHz.
260
  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
261
  *                                                System frequency up to 4.2 MHz
262
  * @retval None
263
  */
264
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
265
 
266
/** @brief  Check PWR flag is set or not.
267
  * @param  __FLAG__: specifies the flag to check.
268
  *           This parameter can be one of the following values:
269
  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
270
  *                  was received from the WKUP pin or from the RTC alarm (Alarm B),
271
  *                  RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
272
  *                  An additional wakeup event is detected if the WKUP pin is enabled
273
  *                  (by setting the EWUP bit) when the WKUP pin level is already high.
274
  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
275
  *                  resumed from StandBy mode.
276
  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
277
  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
278
  *                  For this reason, this bit is equal to 0 after Standby or reset
279
  *                  until the PVDE bit is set.
280
  *            @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
281
  *                 This bit indicates the state of the internal voltage reference, VREFINT.
282
  *            @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
283
  *                 the internal regulator to be ready after the voltage range is changed.
284
  *                 The VOSF bit indicates that the regulator has reached the voltage level
285
  *                 defined with bits VOS of PWR_CR register.
286
  *            @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
287
  *                 mode, this bit stays at 1 until the regulator is ready in main mode.
288
  *                 A polling on this bit is recommended to wait for the regulator main mode.
289
  *                 This bit is reset by hardware when the regulator is ready.
290
  * @retval The new state of __FLAG__ (TRUE or FALSE).
291
  */
292
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
293
 
294
/** @brief  Clear the PWR's pending flags.
295
  * @param  __FLAG__: specifies the flag to clear.
296
  *          This parameter can be one of the following values:
297
  *            @arg PWR_FLAG_WU: Wake Up flag
298
  *            @arg PWR_FLAG_SB: StandBy flag
299
  */
300
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
301
 
302
/**
303
  * @brief Enable interrupt on PVD Exti Line 16.
304
  * @retval None.
305
  */
306
#define __HAL_PWR_PVD_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
307
 
308
/**
309
  * @brief Disable interrupt on PVD Exti Line 16.
310
  * @retval None.
311
  */
312
#define __HAL_PWR_PVD_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
313
 
314
/**
315
  * @brief Enable event on PVD Exti Line 16.
316
  * @retval None.
317
  */
318
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
319
 
320
/**
321
  * @brief Disable event on PVD Exti Line 16.
322
  * @retval None.
323
  */
324
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
325
 
326
 
327
/**
328
  * @brief  PVD EXTI line configuration: set falling edge trigger.
329
  * @retval None.
330
  */
331
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
332
 
333
 
334
/**
335
  * @brief Disable the PVD Extended Interrupt Falling Trigger.
336
  * @retval None.
337
  */
338
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
339
 
340
 
341
/**
342
  * @brief  PVD EXTI line configuration: set rising edge trigger.
343
  * @retval None.
344
  */
345
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
346
 
347
/**
348
  * @brief Disable the PVD Extended Interrupt Rising Trigger.
349
  * @retval None.
350
  */
351
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
352
 
353
/**
354
  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
355
  * @retval None.
356
  */
357
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
358
  do {                                                   \
359
    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
360
    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
361
  } while(0)  
362
 
363
/**
364
  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
365
  * @retval None.
366
  */
367
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
368
  do {                                                    \
369
    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
370
    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
371
  } while(0)  
372
 
373
 
374
 
375
/**
376
  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
377
  * @retval EXTI PVD Line Status.
378
  */
379
#define __HAL_PWR_PVD_EXTI_GET_FLAG()       (EXTI->PR & (PWR_EXTI_LINE_PVD))
380
 
381
/**
382
  * @brief Clear the PVD EXTI flag.
383
  * @retval None.
384
  */
385
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()     (EXTI->PR = (PWR_EXTI_LINE_PVD))
386
 
387
/**
388
  * @brief Generate a Software interrupt on selected EXTI line.
389
  * @retval None.
390
  */
391
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
392
 
393
/**
394
  * @}
395
  */
396
 
397
/* Private macro -------------------------------------------------------------*/
398
/** @defgroup PWR_Private_Macros PWR Private Macros
399
  * @{
400
  */
401
 
402
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
403
                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
404
                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
405
                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
406
 
407
 
408
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
409
                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
410
                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
411
                              ((MODE) == PWR_PVD_MODE_NORMAL))
412
 
413
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
414
                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
415
 
416
 
417
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
418
 
419
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
420
 
421
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
422
                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
423
                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
424
 
425
 
426
/**
427
  * @}
428
  */
429
 
430
 
431
 
432
/* Include PWR HAL Extension module */
433
#include "stm32l1xx_hal_pwr_ex.h"
434
 
435
/* Exported functions --------------------------------------------------------*/
436
 
437
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
438
  * @{
439
  */
440
 
441
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
442
  * @{
443
  */
444
 
445
/* Initialization and de-initialization functions *******************************/
446
void HAL_PWR_DeInit(void);
447
void HAL_PWR_EnableBkUpAccess(void);
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void HAL_PWR_DisableBkUpAccess(void);
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/**
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  * @}
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  */
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/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
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  * @{
456
  */
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/* Peripheral Control functions  ************************************************/
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void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
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void HAL_PWR_EnablePVD(void);
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void HAL_PWR_DisablePVD(void);
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/* WakeUp pins configuration functions ****************************************/
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void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
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void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
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/* Low Power modes configuration functions ************************************/
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void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
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void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
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void HAL_PWR_EnterSTANDBYMode(void);
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void HAL_PWR_EnableSleepOnExit(void);
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void HAL_PWR_DisableSleepOnExit(void);
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void HAL_PWR_EnableSEVOnPend(void);
475
void HAL_PWR_DisableSEVOnPend(void);
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void HAL_PWR_PVD_IRQHandler(void);
480
void HAL_PWR_PVDCallback(void);
481
/**
482
  * @}
483
  */
484
 
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/**
486
  * @}
487
  */
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/**
490
  * @}
491
  */
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/**
494
  * @}
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  */
496
 
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32L1xx_HAL_PWR_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/