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77 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32l1xx_hal_pwr.h |
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4 | * @author MCD Application Team |
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5 | * @brief Header file of PWR HAL module. |
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6 | ****************************************************************************** |
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7 | * @attention |
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8 | * |
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9 | * Copyright (c) 2017 STMicroelectronics. |
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10 | * All rights reserved. |
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11 | * |
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12 | * This software is licensed under terms that can be found in the LICENSE file |
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13 | * in the root directory of this software component. |
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14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
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15 | * |
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16 | ****************************************************************************** |
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17 | */ |
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18 | |||
19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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20 | #ifndef __STM32L1xx_HAL_PWR_H |
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21 | #define __STM32L1xx_HAL_PWR_H |
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22 | |||
23 | #ifdef __cplusplus |
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24 | extern "C" { |
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25 | #endif |
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26 | |||
27 | /* Includes ------------------------------------------------------------------*/ |
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28 | #include "stm32l1xx_hal_def.h" |
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29 | |||
30 | /** @addtogroup STM32L1xx_HAL_Driver |
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31 | * @{ |
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32 | */ |
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33 | |||
34 | /** @addtogroup PWR |
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35 | * @{ |
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36 | */ |
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37 | |||
38 | /* Exported types ------------------------------------------------------------*/ |
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39 | |||
40 | /** @defgroup PWR_Exported_Types PWR Exported Types |
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41 | * @{ |
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42 | */ |
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43 | |||
44 | /** |
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45 | * @brief PWR PVD configuration structure definition |
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46 | */ |
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47 | typedef struct |
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48 | { |
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49 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
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50 | This parameter can be a value of @ref PWR_PVD_detection_level */ |
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51 | |||
52 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
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53 | This parameter can be a value of @ref PWR_PVD_Mode */ |
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54 | }PWR_PVDTypeDef; |
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55 | |||
56 | /** |
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57 | * @} |
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58 | */ |
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59 | |||
60 | /* Internal constants --------------------------------------------------------*/ |
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61 | |||
62 | /** @addtogroup PWR_Private_Constants |
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63 | * @{ |
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64 | */ |
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65 | #define PWR_EXTI_LINE_PVD (0x00010000U) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
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66 | |||
67 | /** |
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68 | * @} |
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69 | */ |
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70 | |||
71 | |||
72 | |||
73 | /* Exported constants --------------------------------------------------------*/ |
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74 | |||
75 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
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76 | * @{ |
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77 | */ |
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78 | |||
79 | /** @defgroup PWR_register_alias_address PWR Register alias address |
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80 | * @{ |
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81 | */ |
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82 | /* ------------- PWR registers bit address in the alias region ---------------*/ |
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83 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) |
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84 | #define PWR_CR_OFFSET 0x00 |
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85 | #define PWR_CSR_OFFSET 0x04 |
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86 | #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) |
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87 | #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) |
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88 | /** |
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89 | * @} |
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90 | */ |
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91 | |||
92 | /** @defgroup PWR_CR_register_alias PWR CR Register alias address |
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93 | * @{ |
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94 | */ |
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95 | /* --- CR Register ---*/ |
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96 | /* Alias word address of LPSDSR bit */ |
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97 | #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR) |
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98 | #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4))) |
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99 | |||
100 | /* Alias word address of DBP bit */ |
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101 | #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) |
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102 | #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))) |
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103 | |||
104 | /* Alias word address of LPRUN bit */ |
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105 | #define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN) |
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106 | #define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4))) |
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107 | |||
108 | /* Alias word address of PVDE bit */ |
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109 | #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) |
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110 | #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))) |
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111 | |||
112 | /* Alias word address of FWU bit */ |
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113 | #define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU) |
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114 | #define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4))) |
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115 | |||
116 | /* Alias word address of ULP bit */ |
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117 | #define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP) |
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118 | #define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4))) |
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119 | /** |
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120 | * @} |
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121 | */ |
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122 | |||
123 | /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address |
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124 | * @{ |
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125 | */ |
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126 | |||
127 | /* --- CSR Register ---*/ |
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128 | /* Alias word address of EWUP1, EWUP2 and EWUP3 bits */ |
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129 | #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4))) |
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130 | /** |
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131 | * @} |
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132 | */ |
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133 | |||
134 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level |
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135 | * @{ |
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136 | */ |
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137 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 |
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138 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 |
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139 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 |
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140 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 |
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141 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 |
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142 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 |
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143 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 |
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144 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage |
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145 | (Compare internally to VREFINT) */ |
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146 | |||
147 | /** |
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148 | * @} |
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149 | */ |
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150 | |||
151 | /** @defgroup PWR_PVD_Mode PWR PVD Mode |
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152 | * @{ |
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153 | */ |
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154 | #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ |
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155 | #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ |
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156 | #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ |
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157 | #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
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158 | #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ |
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159 | #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ |
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160 | #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ |
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161 | |||
162 | /** |
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163 | * @} |
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164 | */ |
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165 | |||
166 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode |
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167 | * @{ |
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168 | */ |
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169 | #define PWR_MAINREGULATOR_ON (0x00000000U) |
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170 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR |
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171 | |||
172 | /** |
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173 | * @} |
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174 | */ |
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175 | |||
176 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
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177 | * @{ |
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178 | */ |
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179 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) |
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180 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) |
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181 | |||
182 | /** |
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183 | * @} |
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184 | */ |
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185 | |||
186 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
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187 | * @{ |
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188 | */ |
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189 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) |
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190 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) |
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191 | |||
192 | /** |
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193 | * @} |
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194 | */ |
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195 | |||
196 | /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale |
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197 | * @{ |
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198 | */ |
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199 | |||
200 | #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 |
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201 | #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 |
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202 | #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS |
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203 | |||
204 | |||
205 | /** |
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206 | * @} |
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207 | */ |
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208 | |||
209 | /** @defgroup PWR_Flag PWR Flag |
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210 | * @{ |
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211 | */ |
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212 | #define PWR_FLAG_WU PWR_CSR_WUF |
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213 | #define PWR_FLAG_SB PWR_CSR_SBF |
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214 | #define PWR_FLAG_PVDO PWR_CSR_PVDO |
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215 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF |
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216 | #define PWR_FLAG_VOS PWR_CSR_VOSF |
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217 | #define PWR_FLAG_REGLP PWR_CSR_REGLPF |
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218 | |||
219 | /** |
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220 | * @} |
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221 | */ |
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222 | |||
223 | /** |
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224 | * @} |
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225 | */ |
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226 | |||
227 | /* Exported macro ------------------------------------------------------------*/ |
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228 | /** @defgroup PWR_Exported_Macros PWR Exported Macros |
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229 | * @{ |
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230 | */ |
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231 | |||
232 | /** @brief macros configure the main internal regulator output voltage. |
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233 | * @param __REGULATOR__ specifies the regulator output voltage to achieve |
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234 | * a tradeoff between performance and power consumption when the device does |
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235 | * not operate at the maximum frequency (refer to the datasheets for more details). |
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236 | * This parameter can be one of the following values: |
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237 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, |
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238 | * System frequency up to 32 MHz. |
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239 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, |
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240 | * System frequency up to 16 MHz. |
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241 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, |
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242 | * System frequency up to 4.2 MHz |
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243 | * @retval None |
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244 | */ |
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245 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) |
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246 | |||
247 | /** @brief Check PWR flag is set or not. |
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248 | * @param __FLAG__ specifies the flag to check. |
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249 | * This parameter can be one of the following values: |
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250 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
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251 | * was received from the WKUP pin or from the RTC alarm (Alarm B), |
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252 | * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. |
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253 | * An additional wakeup event is detected if the WKUP pin is enabled |
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254 | * (by setting the EWUP bit) when the WKUP pin level is already high. |
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255 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
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256 | * resumed from StandBy mode. |
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257 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
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258 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode |
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259 | * For this reason, this bit is equal to 0 after Standby or reset |
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260 | * until the PVDE bit is set. |
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261 | * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. |
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262 | * This bit indicates the state of the internal voltage reference, VREFINT. |
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263 | * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for |
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264 | * the internal regulator to be ready after the voltage range is changed. |
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265 | * The VOSF bit indicates that the regulator has reached the voltage level |
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266 | * defined with bits VOS of PWR_CR register. |
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267 | * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run |
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268 | * mode, this bit stays at 1 until the regulator is ready in main mode. |
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269 | * A polling on this bit is recommended to wait for the regulator main mode. |
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270 | * This bit is reset by hardware when the regulator is ready. |
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271 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
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272 | */ |
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273 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
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274 | |||
275 | /** @brief Clear the PWR's pending flags. |
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276 | * @param __FLAG__ specifies the flag to clear. |
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277 | * This parameter can be one of the following values: |
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278 | * @arg PWR_FLAG_WU: Wake Up flag |
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279 | * @arg PWR_FLAG_SB: StandBy flag |
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280 | */ |
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281 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) |
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282 | |||
283 | /** |
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284 | * @brief Enable interrupt on PVD Exti Line 16. |
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285 | * @retval None. |
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286 | */ |
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287 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
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288 | |||
289 | /** |
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290 | * @brief Disable interrupt on PVD Exti Line 16. |
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291 | * @retval None. |
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292 | */ |
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293 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
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294 | |||
295 | /** |
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296 | * @brief Enable event on PVD Exti Line 16. |
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297 | * @retval None. |
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298 | */ |
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299 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
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300 | |||
301 | /** |
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302 | * @brief Disable event on PVD Exti Line 16. |
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303 | * @retval None. |
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304 | */ |
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305 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
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306 | |||
307 | |||
308 | /** |
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309 | * @brief PVD EXTI line configuration: set falling edge trigger. |
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310 | * @retval None. |
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311 | */ |
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312 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
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313 | |||
314 | |||
315 | /** |
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316 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
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317 | * @retval None. |
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318 | */ |
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319 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
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320 | |||
321 | |||
322 | /** |
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323 | * @brief PVD EXTI line configuration: set rising edge trigger. |
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324 | * @retval None. |
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325 | */ |
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326 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
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327 | |||
328 | /** |
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329 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
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330 | * @retval None. |
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331 | */ |
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332 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
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333 | |||
334 | /** |
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335 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. |
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336 | * @retval None. |
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337 | */ |
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338 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
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339 | do { \ |
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340 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ |
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341 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ |
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342 | } while(0) |
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343 | |||
344 | /** |
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345 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
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346 | * @retval None. |
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347 | */ |
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348 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
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349 | do { \ |
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350 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ |
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351 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ |
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352 | } while(0) |
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353 | |||
354 | |||
355 | |||
356 | /** |
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357 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
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358 | * @retval EXTI PVD Line Status. |
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359 | */ |
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360 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
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361 | |||
362 | /** |
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363 | * @brief Clear the PVD EXTI flag. |
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364 | * @retval None. |
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365 | */ |
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366 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
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367 | |||
368 | /** |
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369 | * @brief Generate a Software interrupt on selected EXTI line. |
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370 | * @retval None. |
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371 | */ |
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372 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
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373 | |||
374 | /** |
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375 | * @} |
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376 | */ |
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377 | |||
378 | /* Private macro -------------------------------------------------------------*/ |
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379 | /** @defgroup PWR_Private_Macros PWR Private Macros |
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380 | * @{ |
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381 | */ |
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382 | |||
383 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
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384 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
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385 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
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386 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
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387 | |||
388 | |||
389 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
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390 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
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391 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
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392 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
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393 | |||
394 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
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395 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
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396 | |||
397 | |||
398 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
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399 | |||
400 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) |
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401 | |||
402 | #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
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403 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ |
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404 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) |
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405 | |||
406 | |||
407 | /** |
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408 | * @} |
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409 | */ |
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410 | |||
411 | |||
412 | |||
413 | /* Include PWR HAL Extension module */ |
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414 | #include "stm32l1xx_hal_pwr_ex.h" |
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415 | |||
416 | /* Exported functions --------------------------------------------------------*/ |
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417 | |||
418 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions |
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419 | * @{ |
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420 | */ |
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421 | |||
422 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
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423 | * @{ |
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424 | */ |
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425 | |||
426 | /* Initialization and de-initialization functions *******************************/ |
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427 | void HAL_PWR_DeInit(void); |
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428 | void HAL_PWR_EnableBkUpAccess(void); |
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429 | void HAL_PWR_DisableBkUpAccess(void); |
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430 | |||
431 | /** |
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432 | * @} |
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433 | */ |
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434 | |||
435 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions |
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436 | * @{ |
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437 | */ |
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438 | |||
439 | /* Peripheral Control functions ************************************************/ |
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440 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
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441 | void HAL_PWR_EnablePVD(void); |
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442 | void HAL_PWR_DisablePVD(void); |
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443 | |||
444 | /* WakeUp pins configuration functions ****************************************/ |
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445 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
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446 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
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447 | |||
448 | /* Low Power modes configuration functions ************************************/ |
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449 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
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450 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
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451 | void HAL_PWR_EnterSTANDBYMode(void); |
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452 | |||
453 | void HAL_PWR_EnableSleepOnExit(void); |
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454 | void HAL_PWR_DisableSleepOnExit(void); |
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455 | void HAL_PWR_EnableSEVOnPend(void); |
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456 | void HAL_PWR_DisableSEVOnPend(void); |
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457 | |||
458 | |||
459 | |||
460 | void HAL_PWR_PVD_IRQHandler(void); |
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461 | void HAL_PWR_PVDCallback(void); |
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462 | /** |
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463 | * @} |
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464 | */ |
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465 | |||
466 | /** |
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467 | * @} |
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468 | */ |
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469 | |||
470 | /** |
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471 | * @} |
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472 | */ |
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473 | |||
474 | /** |
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475 | * @} |
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476 | */ |
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477 | |||
478 | #ifdef __cplusplus |
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479 | } |
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480 | #endif |
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481 | |||
482 | |||
483 | #endif /* __STM32L1xx_HAL_PWR_H */ |