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| Rev | Author | Line No. | Line |
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| 30 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32_hal_legacy.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @version V1.2.0 |
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| 6 | * @date 01-July-2016 |
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| 7 | * @brief This file contains aliases definition for the STM32Cube HAL constants |
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| 8 | * macros and functions maintained for legacy purpose. |
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| 9 | ****************************************************************************** |
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| 10 | * @attention |
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| 11 | * |
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| 12 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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| 13 | * |
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| 14 | * Redistribution and use in source and binary forms, with or without modification, |
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| 15 | * are permitted provided that the following conditions are met: |
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| 16 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 17 | * this list of conditions and the following disclaimer. |
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 19 | * this list of conditions and the following disclaimer in the documentation |
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| 20 | * and/or other materials provided with the distribution. |
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| 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 22 | * may be used to endorse or promote products derived from this software |
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| 23 | * without specific prior written permission. |
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| 24 | * |
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| 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 35 | * |
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| 36 | ****************************************************************************** |
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| 37 | */ |
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| 38 | |||
| 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 40 | #ifndef __STM32_HAL_LEGACY |
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| 41 | #define __STM32_HAL_LEGACY |
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| 42 | |||
| 43 | #ifdef __cplusplus |
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| 44 | extern "C" { |
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| 45 | #endif |
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| 46 | |||
| 47 | /* Includes ------------------------------------------------------------------*/ |
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| 48 | /* Exported types ------------------------------------------------------------*/ |
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| 49 | /* Exported constants --------------------------------------------------------*/ |
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| 50 | |||
| 51 | /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose |
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| 52 | * @{ |
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| 53 | */ |
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| 54 | #define AES_FLAG_RDERR CRYP_FLAG_RDERR |
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| 55 | #define AES_FLAG_WRERR CRYP_FLAG_WRERR |
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| 56 | #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF |
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| 57 | #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR |
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| 58 | #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR |
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| 59 | |||
| 60 | /** |
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| 61 | * @} |
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| 62 | */ |
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| 63 | |||
| 64 | /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose |
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| 65 | * @{ |
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| 66 | */ |
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| 67 | #define ADC_RESOLUTION12b ADC_RESOLUTION_12B |
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| 68 | #define ADC_RESOLUTION10b ADC_RESOLUTION_10B |
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| 69 | #define ADC_RESOLUTION8b ADC_RESOLUTION_8B |
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| 70 | #define ADC_RESOLUTION6b ADC_RESOLUTION_6B |
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| 71 | #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN |
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| 72 | #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED |
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| 73 | #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV |
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| 74 | #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV |
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| 75 | #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV |
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| 76 | #define REGULAR_GROUP ADC_REGULAR_GROUP |
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| 77 | #define INJECTED_GROUP ADC_INJECTED_GROUP |
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| 78 | #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP |
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| 79 | #define AWD_EVENT ADC_AWD_EVENT |
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| 80 | #define AWD1_EVENT ADC_AWD1_EVENT |
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| 81 | #define AWD2_EVENT ADC_AWD2_EVENT |
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| 82 | #define AWD3_EVENT ADC_AWD3_EVENT |
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| 83 | #define OVR_EVENT ADC_OVR_EVENT |
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| 84 | #define JQOVF_EVENT ADC_JQOVF_EVENT |
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| 85 | #define ALL_CHANNELS ADC_ALL_CHANNELS |
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| 86 | #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS |
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| 87 | #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS |
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| 88 | #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR |
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| 89 | #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT |
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| 90 | #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 |
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| 91 | #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 |
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| 92 | #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 |
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| 93 | #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 |
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| 94 | #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 |
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| 95 | #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO |
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| 96 | #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 |
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| 97 | #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO |
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| 98 | #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 |
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| 99 | #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO |
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| 100 | #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 |
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| 101 | #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 |
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| 102 | #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE |
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| 103 | #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING |
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| 104 | #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING |
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| 105 | #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING |
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| 106 | #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 |
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| 107 | |||
| 108 | #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY |
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| 109 | #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY |
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| 110 | #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC |
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| 111 | #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC |
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| 112 | #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL |
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| 113 | #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL |
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| 114 | #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 |
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| 115 | /** |
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| 116 | * @} |
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| 117 | */ |
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| 118 | |||
| 119 | /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose |
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| 120 | * @{ |
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| 121 | */ |
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| 122 | |||
| 123 | #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG |
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| 124 | |||
| 125 | /** |
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| 126 | * @} |
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| 127 | */ |
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| 128 | |||
| 129 | /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose |
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| 130 | * @{ |
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| 131 | */ |
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| 132 | #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE |
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| 133 | #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE |
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| 134 | #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 |
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| 135 | #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 |
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| 136 | #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 |
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| 137 | #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 |
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| 138 | #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 |
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| 139 | #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 |
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| 140 | #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 |
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| 141 | #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR |
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| 142 | #if defined(STM32F373xC) || defined(STM32F378xx) |
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| 143 | #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 |
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| 144 | #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR |
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| 145 | #endif /* STM32F373xC || STM32F378xx */ |
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| 146 | |||
| 147 | #if defined(STM32L0) || defined(STM32L4) |
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| 148 | #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON |
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| 149 | |||
| 150 | #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 |
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| 151 | #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 |
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| 152 | #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 |
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| 153 | #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 |
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| 154 | #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 |
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| 155 | #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 |
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| 156 | |||
| 157 | #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT |
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| 158 | #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT |
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| 159 | #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT |
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| 160 | #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT |
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| 161 | #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 |
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| 162 | #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 |
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| 163 | #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 |
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| 164 | #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 |
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| 165 | #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 |
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| 166 | #if defined(STM32L0) |
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| 167 | /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ |
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| 168 | /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ |
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| 169 | /* to the second dedicated IO (only for COMP2). */ |
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| 170 | #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 |
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| 171 | #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 |
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| 172 | #else |
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| 173 | #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 |
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| 174 | #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 |
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| 175 | #endif |
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| 176 | #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 |
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| 177 | #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 |
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| 178 | |||
| 179 | #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW |
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| 180 | #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH |
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| 181 | |||
| 182 | /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ |
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| 183 | /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ |
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| 184 | #if defined(COMP_CSR_LOCK) |
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| 185 | #define COMP_FLAG_LOCK COMP_CSR_LOCK |
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| 186 | #elif defined(COMP_CSR_COMP1LOCK) |
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| 187 | #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK |
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| 188 | #elif defined(COMP_CSR_COMPxLOCK) |
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| 189 | #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK |
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| 190 | #endif |
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| 191 | |||
| 192 | #if defined(STM32L4) |
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| 193 | #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 |
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| 194 | #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 |
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| 195 | #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 |
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| 196 | #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 |
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| 197 | #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 |
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| 198 | #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 |
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| 199 | #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE |
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| 200 | #endif |
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| 201 | |||
| 202 | #if defined(STM32L0) |
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| 203 | #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED |
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| 204 | #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER |
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| 205 | #else |
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| 206 | #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED |
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| 207 | #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED |
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| 208 | #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER |
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| 209 | #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER |
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| 210 | #endif |
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| 211 | |||
| 212 | #endif |
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| 213 | /** |
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| 214 | * @} |
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| 215 | */ |
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| 216 | |||
| 217 | /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose |
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| 218 | * @{ |
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| 219 | */ |
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| 220 | #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig |
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| 221 | /** |
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| 222 | * @} |
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| 223 | */ |
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| 224 | |||
| 225 | /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose |
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| 226 | * @{ |
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| 227 | */ |
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| 228 | |||
| 229 | #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE |
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| 230 | #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE |
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| 231 | |||
| 232 | /** |
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| 233 | * @} |
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| 234 | */ |
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| 235 | |||
| 236 | /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose |
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| 237 | * @{ |
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| 238 | */ |
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| 239 | |||
| 240 | #define DAC1_CHANNEL_1 DAC_CHANNEL_1 |
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| 241 | #define DAC1_CHANNEL_2 DAC_CHANNEL_2 |
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| 242 | #define DAC2_CHANNEL_1 DAC_CHANNEL_1 |
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| 243 | #define DAC_WAVE_NONE ((uint32_t)0x00000000U) |
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| 244 | #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) |
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| 245 | #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) |
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| 246 | #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE |
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| 247 | #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE |
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| 248 | #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE |
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| 249 | |||
| 250 | /** |
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| 251 | * @} |
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| 252 | */ |
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| 253 | |||
| 254 | /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose |
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| 255 | * @{ |
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| 256 | */ |
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| 257 | #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 |
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| 258 | #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 |
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| 259 | #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 |
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| 260 | #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 |
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| 261 | #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 |
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| 262 | #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 |
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| 263 | #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 |
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| 264 | #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 |
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| 265 | #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 |
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| 266 | #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 |
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| 267 | #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 |
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| 268 | #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 |
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| 269 | #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 |
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| 270 | #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 |
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| 271 | #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 |
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| 272 | |||
| 273 | #define IS_HAL_REMAPDMA IS_DMA_REMAP |
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| 274 | #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE |
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| 275 | #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE |
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| 276 | |||
| 277 | |||
| 278 | |||
| 279 | /** |
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| 280 | * @} |
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| 281 | */ |
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| 282 | |||
| 283 | /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose |
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| 284 | * @{ |
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| 285 | */ |
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| 286 | |||
| 287 | #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE |
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| 288 | #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD |
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| 289 | #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD |
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| 290 | #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD |
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| 291 | #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS |
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| 292 | #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES |
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| 293 | #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES |
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| 294 | #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE |
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| 295 | #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE |
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| 296 | #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE |
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| 297 | #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE |
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| 298 | #define OBEX_PCROP OPTIONBYTE_PCROP |
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| 299 | #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG |
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| 300 | #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE |
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| 301 | #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE |
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| 302 | #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE |
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| 303 | #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD |
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| 304 | #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD |
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| 305 | #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE |
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| 306 | #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD |
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| 307 | #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD |
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| 308 | #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE |
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| 309 | #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD |
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| 310 | #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD |
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| 311 | #define PAGESIZE FLASH_PAGE_SIZE |
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| 312 | #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE |
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| 313 | #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD |
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| 314 | #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD |
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| 315 | #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 |
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| 316 | #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 |
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| 317 | #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 |
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| 318 | #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 |
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| 319 | #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST |
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| 320 | #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST |
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| 321 | #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA |
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| 322 | #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB |
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| 323 | #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA |
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| 324 | #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB |
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| 325 | #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE |
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| 326 | #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN |
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| 327 | #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE |
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| 328 | #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN |
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| 329 | #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE |
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| 330 | #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD |
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| 331 | #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG |
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| 332 | #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS |
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| 333 | #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP |
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| 334 | #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV |
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| 335 | #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR |
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| 336 | #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG |
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| 337 | #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION |
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| 338 | #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA |
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| 339 | #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE |
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| 340 | #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE |
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| 341 | #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS |
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| 342 | #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS |
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| 343 | #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST |
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| 344 | #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR |
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| 345 | #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO |
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| 346 | #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION |
||
| 347 | #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS |
||
| 348 | #define OB_WDG_SW OB_IWDG_SW |
||
| 349 | #define OB_WDG_HW OB_IWDG_HW |
||
| 350 | #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET |
||
| 351 | #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET |
||
| 352 | #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET |
||
| 353 | #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET |
||
| 354 | #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR |
||
| 355 | #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 |
||
| 356 | #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 |
||
| 357 | #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 |
||
| 358 | /** |
||
| 359 | * @} |
||
| 360 | */ |
||
| 361 | |||
| 362 | /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose |
||
| 363 | * @{ |
||
| 364 | */ |
||
| 365 | |||
| 366 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 |
||
| 367 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 |
||
| 368 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 |
||
| 369 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 |
||
| 370 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 |
||
| 371 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 |
||
| 372 | #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 |
||
| 373 | #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 |
||
| 374 | #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 |
||
| 375 | /** |
||
| 376 | * @} |
||
| 377 | */ |
||
| 378 | |||
| 379 | |||
| 380 | /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose |
||
| 381 | * @{ |
||
| 382 | */ |
||
| 383 | #if defined(STM32L4) || defined(STM32F7) |
||
| 384 | #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE |
||
| 385 | #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE |
||
| 386 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 |
||
| 387 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 |
||
| 388 | #else |
||
| 389 | #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE |
||
| 390 | #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE |
||
| 391 | #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 |
||
| 392 | #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
||
| 393 | #endif |
||
| 394 | /** |
||
| 395 | * @} |
||
| 396 | */ |
||
| 397 | |||
| 398 | /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose |
||
| 399 | * @{ |
||
| 400 | */ |
||
| 401 | |||
| 402 | #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef |
||
| 403 | #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef |
||
| 404 | /** |
||
| 405 | * @} |
||
| 406 | */ |
||
| 407 | |||
| 408 | /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose |
||
| 409 | * @{ |
||
| 410 | */ |
||
| 411 | #define GET_GPIO_SOURCE GPIO_GET_INDEX |
||
| 412 | #define GET_GPIO_INDEX GPIO_GET_INDEX |
||
| 413 | |||
| 414 | #if defined(STM32F4) |
||
| 415 | #define GPIO_AF12_SDMMC GPIO_AF12_SDIO |
||
| 416 | #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO |
||
| 417 | #endif |
||
| 418 | |||
| 419 | #if defined(STM32F7) |
||
| 420 | #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 |
||
| 421 | #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 |
||
| 422 | #endif |
||
| 423 | |||
| 424 | #if defined(STM32L4) |
||
| 425 | #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 |
||
| 426 | #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 |
||
| 427 | #endif |
||
| 428 | |||
| 429 | #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 |
||
| 430 | #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 |
||
| 431 | #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 |
||
| 432 | |||
| 433 | #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) |
||
| 434 | #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW |
||
| 435 | #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM |
||
| 436 | #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH |
||
| 437 | #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH |
||
| 438 | #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ |
||
| 439 | |||
| 440 | #if defined(STM32L1) |
||
| 441 | #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW |
||
| 442 | #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM |
||
| 443 | #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH |
||
| 444 | #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH |
||
| 445 | #endif /* STM32L1 */ |
||
| 446 | |||
| 447 | #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) |
||
| 448 | #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW |
||
| 449 | #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM |
||
| 450 | #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH |
||
| 451 | #endif /* STM32F0 || STM32F3 || STM32F1 */ |
||
| 452 | |||
| 453 | #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 |
||
| 454 | /** |
||
| 455 | * @} |
||
| 456 | */ |
||
| 457 | |||
| 458 | /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose |
||
| 459 | * @{ |
||
| 460 | */ |
||
| 461 | #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED |
||
| 462 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 |
||
| 463 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 |
||
| 464 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 |
||
| 465 | #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 |
||
| 466 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 |
||
| 467 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 |
||
| 468 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 |
||
| 469 | #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 |
||
| 470 | |||
| 471 | #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER |
||
| 472 | #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER |
||
| 473 | #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD |
||
| 474 | #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD |
||
| 475 | #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER |
||
| 476 | #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER |
||
| 477 | #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE |
||
| 478 | #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE |
||
| 479 | /** |
||
| 480 | * @} |
||
| 481 | */ |
||
| 482 | |||
| 483 | /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose |
||
| 484 | * @{ |
||
| 485 | */ |
||
| 486 | #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE |
||
| 487 | #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE |
||
| 488 | #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE |
||
| 489 | #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE |
||
| 490 | #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE |
||
| 491 | #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE |
||
| 492 | #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE |
||
| 493 | #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE |
||
| 494 | #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) |
||
| 495 | #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX |
||
| 496 | #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX |
||
| 497 | #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX |
||
| 498 | #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX |
||
| 499 | #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX |
||
| 500 | #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX |
||
| 501 | #endif |
||
| 502 | /** |
||
| 503 | * @} |
||
| 504 | */ |
||
| 505 | |||
| 506 | /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose |
||
| 507 | * @{ |
||
| 508 | */ |
||
| 509 | #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE |
||
| 510 | #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE |
||
| 511 | |||
| 512 | /** |
||
| 513 | * @} |
||
| 514 | */ |
||
| 515 | |||
| 516 | /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose |
||
| 517 | * @{ |
||
| 518 | */ |
||
| 519 | #define KR_KEY_RELOAD IWDG_KEY_RELOAD |
||
| 520 | #define KR_KEY_ENABLE IWDG_KEY_ENABLE |
||
| 521 | #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE |
||
| 522 | #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE |
||
| 523 | /** |
||
| 524 | * @} |
||
| 525 | */ |
||
| 526 | |||
| 527 | /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose |
||
| 528 | * @{ |
||
| 529 | */ |
||
| 530 | |||
| 531 | #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION |
||
| 532 | #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS |
||
| 533 | #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS |
||
| 534 | #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS |
||
| 535 | |||
| 536 | #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING |
||
| 537 | #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING |
||
| 538 | #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING |
||
| 539 | |||
| 540 | #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION |
||
| 541 | #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS |
||
| 542 | #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS |
||
| 543 | #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS |
||
| 544 | |||
| 545 | /* The following 3 definition have also been present in a temporary version of lptim.h */ |
||
| 546 | /* They need to be renamed also to the right name, just in case */ |
||
| 547 | #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS |
||
| 548 | #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS |
||
| 549 | #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS |
||
| 550 | |||
| 551 | /** |
||
| 552 | * @} |
||
| 553 | */ |
||
| 554 | |||
| 555 | /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose |
||
| 556 | * @{ |
||
| 557 | */ |
||
| 558 | #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b |
||
| 559 | #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b |
||
| 560 | #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b |
||
| 561 | #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b |
||
| 562 | |||
| 563 | #define NAND_AddressTypedef NAND_AddressTypeDef |
||
| 564 | |||
| 565 | #define __ARRAY_ADDRESS ARRAY_ADDRESS |
||
| 566 | #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE |
||
| 567 | #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE |
||
| 568 | #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE |
||
| 569 | #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE |
||
| 570 | /** |
||
| 571 | * @} |
||
| 572 | */ |
||
| 573 | |||
| 574 | /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose |
||
| 575 | * @{ |
||
| 576 | */ |
||
| 577 | #define NOR_StatusTypedef HAL_NOR_StatusTypeDef |
||
| 578 | #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS |
||
| 579 | #define NOR_ONGOING HAL_NOR_STATUS_ONGOING |
||
| 580 | #define NOR_ERROR HAL_NOR_STATUS_ERROR |
||
| 581 | #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT |
||
| 582 | |||
| 583 | #define __NOR_WRITE NOR_WRITE |
||
| 584 | #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT |
||
| 585 | /** |
||
| 586 | * @} |
||
| 587 | */ |
||
| 588 | |||
| 589 | /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose |
||
| 590 | * @{ |
||
| 591 | */ |
||
| 592 | |||
| 593 | #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 |
||
| 594 | #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 |
||
| 595 | #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 |
||
| 596 | #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 |
||
| 597 | |||
| 598 | #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 |
||
| 599 | #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 |
||
| 600 | #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 |
||
| 601 | #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 |
||
| 602 | |||
| 603 | #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 |
||
| 604 | #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 |
||
| 605 | |||
| 606 | #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 |
||
| 607 | #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 |
||
| 608 | |||
| 609 | #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 |
||
| 610 | #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 |
||
| 611 | |||
| 612 | #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 |
||
| 613 | |||
| 614 | #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO |
||
| 615 | #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 |
||
| 616 | #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 |
||
| 617 | |||
| 618 | /** |
||
| 619 | * @} |
||
| 620 | */ |
||
| 621 | |||
| 622 | /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose |
||
| 623 | * @{ |
||
| 624 | */ |
||
| 625 | #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS |
||
| 626 | #if defined(STM32F7) |
||
| 627 | #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL |
||
| 628 | #endif |
||
| 629 | /** |
||
| 630 | * @} |
||
| 631 | */ |
||
| 632 | |||
| 633 | /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose |
||
| 634 | * @{ |
||
| 635 | */ |
||
| 636 | |||
| 637 | /* Compact Flash-ATA registers description */ |
||
| 638 | #define CF_DATA ATA_DATA |
||
| 639 | #define CF_SECTOR_COUNT ATA_SECTOR_COUNT |
||
| 640 | #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER |
||
| 641 | #define CF_CYLINDER_LOW ATA_CYLINDER_LOW |
||
| 642 | #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH |
||
| 643 | #define CF_CARD_HEAD ATA_CARD_HEAD |
||
| 644 | #define CF_STATUS_CMD ATA_STATUS_CMD |
||
| 645 | #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE |
||
| 646 | #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA |
||
| 647 | |||
| 648 | /* Compact Flash-ATA commands */ |
||
| 649 | #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD |
||
| 650 | #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD |
||
| 651 | #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD |
||
| 652 | #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD |
||
| 653 | |||
| 654 | #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef |
||
| 655 | #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS |
||
| 656 | #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING |
||
| 657 | #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR |
||
| 658 | #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT |
||
| 659 | /** |
||
| 660 | * @} |
||
| 661 | */ |
||
| 662 | |||
| 663 | /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose |
||
| 664 | * @{ |
||
| 665 | */ |
||
| 666 | |||
| 667 | #define FORMAT_BIN RTC_FORMAT_BIN |
||
| 668 | #define FORMAT_BCD RTC_FORMAT_BCD |
||
| 669 | |||
| 670 | #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE |
||
| 671 | #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE |
||
| 672 | #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE |
||
| 673 | #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE |
||
| 674 | #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE |
||
| 675 | |||
| 676 | #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE |
||
| 677 | #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE |
||
| 678 | #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE |
||
| 679 | #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE |
||
| 680 | #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE |
||
| 681 | #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE |
||
| 682 | #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT |
||
| 683 | #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT |
||
| 684 | |||
| 685 | #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT |
||
| 686 | #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 |
||
| 687 | #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 |
||
| 688 | #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 |
||
| 689 | |||
| 690 | #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE |
||
| 691 | #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 |
||
| 692 | #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 |
||
| 693 | |||
| 694 | #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT |
||
| 695 | #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 |
||
| 696 | #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 |
||
| 697 | |||
| 698 | /** |
||
| 699 | * @} |
||
| 700 | */ |
||
| 701 | |||
| 702 | |||
| 703 | /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose |
||
| 704 | * @{ |
||
| 705 | */ |
||
| 706 | #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE |
||
| 707 | #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE |
||
| 708 | |||
| 709 | #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE |
||
| 710 | #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE |
||
| 711 | #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE |
||
| 712 | #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE |
||
| 713 | |||
| 714 | #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE |
||
| 715 | #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE |
||
| 716 | |||
| 717 | #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE |
||
| 718 | #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE |
||
| 719 | /** |
||
| 720 | * @} |
||
| 721 | */ |
||
| 722 | |||
| 723 | |||
| 724 | /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose |
||
| 725 | * @{ |
||
| 726 | */ |
||
| 727 | #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE |
||
| 728 | #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE |
||
| 729 | #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE |
||
| 730 | #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE |
||
| 731 | #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE |
||
| 732 | #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE |
||
| 733 | #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE |
||
| 734 | #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE |
||
| 735 | #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE |
||
| 736 | #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE |
||
| 737 | #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN |
||
| 738 | /** |
||
| 739 | * @} |
||
| 740 | */ |
||
| 741 | |||
| 742 | /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose |
||
| 743 | * @{ |
||
| 744 | */ |
||
| 745 | #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE |
||
| 746 | #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE |
||
| 747 | |||
| 748 | #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE |
||
| 749 | #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE |
||
| 750 | |||
| 751 | #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE |
||
| 752 | #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE |
||
| 753 | |||
| 754 | /** |
||
| 755 | * @} |
||
| 756 | */ |
||
| 757 | |||
| 758 | /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose |
||
| 759 | * @{ |
||
| 760 | */ |
||
| 761 | #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK |
||
| 762 | #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK |
||
| 763 | |||
| 764 | #define TIM_DMABase_CR1 TIM_DMABASE_CR1 |
||
| 765 | #define TIM_DMABase_CR2 TIM_DMABASE_CR2 |
||
| 766 | #define TIM_DMABase_SMCR TIM_DMABASE_SMCR |
||
| 767 | #define TIM_DMABase_DIER TIM_DMABASE_DIER |
||
| 768 | #define TIM_DMABase_SR TIM_DMABASE_SR |
||
| 769 | #define TIM_DMABase_EGR TIM_DMABASE_EGR |
||
| 770 | #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 |
||
| 771 | #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 |
||
| 772 | #define TIM_DMABase_CCER TIM_DMABASE_CCER |
||
| 773 | #define TIM_DMABase_CNT TIM_DMABASE_CNT |
||
| 774 | #define TIM_DMABase_PSC TIM_DMABASE_PSC |
||
| 775 | #define TIM_DMABase_ARR TIM_DMABASE_ARR |
||
| 776 | #define TIM_DMABase_RCR TIM_DMABASE_RCR |
||
| 777 | #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 |
||
| 778 | #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 |
||
| 779 | #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 |
||
| 780 | #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 |
||
| 781 | #define TIM_DMABase_BDTR TIM_DMABASE_BDTR |
||
| 782 | #define TIM_DMABase_DCR TIM_DMABASE_DCR |
||
| 783 | #define TIM_DMABase_DMAR TIM_DMABASE_DMAR |
||
| 784 | #define TIM_DMABase_OR1 TIM_DMABASE_OR1 |
||
| 785 | #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 |
||
| 786 | #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 |
||
| 787 | #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 |
||
| 788 | #define TIM_DMABase_OR2 TIM_DMABASE_OR2 |
||
| 789 | #define TIM_DMABase_OR3 TIM_DMABASE_OR3 |
||
| 790 | #define TIM_DMABase_OR TIM_DMABASE_OR |
||
| 791 | |||
| 792 | #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE |
||
| 793 | #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 |
||
| 794 | #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 |
||
| 795 | #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 |
||
| 796 | #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 |
||
| 797 | #define TIM_EventSource_COM TIM_EVENTSOURCE_COM |
||
| 798 | #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER |
||
| 799 | #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK |
||
| 800 | #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 |
||
| 801 | |||
| 802 | #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER |
||
| 803 | #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS |
||
| 804 | #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS |
||
| 805 | #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS |
||
| 806 | #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS |
||
| 807 | #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS |
||
| 808 | #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS |
||
| 809 | #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS |
||
| 810 | #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS |
||
| 811 | #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS |
||
| 812 | #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS |
||
| 813 | #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS |
||
| 814 | #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS |
||
| 815 | #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS |
||
| 816 | #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS |
||
| 817 | #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS |
||
| 818 | #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS |
||
| 819 | #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS |
||
| 820 | |||
| 821 | /** |
||
| 822 | * @} |
||
| 823 | */ |
||
| 824 | |||
| 825 | /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose |
||
| 826 | * @{ |
||
| 827 | */ |
||
| 828 | #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING |
||
| 829 | #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING |
||
| 830 | /** |
||
| 831 | * @} |
||
| 832 | */ |
||
| 833 | |||
| 834 | /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose |
||
| 835 | * @{ |
||
| 836 | */ |
||
| 837 | #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE |
||
| 838 | #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE |
||
| 839 | #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE |
||
| 840 | #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE |
||
| 841 | |||
| 842 | #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE |
||
| 843 | #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE |
||
| 844 | |||
| 845 | #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 |
||
| 846 | #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 |
||
| 847 | #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 |
||
| 848 | #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 |
||
| 849 | |||
| 850 | #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 |
||
| 851 | #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 |
||
| 852 | #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 |
||
| 853 | #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 |
||
| 854 | |||
| 855 | #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE |
||
| 856 | #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK |
||
| 857 | |||
| 858 | /** |
||
| 859 | * @} |
||
| 860 | */ |
||
| 861 | |||
| 862 | |||
| 863 | /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose |
||
| 864 | * @{ |
||
| 865 | */ |
||
| 866 | |||
| 867 | #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE |
||
| 868 | #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE |
||
| 869 | |||
| 870 | #define USARTNACK_ENABLED USART_NACK_ENABLE |
||
| 871 | #define USARTNACK_DISABLED USART_NACK_DISABLE |
||
| 872 | /** |
||
| 873 | * @} |
||
| 874 | */ |
||
| 875 | |||
| 876 | /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose |
||
| 877 | * @{ |
||
| 878 | */ |
||
| 879 | #define CFR_BASE WWDG_CFR_BASE |
||
| 880 | |||
| 881 | /** |
||
| 882 | * @} |
||
| 883 | */ |
||
| 884 | |||
| 885 | /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose |
||
| 886 | * @{ |
||
| 887 | */ |
||
| 888 | #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 |
||
| 889 | #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 |
||
| 890 | #define CAN_IT_RQCP0 CAN_IT_TME |
||
| 891 | #define CAN_IT_RQCP1 CAN_IT_TME |
||
| 892 | #define CAN_IT_RQCP2 CAN_IT_TME |
||
| 893 | #define INAK_TIMEOUT CAN_TIMEOUT_VALUE |
||
| 894 | #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE |
||
| 895 | #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) |
||
| 896 | #define CAN_TXSTATUS_OK ((uint8_t)0x01U) |
||
| 897 | #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) |
||
| 898 | |||
| 899 | /** |
||
| 900 | * @} |
||
| 901 | */ |
||
| 902 | |||
| 903 | /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose |
||
| 904 | * @{ |
||
| 905 | */ |
||
| 906 | |||
| 907 | #define VLAN_TAG ETH_VLAN_TAG |
||
| 908 | #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD |
||
| 909 | #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD |
||
| 910 | #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD |
||
| 911 | #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK |
||
| 912 | #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK |
||
| 913 | #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK |
||
| 914 | #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK |
||
| 915 | |||
| 916 | #define ETH_MMCCR ((uint32_t)0x00000100U) |
||
| 917 | #define ETH_MMCRIR ((uint32_t)0x00000104U) |
||
| 918 | #define ETH_MMCTIR ((uint32_t)0x00000108U) |
||
| 919 | #define ETH_MMCRIMR ((uint32_t)0x0000010CU) |
||
| 920 | #define ETH_MMCTIMR ((uint32_t)0x00000110U) |
||
| 921 | #define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) |
||
| 922 | #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) |
||
| 923 | #define ETH_MMCTGFCR ((uint32_t)0x00000168U) |
||
| 924 | #define ETH_MMCRFCECR ((uint32_t)0x00000194U) |
||
| 925 | #define ETH_MMCRFAECR ((uint32_t)0x00000198U) |
||
| 926 | #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) |
||
| 927 | |||
| 928 | #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ |
||
| 929 | #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ |
||
| 930 | #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ |
||
| 931 | #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ |
||
| 932 | #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ |
||
| 933 | #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ |
||
| 934 | #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ |
||
| 935 | #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ |
||
| 936 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ |
||
| 937 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ |
||
| 938 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ |
||
| 939 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ |
||
| 940 | #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ |
||
| 941 | #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ |
||
| 942 | #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ |
||
| 943 | #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ |
||
| 944 | #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ |
||
| 945 | #if defined(STM32F1) |
||
| 946 | #else |
||
| 947 | #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ |
||
| 948 | #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ |
||
| 949 | #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ |
||
| 950 | #endif |
||
| 951 | #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ |
||
| 952 | #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ |
||
| 953 | #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ |
||
| 954 | #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ |
||
| 955 | #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ |
||
| 956 | #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ |
||
| 957 | #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ |
||
| 958 | |||
| 959 | /** |
||
| 960 | * @} |
||
| 961 | */ |
||
| 962 | |||
| 963 | /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose |
||
| 964 | * @{ |
||
| 965 | */ |
||
| 966 | #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR |
||
| 967 | #define DCMI_IT_OVF DCMI_IT_OVR |
||
| 968 | #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI |
||
| 969 | #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI |
||
| 970 | |||
| 971 | #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop |
||
| 972 | #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop |
||
| 973 | #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop |
||
| 974 | |||
| 975 | /** |
||
| 976 | * @} |
||
| 977 | */ |
||
| 978 | |||
| 979 | #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ |
||
| 980 | defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) |
||
| 981 | /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose |
||
| 982 | * @{ |
||
| 983 | */ |
||
| 984 | #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 |
||
| 985 | #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 |
||
| 986 | #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 |
||
| 987 | #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 |
||
| 988 | #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 |
||
| 989 | |||
| 990 | #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 |
||
| 991 | #define CM_RGB888 DMA2D_INPUT_RGB888 |
||
| 992 | #define CM_RGB565 DMA2D_INPUT_RGB565 |
||
| 993 | #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 |
||
| 994 | #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 |
||
| 995 | #define CM_L8 DMA2D_INPUT_L8 |
||
| 996 | #define CM_AL44 DMA2D_INPUT_AL44 |
||
| 997 | #define CM_AL88 DMA2D_INPUT_AL88 |
||
| 998 | #define CM_L4 DMA2D_INPUT_L4 |
||
| 999 | #define CM_A8 DMA2D_INPUT_A8 |
||
| 1000 | #define CM_A4 DMA2D_INPUT_A4 |
||
| 1001 | /** |
||
| 1002 | * @} |
||
| 1003 | */ |
||
| 1004 | #endif /* STM32L4xx || STM32F7*/ |
||
| 1005 | |||
| 1006 | /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose |
||
| 1007 | * @{ |
||
| 1008 | */ |
||
| 1009 | |||
| 1010 | /** |
||
| 1011 | * @} |
||
| 1012 | */ |
||
| 1013 | |||
| 1014 | /* Exported functions --------------------------------------------------------*/ |
||
| 1015 | |||
| 1016 | /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose |
||
| 1017 | * @{ |
||
| 1018 | */ |
||
| 1019 | #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback |
||
| 1020 | /** |
||
| 1021 | * @} |
||
| 1022 | */ |
||
| 1023 | |||
| 1024 | /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose |
||
| 1025 | * @{ |
||
| 1026 | */ |
||
| 1027 | #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef |
||
| 1028 | #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef |
||
| 1029 | #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish |
||
| 1030 | #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish |
||
| 1031 | #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish |
||
| 1032 | #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish |
||
| 1033 | |||
| 1034 | /*HASH Algorithm Selection*/ |
||
| 1035 | |||
| 1036 | #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 |
||
| 1037 | #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 |
||
| 1038 | #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 |
||
| 1039 | #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 |
||
| 1040 | |||
| 1041 | #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH |
||
| 1042 | #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC |
||
| 1043 | |||
| 1044 | #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY |
||
| 1045 | #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY |
||
| 1046 | /** |
||
| 1047 | * @} |
||
| 1048 | */ |
||
| 1049 | |||
| 1050 | /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose |
||
| 1051 | * @{ |
||
| 1052 | */ |
||
| 1053 | #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode |
||
| 1054 | #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode |
||
| 1055 | #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode |
||
| 1056 | #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode |
||
| 1057 | #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode |
||
| 1058 | #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode |
||
| 1059 | #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) |
||
| 1060 | #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect |
||
| 1061 | #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) |
||
| 1062 | #if defined(STM32L0) |
||
| 1063 | #else |
||
| 1064 | #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) |
||
| 1065 | #endif |
||
| 1066 | #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) |
||
| 1067 | #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) |
||
| 1068 | /** |
||
| 1069 | * @} |
||
| 1070 | */ |
||
| 1071 | |||
| 1072 | /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose |
||
| 1073 | * @{ |
||
| 1074 | */ |
||
| 1075 | #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram |
||
| 1076 | #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown |
||
| 1077 | #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown |
||
| 1078 | #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock |
||
| 1079 | #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock |
||
| 1080 | #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase |
||
| 1081 | #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program |
||
| 1082 | |||
| 1083 | /** |
||
| 1084 | * @} |
||
| 1085 | */ |
||
| 1086 | |||
| 1087 | /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose |
||
| 1088 | * @{ |
||
| 1089 | */ |
||
| 1090 | #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter |
||
| 1091 | #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter |
||
| 1092 | #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter |
||
| 1093 | #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter |
||
| 1094 | |||
| 1095 | #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) |
||
| 1096 | /** |
||
| 1097 | * @} |
||
| 1098 | */ |
||
| 1099 | |||
| 1100 | /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose |
||
| 1101 | * @{ |
||
| 1102 | */ |
||
| 1103 | #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD |
||
| 1104 | #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg |
||
| 1105 | #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown |
||
| 1106 | #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor |
||
| 1107 | #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg |
||
| 1108 | #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown |
||
| 1109 | #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor |
||
| 1110 | #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler |
||
| 1111 | #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD |
||
| 1112 | #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler |
||
| 1113 | #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback |
||
| 1114 | #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive |
||
| 1115 | #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive |
||
| 1116 | #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC |
||
| 1117 | #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC |
||
| 1118 | #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM |
||
| 1119 | |||
| 1120 | #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL |
||
| 1121 | #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING |
||
| 1122 | #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING |
||
| 1123 | #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING |
||
| 1124 | #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING |
||
| 1125 | #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING |
||
| 1126 | #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING |
||
| 1127 | |||
| 1128 | #define CR_OFFSET_BB PWR_CR_OFFSET_BB |
||
| 1129 | #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB |
||
| 1130 | |||
| 1131 | #define DBP_BitNumber DBP_BIT_NUMBER |
||
| 1132 | #define PVDE_BitNumber PVDE_BIT_NUMBER |
||
| 1133 | #define PMODE_BitNumber PMODE_BIT_NUMBER |
||
| 1134 | #define EWUP_BitNumber EWUP_BIT_NUMBER |
||
| 1135 | #define FPDS_BitNumber FPDS_BIT_NUMBER |
||
| 1136 | #define ODEN_BitNumber ODEN_BIT_NUMBER |
||
| 1137 | #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER |
||
| 1138 | #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER |
||
| 1139 | #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER |
||
| 1140 | #define BRE_BitNumber BRE_BIT_NUMBER |
||
| 1141 | |||
| 1142 | #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL |
||
| 1143 | |||
| 1144 | /** |
||
| 1145 | * @} |
||
| 1146 | */ |
||
| 1147 | |||
| 1148 | /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose |
||
| 1149 | * @{ |
||
| 1150 | */ |
||
| 1151 | #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT |
||
| 1152 | #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback |
||
| 1153 | #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback |
||
| 1154 | /** |
||
| 1155 | * @} |
||
| 1156 | */ |
||
| 1157 | |||
| 1158 | /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose |
||
| 1159 | * @{ |
||
| 1160 | */ |
||
| 1161 | #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo |
||
| 1162 | /** |
||
| 1163 | * @} |
||
| 1164 | */ |
||
| 1165 | |||
| 1166 | /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose |
||
| 1167 | * @{ |
||
| 1168 | */ |
||
| 1169 | #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt |
||
| 1170 | #define HAL_TIM_DMAError TIM_DMAError |
||
| 1171 | #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt |
||
| 1172 | #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt |
||
| 1173 | /** |
||
| 1174 | * @} |
||
| 1175 | */ |
||
| 1176 | |||
| 1177 | /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose |
||
| 1178 | * @{ |
||
| 1179 | */ |
||
| 1180 | #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback |
||
| 1181 | /** |
||
| 1182 | * @} |
||
| 1183 | */ |
||
| 1184 | |||
| 1185 | /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose |
||
| 1186 | * @{ |
||
| 1187 | */ |
||
| 1188 | #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback |
||
| 1189 | /** |
||
| 1190 | * @} |
||
| 1191 | */ |
||
| 1192 | |||
| 1193 | |||
| 1194 | /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose |
||
| 1195 | * @{ |
||
| 1196 | */ |
||
| 1197 | |||
| 1198 | /** |
||
| 1199 | * @} |
||
| 1200 | */ |
||
| 1201 | |||
| 1202 | /* Exported macros ------------------------------------------------------------*/ |
||
| 1203 | |||
| 1204 | /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose |
||
| 1205 | * @{ |
||
| 1206 | */ |
||
| 1207 | #define AES_IT_CC CRYP_IT_CC |
||
| 1208 | #define AES_IT_ERR CRYP_IT_ERR |
||
| 1209 | #define AES_FLAG_CCF CRYP_FLAG_CCF |
||
| 1210 | /** |
||
| 1211 | * @} |
||
| 1212 | */ |
||
| 1213 | |||
| 1214 | /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose |
||
| 1215 | * @{ |
||
| 1216 | */ |
||
| 1217 | #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE |
||
| 1218 | #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH |
||
| 1219 | #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH |
||
| 1220 | #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM |
||
| 1221 | #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC |
||
| 1222 | #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM |
||
| 1223 | #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC |
||
| 1224 | #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI |
||
| 1225 | #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK |
||
| 1226 | #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG |
||
| 1227 | #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG |
||
| 1228 | #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE |
||
| 1229 | #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE |
||
| 1230 | |||
| 1231 | #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY |
||
| 1232 | #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 |
||
| 1233 | #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS |
||
| 1234 | #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER |
||
| 1235 | #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER |
||
| 1236 | |||
| 1237 | /** |
||
| 1238 | * @} |
||
| 1239 | */ |
||
| 1240 | |||
| 1241 | |||
| 1242 | /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose |
||
| 1243 | * @{ |
||
| 1244 | */ |
||
| 1245 | #define __ADC_ENABLE __HAL_ADC_ENABLE |
||
| 1246 | #define __ADC_DISABLE __HAL_ADC_DISABLE |
||
| 1247 | #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS |
||
| 1248 | #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS |
||
| 1249 | #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE |
||
| 1250 | #define __ADC_IS_ENABLED ADC_IS_ENABLE |
||
| 1251 | #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR |
||
| 1252 | #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED |
||
| 1253 | #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED |
||
| 1254 | #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR |
||
| 1255 | #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED |
||
| 1256 | #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING |
||
| 1257 | #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE |
||
| 1258 | |||
| 1259 | #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION |
||
| 1260 | #define __HAL_ADC_JSQR_RK ADC_JSQR_RK |
||
| 1261 | #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT |
||
| 1262 | #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR |
||
| 1263 | #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION |
||
| 1264 | #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE |
||
| 1265 | #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS |
||
| 1266 | #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS |
||
| 1267 | #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM |
||
| 1268 | #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT |
||
| 1269 | #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS |
||
| 1270 | #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN |
||
| 1271 | #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ |
||
| 1272 | #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET |
||
| 1273 | #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET |
||
| 1274 | #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL |
||
| 1275 | #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL |
||
| 1276 | #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET |
||
| 1277 | #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET |
||
| 1278 | #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD |
||
| 1279 | |||
| 1280 | #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION |
||
| 1281 | #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION |
||
| 1282 | #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION |
||
| 1283 | #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER |
||
| 1284 | #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI |
||
| 1285 | #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE |
||
| 1286 | #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE |
||
| 1287 | #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER |
||
| 1288 | #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER |
||
| 1289 | #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE |
||
| 1290 | |||
| 1291 | #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT |
||
| 1292 | #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT |
||
| 1293 | #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL |
||
| 1294 | #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM |
||
| 1295 | #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET |
||
| 1296 | #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE |
||
| 1297 | #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE |
||
| 1298 | #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER |
||
| 1299 | |||
| 1300 | #define __HAL_ADC_SQR1 ADC_SQR1 |
||
| 1301 | #define __HAL_ADC_SMPR1 ADC_SMPR1 |
||
| 1302 | #define __HAL_ADC_SMPR2 ADC_SMPR2 |
||
| 1303 | #define __HAL_ADC_SQR3_RK ADC_SQR3_RK |
||
| 1304 | #define __HAL_ADC_SQR2_RK ADC_SQR2_RK |
||
| 1305 | #define __HAL_ADC_SQR1_RK ADC_SQR1_RK |
||
| 1306 | #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS |
||
| 1307 | #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS |
||
| 1308 | #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV |
||
| 1309 | #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection |
||
| 1310 | #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq |
||
| 1311 | #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION |
||
| 1312 | #define __HAL_ADC_JSQR ADC_JSQR |
||
| 1313 | |||
| 1314 | #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL |
||
| 1315 | #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS |
||
| 1316 | #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF |
||
| 1317 | #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT |
||
| 1318 | #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS |
||
| 1319 | #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN |
||
| 1320 | #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR |
||
| 1321 | #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ |
||
| 1322 | |||
| 1323 | /** |
||
| 1324 | * @} |
||
| 1325 | */ |
||
| 1326 | |||
| 1327 | /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose |
||
| 1328 | * @{ |
||
| 1329 | */ |
||
| 1330 | #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT |
||
| 1331 | #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT |
||
| 1332 | #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT |
||
| 1333 | #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE |
||
| 1334 | |||
| 1335 | /** |
||
| 1336 | * @} |
||
| 1337 | */ |
||
| 1338 | |||
| 1339 | /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose |
||
| 1340 | * @{ |
||
| 1341 | */ |
||
| 1342 | #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 |
||
| 1343 | #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 |
||
| 1344 | #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 |
||
| 1345 | #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 |
||
| 1346 | #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 |
||
| 1347 | #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 |
||
| 1348 | #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 |
||
| 1349 | #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 |
||
| 1350 | #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 |
||
| 1351 | #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 |
||
| 1352 | #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 |
||
| 1353 | #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 |
||
| 1354 | #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 |
||
| 1355 | #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 |
||
| 1356 | #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 |
||
| 1357 | #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 |
||
| 1358 | |||
| 1359 | #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 |
||
| 1360 | #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 |
||
| 1361 | #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 |
||
| 1362 | #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 |
||
| 1363 | #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 |
||
| 1364 | #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 |
||
| 1365 | #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 |
||
| 1366 | #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 |
||
| 1367 | #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 |
||
| 1368 | #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 |
||
| 1369 | #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 |
||
| 1370 | #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 |
||
| 1371 | #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 |
||
| 1372 | #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 |
||
| 1373 | |||
| 1374 | |||
| 1375 | #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 |
||
| 1376 | #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 |
||
| 1377 | #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 |
||
| 1378 | #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 |
||
| 1379 | #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 |
||
| 1380 | #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 |
||
| 1381 | #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC |
||
| 1382 | #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC |
||
| 1383 | #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG |
||
| 1384 | #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG |
||
| 1385 | #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG |
||
| 1386 | #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG |
||
| 1387 | #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT |
||
| 1388 | #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT |
||
| 1389 | #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT |
||
| 1390 | #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT |
||
| 1391 | #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT |
||
| 1392 | #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT |
||
| 1393 | #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 |
||
| 1394 | #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 |
||
| 1395 | #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 |
||
| 1396 | #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 |
||
| 1397 | #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 |
||
| 1398 | #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 |
||
| 1399 | |||
| 1400 | /** |
||
| 1401 | * @} |
||
| 1402 | */ |
||
| 1403 | |||
| 1404 | /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose |
||
| 1405 | * @{ |
||
| 1406 | */ |
||
| 1407 | #if defined(STM32F3) |
||
| 1408 | #define COMP_START __HAL_COMP_ENABLE |
||
| 1409 | #define COMP_STOP __HAL_COMP_DISABLE |
||
| 1410 | #define COMP_LOCK __HAL_COMP_LOCK |
||
| 1411 | |||
| 1412 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
||
| 1413 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1414 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1415 | __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) |
||
| 1416 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1417 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1418 | __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) |
||
| 1419 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1420 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1421 | __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) |
||
| 1422 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1423 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1424 | __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) |
||
| 1425 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ |
||
| 1426 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ |
||
| 1427 | __HAL_COMP_COMP6_EXTI_ENABLE_IT()) |
||
| 1428 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ |
||
| 1429 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ |
||
| 1430 | __HAL_COMP_COMP6_EXTI_DISABLE_IT()) |
||
| 1431 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ |
||
| 1432 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ |
||
| 1433 | __HAL_COMP_COMP6_EXTI_GET_FLAG()) |
||
| 1434 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ |
||
| 1435 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ |
||
| 1436 | __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) |
||
| 1437 | # endif |
||
| 1438 | # if defined(STM32F302xE) || defined(STM32F302xC) |
||
| 1439 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1440 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1441 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1442 | __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) |
||
| 1443 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1444 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1445 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1446 | __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) |
||
| 1447 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1448 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1449 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1450 | __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) |
||
| 1451 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1452 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1453 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1454 | __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) |
||
| 1455 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
||
| 1456 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ |
||
| 1457 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ |
||
| 1458 | __HAL_COMP_COMP6_EXTI_ENABLE_IT()) |
||
| 1459 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
||
| 1460 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ |
||
| 1461 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ |
||
| 1462 | __HAL_COMP_COMP6_EXTI_DISABLE_IT()) |
||
| 1463 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
||
| 1464 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ |
||
| 1465 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ |
||
| 1466 | __HAL_COMP_COMP6_EXTI_GET_FLAG()) |
||
| 1467 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
||
| 1468 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ |
||
| 1469 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ |
||
| 1470 | __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) |
||
| 1471 | # endif |
||
| 1472 | # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) |
||
| 1473 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1474 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1475 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1476 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1477 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1478 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1479 | __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) |
||
| 1480 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1481 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1482 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1483 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1484 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1485 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1486 | __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) |
||
| 1487 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1488 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1489 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1490 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1491 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1492 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1493 | __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) |
||
| 1494 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1495 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1496 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1497 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1498 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1499 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1500 | __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) |
||
| 1501 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
||
| 1502 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ |
||
| 1503 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ |
||
| 1504 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ |
||
| 1505 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ |
||
| 1506 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ |
||
| 1507 | __HAL_COMP_COMP7_EXTI_ENABLE_IT()) |
||
| 1508 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
||
| 1509 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ |
||
| 1510 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ |
||
| 1511 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ |
||
| 1512 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ |
||
| 1513 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ |
||
| 1514 | __HAL_COMP_COMP7_EXTI_DISABLE_IT()) |
||
| 1515 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
||
| 1516 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ |
||
| 1517 | ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ |
||
| 1518 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ |
||
| 1519 | ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ |
||
| 1520 | ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ |
||
| 1521 | __HAL_COMP_COMP7_EXTI_GET_FLAG()) |
||
| 1522 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
||
| 1523 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ |
||
| 1524 | ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ |
||
| 1525 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ |
||
| 1526 | ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ |
||
| 1527 | ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ |
||
| 1528 | __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) |
||
| 1529 | # endif |
||
| 1530 | # if defined(STM32F373xC) ||defined(STM32F378xx) |
||
| 1531 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1532 | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) |
||
| 1533 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1534 | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) |
||
| 1535 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1536 | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) |
||
| 1537 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1538 | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) |
||
| 1539 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
||
| 1540 | __HAL_COMP_COMP2_EXTI_ENABLE_IT()) |
||
| 1541 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
||
| 1542 | __HAL_COMP_COMP2_EXTI_DISABLE_IT()) |
||
| 1543 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
||
| 1544 | __HAL_COMP_COMP2_EXTI_GET_FLAG()) |
||
| 1545 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
||
| 1546 | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) |
||
| 1547 | # endif |
||
| 1548 | #else |
||
| 1549 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
||
| 1550 | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) |
||
| 1551 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
||
| 1552 | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) |
||
| 1553 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
||
| 1554 | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) |
||
| 1555 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
||
| 1556 | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) |
||
| 1557 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
||
| 1558 | __HAL_COMP_COMP2_EXTI_ENABLE_IT()) |
||
| 1559 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
||
| 1560 | __HAL_COMP_COMP2_EXTI_DISABLE_IT()) |
||
| 1561 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
||
| 1562 | __HAL_COMP_COMP2_EXTI_GET_FLAG()) |
||
| 1563 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
||
| 1564 | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) |
||
| 1565 | #endif |
||
| 1566 | |||
| 1567 | #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE |
||
| 1568 | |||
| 1569 | #if defined(STM32L0) || defined(STM32L4) |
||
| 1570 | /* Note: On these STM32 families, the only argument of this macro */ |
||
| 1571 | /* is COMP_FLAG_LOCK. */ |
||
| 1572 | /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ |
||
| 1573 | /* argument. */ |
||
| 1574 | #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) |
||
| 1575 | #endif |
||
| 1576 | /** |
||
| 1577 | * @} |
||
| 1578 | */ |
||
| 1579 | |||
| 1580 | #if defined(STM32L0) || defined(STM32L4) |
||
| 1581 | /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose |
||
| 1582 | * @{ |
||
| 1583 | */ |
||
| 1584 | #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ |
||
| 1585 | #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ |
||
| 1586 | /** |
||
| 1587 | * @} |
||
| 1588 | */ |
||
| 1589 | #endif |
||
| 1590 | |||
| 1591 | /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose |
||
| 1592 | * @{ |
||
| 1593 | */ |
||
| 1594 | |||
| 1595 | #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ |
||
| 1596 | ((WAVE) == DAC_WAVE_NOISE)|| \ |
||
| 1597 | ((WAVE) == DAC_WAVE_TRIANGLE)) |
||
| 1598 | |||
| 1599 | /** |
||
| 1600 | * @} |
||
| 1601 | */ |
||
| 1602 | |||
| 1603 | /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose |
||
| 1604 | * @{ |
||
| 1605 | */ |
||
| 1606 | |||
| 1607 | #define IS_WRPAREA IS_OB_WRPAREA |
||
| 1608 | #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM |
||
| 1609 | #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM |
||
| 1610 | #define IS_TYPEERASE IS_FLASH_TYPEERASE |
||
| 1611 | #define IS_NBSECTORS IS_FLASH_NBSECTORS |
||
| 1612 | #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE |
||
| 1613 | |||
| 1614 | /** |
||
| 1615 | * @} |
||
| 1616 | */ |
||
| 1617 | |||
| 1618 | /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose |
||
| 1619 | * @{ |
||
| 1620 | */ |
||
| 1621 | |||
| 1622 | #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 |
||
| 1623 | #define __HAL_I2C_GENERATE_START I2C_GENERATE_START |
||
| 1624 | #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE |
||
| 1625 | #define __HAL_I2C_RISE_TIME I2C_RISE_TIME |
||
| 1626 | #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD |
||
| 1627 | #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST |
||
| 1628 | #define __HAL_I2C_SPEED I2C_SPEED |
||
| 1629 | #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE |
||
| 1630 | #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ |
||
| 1631 | #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS |
||
| 1632 | #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE |
||
| 1633 | #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ |
||
| 1634 | #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB |
||
| 1635 | #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB |
||
| 1636 | #define __HAL_I2C_FREQRANGE I2C_FREQRANGE |
||
| 1637 | /** |
||
| 1638 | * @} |
||
| 1639 | */ |
||
| 1640 | |||
| 1641 | /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose |
||
| 1642 | * @{ |
||
| 1643 | */ |
||
| 1644 | |||
| 1645 | #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE |
||
| 1646 | #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT |
||
| 1647 | |||
| 1648 | /** |
||
| 1649 | * @} |
||
| 1650 | */ |
||
| 1651 | |||
| 1652 | /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose |
||
| 1653 | * @{ |
||
| 1654 | */ |
||
| 1655 | |||
| 1656 | #define __IRDA_DISABLE __HAL_IRDA_DISABLE |
||
| 1657 | #define __IRDA_ENABLE __HAL_IRDA_ENABLE |
||
| 1658 | |||
| 1659 | #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE |
||
| 1660 | #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION |
||
| 1661 | #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE |
||
| 1662 | #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION |
||
| 1663 | |||
| 1664 | #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE |
||
| 1665 | |||
| 1666 | |||
| 1667 | /** |
||
| 1668 | * @} |
||
| 1669 | */ |
||
| 1670 | |||
| 1671 | |||
| 1672 | /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose |
||
| 1673 | * @{ |
||
| 1674 | */ |
||
| 1675 | #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS |
||
| 1676 | #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS |
||
| 1677 | /** |
||
| 1678 | * @} |
||
| 1679 | */ |
||
| 1680 | |||
| 1681 | |||
| 1682 | /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose |
||
| 1683 | * @{ |
||
| 1684 | */ |
||
| 1685 | |||
| 1686 | #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT |
||
| 1687 | #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT |
||
| 1688 | #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE |
||
| 1689 | |||
| 1690 | /** |
||
| 1691 | * @} |
||
| 1692 | */ |
||
| 1693 | |||
| 1694 | |||
| 1695 | /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose |
||
| 1696 | * @{ |
||
| 1697 | */ |
||
| 1698 | #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD |
||
| 1699 | #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX |
||
| 1700 | #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX |
||
| 1701 | #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX |
||
| 1702 | #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX |
||
| 1703 | #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L |
||
| 1704 | #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H |
||
| 1705 | #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM |
||
| 1706 | #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES |
||
| 1707 | #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX |
||
| 1708 | #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT |
||
| 1709 | #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION |
||
| 1710 | #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET |
||
| 1711 | |||
| 1712 | /** |
||
| 1713 | * @} |
||
| 1714 | */ |
||
| 1715 | |||
| 1716 | |||
| 1717 | /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose |
||
| 1718 | * @{ |
||
| 1719 | */ |
||
| 1720 | #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT |
||
| 1721 | #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT |
||
| 1722 | #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE |
||
| 1723 | #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE |
||
| 1724 | #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE |
||
| 1725 | #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE |
||
| 1726 | #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE |
||
| 1727 | #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE |
||
| 1728 | #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE |
||
| 1729 | #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE |
||
| 1730 | #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE |
||
| 1731 | #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE |
||
| 1732 | #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine |
||
| 1733 | #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine |
||
| 1734 | #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig |
||
| 1735 | #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig |
||
| 1736 | #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) |
||
| 1737 | #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT |
||
| 1738 | #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT |
||
| 1739 | #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE |
||
| 1740 | #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE |
||
| 1741 | #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE |
||
| 1742 | #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE |
||
| 1743 | #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE |
||
| 1744 | #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE |
||
| 1745 | #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) |
||
| 1746 | #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) |
||
| 1747 | #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention |
||
| 1748 | #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention |
||
| 1749 | #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 |
||
| 1750 | #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 |
||
| 1751 | #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE |
||
| 1752 | #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE |
||
| 1753 | #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB |
||
| 1754 | #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB |
||
| 1755 | |||
| 1756 | #if defined (STM32F4) |
||
| 1757 | #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() |
||
| 1758 | #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() |
||
| 1759 | #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() |
||
| 1760 | #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() |
||
| 1761 | #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() |
||
| 1762 | #else |
||
| 1763 | #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG |
||
| 1764 | #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT |
||
| 1765 | #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT |
||
| 1766 | #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT |
||
| 1767 | #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG |
||
| 1768 | #endif /* STM32F4 */ |
||
| 1769 | /** |
||
| 1770 | * @} |
||
| 1771 | */ |
||
| 1772 | |||
| 1773 | |||
| 1774 | /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose |
||
| 1775 | * @{ |
||
| 1776 | */ |
||
| 1777 | |||
| 1778 | #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI |
||
| 1779 | #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI |
||
| 1780 | |||
| 1781 | #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback |
||
| 1782 | #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) |
||
| 1783 | |||
| 1784 | #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE |
||
| 1785 | #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE |
||
| 1786 | #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE |
||
| 1787 | #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE |
||
| 1788 | #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET |
||
| 1789 | #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET |
||
| 1790 | #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE |
||
| 1791 | #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE |
||
| 1792 | #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET |
||
| 1793 | #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET |
||
| 1794 | #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE |
||
| 1795 | #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE |
||
| 1796 | #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE |
||
| 1797 | #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE |
||
| 1798 | #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET |
||
| 1799 | #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET |
||
| 1800 | #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE |
||
| 1801 | #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE |
||
| 1802 | #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET |
||
| 1803 | #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET |
||
| 1804 | #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE |
||
| 1805 | #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE |
||
| 1806 | #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE |
||
| 1807 | #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE |
||
| 1808 | #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET |
||
| 1809 | #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET |
||
| 1810 | #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE |
||
| 1811 | #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE |
||
| 1812 | #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE |
||
| 1813 | #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE |
||
| 1814 | #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET |
||
| 1815 | #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET |
||
| 1816 | #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE |
||
| 1817 | #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE |
||
| 1818 | #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET |
||
| 1819 | #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET |
||
| 1820 | #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET |
||
| 1821 | #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET |
||
| 1822 | #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET |
||
| 1823 | #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET |
||
| 1824 | #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET |
||
| 1825 | #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET |
||
| 1826 | #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET |
||
| 1827 | #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET |
||
| 1828 | #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET |
||
| 1829 | #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET |
||
| 1830 | #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET |
||
| 1831 | #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET |
||
| 1832 | #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE |
||
| 1833 | #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE |
||
| 1834 | #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET |
||
| 1835 | #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET |
||
| 1836 | #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE |
||
| 1837 | #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE |
||
| 1838 | #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE |
||
| 1839 | #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE |
||
| 1840 | #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET |
||
| 1841 | #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET |
||
| 1842 | #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE |
||
| 1843 | #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE |
||
| 1844 | #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET |
||
| 1845 | #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET |
||
| 1846 | #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE |
||
| 1847 | #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE |
||
| 1848 | #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET |
||
| 1849 | #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET |
||
| 1850 | #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE |
||
| 1851 | #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE |
||
| 1852 | #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE |
||
| 1853 | #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE |
||
| 1854 | #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET |
||
| 1855 | #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET |
||
| 1856 | #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE |
||
| 1857 | #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE |
||
| 1858 | #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET |
||
| 1859 | #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET |
||
| 1860 | #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE |
||
| 1861 | #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE |
||
| 1862 | #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE |
||
| 1863 | #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE |
||
| 1864 | #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET |
||
| 1865 | #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET |
||
| 1866 | #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE |
||
| 1867 | #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE |
||
| 1868 | #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET |
||
| 1869 | #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET |
||
| 1870 | #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE |
||
| 1871 | #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE |
||
| 1872 | #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE |
||
| 1873 | #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE |
||
| 1874 | #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET |
||
| 1875 | #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET |
||
| 1876 | #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE |
||
| 1877 | #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE |
||
| 1878 | #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET |
||
| 1879 | #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET |
||
| 1880 | #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE |
||
| 1881 | #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE |
||
| 1882 | #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE |
||
| 1883 | #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE |
||
| 1884 | #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET |
||
| 1885 | #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET |
||
| 1886 | #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE |
||
| 1887 | #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE |
||
| 1888 | #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE |
||
| 1889 | #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE |
||
| 1890 | #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET |
||
| 1891 | #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET |
||
| 1892 | #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE |
||
| 1893 | #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE |
||
| 1894 | #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE |
||
| 1895 | #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE |
||
| 1896 | #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET |
||
| 1897 | #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET |
||
| 1898 | #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE |
||
| 1899 | #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE |
||
| 1900 | #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET |
||
| 1901 | #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET |
||
| 1902 | #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE |
||
| 1903 | #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE |
||
| 1904 | #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE |
||
| 1905 | #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE |
||
| 1906 | #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE |
||
| 1907 | #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE |
||
| 1908 | #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE |
||
| 1909 | #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE |
||
| 1910 | #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE |
||
| 1911 | #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE |
||
| 1912 | #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET |
||
| 1913 | #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET |
||
| 1914 | #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE |
||
| 1915 | #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE |
||
| 1916 | #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET |
||
| 1917 | #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET |
||
| 1918 | #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE |
||
| 1919 | #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE |
||
| 1920 | #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE |
||
| 1921 | #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE |
||
| 1922 | #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE |
||
| 1923 | #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE |
||
| 1924 | #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET |
||
| 1925 | #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET |
||
| 1926 | #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE |
||
| 1927 | #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE |
||
| 1928 | #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE |
||
| 1929 | #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE |
||
| 1930 | #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE |
||
| 1931 | #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE |
||
| 1932 | #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET |
||
| 1933 | #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET |
||
| 1934 | #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE |
||
| 1935 | #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE |
||
| 1936 | #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE |
||
| 1937 | #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE |
||
| 1938 | #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET |
||
| 1939 | #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET |
||
| 1940 | #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE |
||
| 1941 | #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE |
||
| 1942 | #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE |
||
| 1943 | #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE |
||
| 1944 | #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET |
||
| 1945 | #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET |
||
| 1946 | #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE |
||
| 1947 | #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE |
||
| 1948 | #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE |
||
| 1949 | #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE |
||
| 1950 | #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET |
||
| 1951 | #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET |
||
| 1952 | #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE |
||
| 1953 | #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE |
||
| 1954 | #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE |
||
| 1955 | #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE |
||
| 1956 | #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET |
||
| 1957 | #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET |
||
| 1958 | #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE |
||
| 1959 | #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE |
||
| 1960 | #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE |
||
| 1961 | #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE |
||
| 1962 | #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET |
||
| 1963 | #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET |
||
| 1964 | #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE |
||
| 1965 | #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE |
||
| 1966 | #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE |
||
| 1967 | #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE |
||
| 1968 | #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET |
||
| 1969 | #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET |
||
| 1970 | #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE |
||
| 1971 | #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE |
||
| 1972 | #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE |
||
| 1973 | #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE |
||
| 1974 | #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET |
||
| 1975 | #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET |
||
| 1976 | #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE |
||
| 1977 | #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE |
||
| 1978 | #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE |
||
| 1979 | #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE |
||
| 1980 | #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET |
||
| 1981 | #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET |
||
| 1982 | #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE |
||
| 1983 | #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE |
||
| 1984 | #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE |
||
| 1985 | #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE |
||
| 1986 | #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET |
||
| 1987 | #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET |
||
| 1988 | #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE |
||
| 1989 | #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE |
||
| 1990 | #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE |
||
| 1991 | #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE |
||
| 1992 | #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET |
||
| 1993 | #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET |
||
| 1994 | #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE |
||
| 1995 | #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE |
||
| 1996 | #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE |
||
| 1997 | #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE |
||
| 1998 | #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET |
||
| 1999 | #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET |
||
| 2000 | #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE |
||
| 2001 | #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE |
||
| 2002 | #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE |
||
| 2003 | #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE |
||
| 2004 | #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET |
||
| 2005 | #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET |
||
| 2006 | #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE |
||
| 2007 | #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE |
||
| 2008 | #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE |
||
| 2009 | #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE |
||
| 2010 | #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET |
||
| 2011 | #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET |
||
| 2012 | #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE |
||
| 2013 | #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE |
||
| 2014 | #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE |
||
| 2015 | #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE |
||
| 2016 | #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET |
||
| 2017 | #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET |
||
| 2018 | #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE |
||
| 2019 | #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE |
||
| 2020 | #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE |
||
| 2021 | #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE |
||
| 2022 | #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET |
||
| 2023 | #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET |
||
| 2024 | #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE |
||
| 2025 | #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE |
||
| 2026 | #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE |
||
| 2027 | #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE |
||
| 2028 | #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET |
||
| 2029 | #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET |
||
| 2030 | #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE |
||
| 2031 | #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE |
||
| 2032 | #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE |
||
| 2033 | #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE |
||
| 2034 | #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET |
||
| 2035 | #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET |
||
| 2036 | #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE |
||
| 2037 | #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE |
||
| 2038 | #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE |
||
| 2039 | #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE |
||
| 2040 | #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET |
||
| 2041 | #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET |
||
| 2042 | #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE |
||
| 2043 | #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE |
||
| 2044 | #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE |
||
| 2045 | #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE |
||
| 2046 | #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET |
||
| 2047 | #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET |
||
| 2048 | #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE |
||
| 2049 | #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE |
||
| 2050 | #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE |
||
| 2051 | #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE |
||
| 2052 | #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET |
||
| 2053 | #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET |
||
| 2054 | #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE |
||
| 2055 | #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE |
||
| 2056 | #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE |
||
| 2057 | #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE |
||
| 2058 | #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET |
||
| 2059 | #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET |
||
| 2060 | #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE |
||
| 2061 | #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE |
||
| 2062 | #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE |
||
| 2063 | #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE |
||
| 2064 | #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE |
||
| 2065 | #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE |
||
| 2066 | #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET |
||
| 2067 | #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET |
||
| 2068 | #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE |
||
| 2069 | #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE |
||
| 2070 | #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE |
||
| 2071 | #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE |
||
| 2072 | #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET |
||
| 2073 | #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET |
||
| 2074 | #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE |
||
| 2075 | #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE |
||
| 2076 | #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE |
||
| 2077 | #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE |
||
| 2078 | #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET |
||
| 2079 | #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET |
||
| 2080 | #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE |
||
| 2081 | #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE |
||
| 2082 | #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE |
||
| 2083 | #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE |
||
| 2084 | #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET |
||
| 2085 | #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET |
||
| 2086 | #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE |
||
| 2087 | #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE |
||
| 2088 | #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE |
||
| 2089 | #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE |
||
| 2090 | #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE |
||
| 2091 | #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE |
||
| 2092 | #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE |
||
| 2093 | #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE |
||
| 2094 | #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE |
||
| 2095 | #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE |
||
| 2096 | #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET |
||
| 2097 | #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET |
||
| 2098 | #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE |
||
| 2099 | #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE |
||
| 2100 | #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE |
||
| 2101 | #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE |
||
| 2102 | #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET |
||
| 2103 | #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET |
||
| 2104 | #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE |
||
| 2105 | #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE |
||
| 2106 | #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE |
||
| 2107 | #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE |
||
| 2108 | #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET |
||
| 2109 | #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET |
||
| 2110 | #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE |
||
| 2111 | #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE |
||
| 2112 | #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET |
||
| 2113 | #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET |
||
| 2114 | #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE |
||
| 2115 | #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE |
||
| 2116 | #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET |
||
| 2117 | #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET |
||
| 2118 | #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE |
||
| 2119 | #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE |
||
| 2120 | #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET |
||
| 2121 | #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET |
||
| 2122 | #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE |
||
| 2123 | #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE |
||
| 2124 | #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET |
||
| 2125 | #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET |
||
| 2126 | #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE |
||
| 2127 | #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE |
||
| 2128 | #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET |
||
| 2129 | #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET |
||
| 2130 | #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE |
||
| 2131 | #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE |
||
| 2132 | #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE |
||
| 2133 | #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE |
||
| 2134 | #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET |
||
| 2135 | #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET |
||
| 2136 | #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE |
||
| 2137 | #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE |
||
| 2138 | #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE |
||
| 2139 | #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE |
||
| 2140 | #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET |
||
| 2141 | #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET |
||
| 2142 | #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE |
||
| 2143 | #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE |
||
| 2144 | #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE |
||
| 2145 | #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE |
||
| 2146 | #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET |
||
| 2147 | #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET |
||
| 2148 | #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE |
||
| 2149 | #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE |
||
| 2150 | #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE |
||
| 2151 | #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE |
||
| 2152 | #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET |
||
| 2153 | #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET |
||
| 2154 | #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE |
||
| 2155 | #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE |
||
| 2156 | #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE |
||
| 2157 | #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE |
||
| 2158 | #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET |
||
| 2159 | #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET |
||
| 2160 | #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE |
||
| 2161 | #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE |
||
| 2162 | #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE |
||
| 2163 | #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE |
||
| 2164 | #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET |
||
| 2165 | #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET |
||
| 2166 | #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE |
||
| 2167 | #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE |
||
| 2168 | #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE |
||
| 2169 | #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE |
||
| 2170 | #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET |
||
| 2171 | #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET |
||
| 2172 | #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE |
||
| 2173 | #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE |
||
| 2174 | #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE |
||
| 2175 | #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE |
||
| 2176 | #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET |
||
| 2177 | #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET |
||
| 2178 | #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE |
||
| 2179 | #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE |
||
| 2180 | #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE |
||
| 2181 | #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE |
||
| 2182 | #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET |
||
| 2183 | #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET |
||
| 2184 | #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE |
||
| 2185 | #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE |
||
| 2186 | #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE |
||
| 2187 | #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE |
||
| 2188 | #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET |
||
| 2189 | #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET |
||
| 2190 | #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE |
||
| 2191 | #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE |
||
| 2192 | #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET |
||
| 2193 | #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET |
||
| 2194 | #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE |
||
| 2195 | #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE |
||
| 2196 | #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE |
||
| 2197 | #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE |
||
| 2198 | #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET |
||
| 2199 | #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET |
||
| 2200 | #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE |
||
| 2201 | #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE |
||
| 2202 | #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE |
||
| 2203 | #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE |
||
| 2204 | #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET |
||
| 2205 | #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET |
||
| 2206 | #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE |
||
| 2207 | #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE |
||
| 2208 | #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE |
||
| 2209 | #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE |
||
| 2210 | #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET |
||
| 2211 | #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET |
||
| 2212 | #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE |
||
| 2213 | #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE |
||
| 2214 | #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE |
||
| 2215 | #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE |
||
| 2216 | #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET |
||
| 2217 | #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET |
||
| 2218 | #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE |
||
| 2219 | #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE |
||
| 2220 | #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE |
||
| 2221 | #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE |
||
| 2222 | #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET |
||
| 2223 | #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET |
||
| 2224 | #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE |
||
| 2225 | #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE |
||
| 2226 | #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE |
||
| 2227 | #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE |
||
| 2228 | #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET |
||
| 2229 | #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET |
||
| 2230 | #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE |
||
| 2231 | #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE |
||
| 2232 | #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE |
||
| 2233 | #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE |
||
| 2234 | #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET |
||
| 2235 | #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET |
||
| 2236 | #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE |
||
| 2237 | #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE |
||
| 2238 | #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE |
||
| 2239 | #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE |
||
| 2240 | #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET |
||
| 2241 | #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET |
||
| 2242 | #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE |
||
| 2243 | #define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE |
||
| 2244 | #define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET |
||
| 2245 | #define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET |
||
| 2246 | #define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE |
||
| 2247 | #define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE |
||
| 2248 | #define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET |
||
| 2249 | #define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET |
||
| 2250 | #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE |
||
| 2251 | #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE |
||
| 2252 | #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET |
||
| 2253 | #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE |
||
| 2254 | #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE |
||
| 2255 | #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE |
||
| 2256 | #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE |
||
| 2257 | #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET |
||
| 2258 | #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE |
||
| 2259 | #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE |
||
| 2260 | #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE |
||
| 2261 | #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE |
||
| 2262 | #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET |
||
| 2263 | #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET |
||
| 2264 | #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE |
||
| 2265 | #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE |
||
| 2266 | #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET |
||
| 2267 | #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET |
||
| 2268 | #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE |
||
| 2269 | #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE |
||
| 2270 | #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE |
||
| 2271 | #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE |
||
| 2272 | #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET |
||
| 2273 | #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET |
||
| 2274 | #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE |
||
| 2275 | #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE |
||
| 2276 | #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE |
||
| 2277 | #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE |
||
| 2278 | #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE |
||
| 2279 | #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE |
||
| 2280 | #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET |
||
| 2281 | #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET |
||
| 2282 | #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE |
||
| 2283 | #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE |
||
| 2284 | |||
| 2285 | #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET |
||
| 2286 | #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET |
||
| 2287 | #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE |
||
| 2288 | #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE |
||
| 2289 | #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE |
||
| 2290 | #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE |
||
| 2291 | #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE |
||
| 2292 | #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE |
||
| 2293 | #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE |
||
| 2294 | #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE |
||
| 2295 | #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE |
||
| 2296 | #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE |
||
| 2297 | #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE |
||
| 2298 | #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE |
||
| 2299 | #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE |
||
| 2300 | #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE |
||
| 2301 | #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE |
||
| 2302 | #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE |
||
| 2303 | #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE |
||
| 2304 | #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET |
||
| 2305 | #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET |
||
| 2306 | #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE |
||
| 2307 | #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE |
||
| 2308 | #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE |
||
| 2309 | #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE |
||
| 2310 | #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE |
||
| 2311 | #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET |
||
| 2312 | #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET |
||
| 2313 | #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE |
||
| 2314 | #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE |
||
| 2315 | #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE |
||
| 2316 | #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE |
||
| 2317 | #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET |
||
| 2318 | #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET |
||
| 2319 | #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE |
||
| 2320 | #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE |
||
| 2321 | #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE |
||
| 2322 | #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE |
||
| 2323 | #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET |
||
| 2324 | #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET |
||
| 2325 | #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE |
||
| 2326 | #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE |
||
| 2327 | #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE |
||
| 2328 | #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE |
||
| 2329 | #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE |
||
| 2330 | #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE |
||
| 2331 | #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE |
||
| 2332 | #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE |
||
| 2333 | #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE |
||
| 2334 | #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE |
||
| 2335 | #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE |
||
| 2336 | #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE |
||
| 2337 | #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE |
||
| 2338 | #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE |
||
| 2339 | #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE |
||
| 2340 | #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE |
||
| 2341 | #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE |
||
| 2342 | #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE |
||
| 2343 | #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE |
||
| 2344 | #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE |
||
| 2345 | #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE |
||
| 2346 | #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET |
||
| 2347 | #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET |
||
| 2348 | #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE |
||
| 2349 | #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE |
||
| 2350 | #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE |
||
| 2351 | #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE |
||
| 2352 | #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET |
||
| 2353 | #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET |
||
| 2354 | #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE |
||
| 2355 | #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE |
||
| 2356 | #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE |
||
| 2357 | #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE |
||
| 2358 | #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET |
||
| 2359 | #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET |
||
| 2360 | #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE |
||
| 2361 | #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE |
||
| 2362 | #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE |
||
| 2363 | #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE |
||
| 2364 | #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET |
||
| 2365 | #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET |
||
| 2366 | #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE |
||
| 2367 | #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE |
||
| 2368 | #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE |
||
| 2369 | #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE |
||
| 2370 | #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET |
||
| 2371 | #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE |
||
| 2372 | #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE |
||
| 2373 | #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE |
||
| 2374 | #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE |
||
| 2375 | #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE |
||
| 2376 | #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE |
||
| 2377 | #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET |
||
| 2378 | #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET |
||
| 2379 | #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE |
||
| 2380 | #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE |
||
| 2381 | #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE |
||
| 2382 | #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE |
||
| 2383 | #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET |
||
| 2384 | #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET |
||
| 2385 | #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE |
||
| 2386 | #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE |
||
| 2387 | #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE |
||
| 2388 | #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE |
||
| 2389 | #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET |
||
| 2390 | #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET |
||
| 2391 | #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE |
||
| 2392 | #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE |
||
| 2393 | #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE |
||
| 2394 | #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE |
||
| 2395 | #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET |
||
| 2396 | #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET |
||
| 2397 | #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE |
||
| 2398 | #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE |
||
| 2399 | #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE |
||
| 2400 | #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE |
||
| 2401 | #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED |
||
| 2402 | #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED |
||
| 2403 | #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET |
||
| 2404 | #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET |
||
| 2405 | #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE |
||
| 2406 | #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE |
||
| 2407 | #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED |
||
| 2408 | #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED |
||
| 2409 | #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET |
||
| 2410 | #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE |
||
| 2411 | #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE |
||
| 2412 | #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE |
||
| 2413 | #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE |
||
| 2414 | #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE |
||
| 2415 | #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE |
||
| 2416 | #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE |
||
| 2417 | #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE |
||
| 2418 | #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE |
||
| 2419 | #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET |
||
| 2420 | #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET |
||
| 2421 | #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE |
||
| 2422 | #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE |
||
| 2423 | #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET |
||
| 2424 | #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET |
||
| 2425 | #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE |
||
| 2426 | #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE |
||
| 2427 | #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE |
||
| 2428 | #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE |
||
| 2429 | #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET |
||
| 2430 | #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET |
||
| 2431 | #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE |
||
| 2432 | #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE |
||
| 2433 | |||
| 2434 | /* alias define maintained for legacy */ |
||
| 2435 | #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET |
||
| 2436 | #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET |
||
| 2437 | |||
| 2438 | #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE |
||
| 2439 | #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE |
||
| 2440 | #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE |
||
| 2441 | #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE |
||
| 2442 | #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE |
||
| 2443 | #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE |
||
| 2444 | #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE |
||
| 2445 | #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE |
||
| 2446 | #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE |
||
| 2447 | #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE |
||
| 2448 | #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE |
||
| 2449 | #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE |
||
| 2450 | #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE |
||
| 2451 | #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE |
||
| 2452 | #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE |
||
| 2453 | #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE |
||
| 2454 | #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE |
||
| 2455 | #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE |
||
| 2456 | #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE |
||
| 2457 | #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE |
||
| 2458 | #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE |
||
| 2459 | #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE |
||
| 2460 | |||
| 2461 | #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET |
||
| 2462 | #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET |
||
| 2463 | #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET |
||
| 2464 | #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET |
||
| 2465 | #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET |
||
| 2466 | #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET |
||
| 2467 | #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET |
||
| 2468 | #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET |
||
| 2469 | #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET |
||
| 2470 | #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET |
||
| 2471 | #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET |
||
| 2472 | #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET |
||
| 2473 | #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET |
||
| 2474 | #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET |
||
| 2475 | #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET |
||
| 2476 | #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET |
||
| 2477 | #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET |
||
| 2478 | #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET |
||
| 2479 | #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET |
||
| 2480 | #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET |
||
| 2481 | #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET |
||
| 2482 | #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET |
||
| 2483 | |||
| 2484 | #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED |
||
| 2485 | #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED |
||
| 2486 | #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED |
||
| 2487 | #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED |
||
| 2488 | #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED |
||
| 2489 | #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED |
||
| 2490 | #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED |
||
| 2491 | #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED |
||
| 2492 | #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED |
||
| 2493 | #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED |
||
| 2494 | #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED |
||
| 2495 | #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED |
||
| 2496 | #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED |
||
| 2497 | #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED |
||
| 2498 | #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED |
||
| 2499 | #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED |
||
| 2500 | #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED |
||
| 2501 | #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED |
||
| 2502 | #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED |
||
| 2503 | #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED |
||
| 2504 | #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED |
||
| 2505 | #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED |
||
| 2506 | #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED |
||
| 2507 | #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED |
||
| 2508 | #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED |
||
| 2509 | #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED |
||
| 2510 | #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED |
||
| 2511 | #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED |
||
| 2512 | #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED |
||
| 2513 | #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED |
||
| 2514 | #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED |
||
| 2515 | #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED |
||
| 2516 | #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED |
||
| 2517 | #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED |
||
| 2518 | #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED |
||
| 2519 | #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED |
||
| 2520 | #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED |
||
| 2521 | #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED |
||
| 2522 | #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED |
||
| 2523 | #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED |
||
| 2524 | #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED |
||
| 2525 | #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED |
||
| 2526 | #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED |
||
| 2527 | #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED |
||
| 2528 | #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED |
||
| 2529 | #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED |
||
| 2530 | #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED |
||
| 2531 | #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED |
||
| 2532 | #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED |
||
| 2533 | #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED |
||
| 2534 | #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED |
||
| 2535 | #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED |
||
| 2536 | #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED |
||
| 2537 | #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED |
||
| 2538 | #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED |
||
| 2539 | #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED |
||
| 2540 | #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED |
||
| 2541 | #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED |
||
| 2542 | #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED |
||
| 2543 | #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED |
||
| 2544 | #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED |
||
| 2545 | #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED |
||
| 2546 | #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED |
||
| 2547 | #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED |
||
| 2548 | #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED |
||
| 2549 | #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED |
||
| 2550 | #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED |
||
| 2551 | #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED |
||
| 2552 | #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED |
||
| 2553 | #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED |
||
| 2554 | #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED |
||
| 2555 | #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED |
||
| 2556 | #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED |
||
| 2557 | #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED |
||
| 2558 | #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED |
||
| 2559 | #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED |
||
| 2560 | #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED |
||
| 2561 | #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED |
||
| 2562 | #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED |
||
| 2563 | #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED |
||
| 2564 | #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED |
||
| 2565 | #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED |
||
| 2566 | #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED |
||
| 2567 | #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED |
||
| 2568 | #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED |
||
| 2569 | #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED |
||
| 2570 | #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED |
||
| 2571 | #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED |
||
| 2572 | #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED |
||
| 2573 | #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED |
||
| 2574 | #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED |
||
| 2575 | #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED |
||
| 2576 | #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED |
||
| 2577 | #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED |
||
| 2578 | #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED |
||
| 2579 | #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED |
||
| 2580 | #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED |
||
| 2581 | #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED |
||
| 2582 | #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED |
||
| 2583 | #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED |
||
| 2584 | #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED |
||
| 2585 | #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED |
||
| 2586 | #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED |
||
| 2587 | #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED |
||
| 2588 | #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED |
||
| 2589 | #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED |
||
| 2590 | #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED |
||
| 2591 | #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED |
||
| 2592 | #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED |
||
| 2593 | #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED |
||
| 2594 | #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED |
||
| 2595 | #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED |
||
| 2596 | #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED |
||
| 2597 | #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED |
||
| 2598 | #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED |
||
| 2599 | #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED |
||
| 2600 | |||
| 2601 | #if defined(STM32F4) |
||
| 2602 | #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET |
||
| 2603 | #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET |
||
| 2604 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE |
||
| 2605 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE |
||
| 2606 | #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE |
||
| 2607 | #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE |
||
| 2608 | #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED |
||
| 2609 | #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED |
||
| 2610 | #define Sdmmc1ClockSelection SdioClockSelection |
||
| 2611 | #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO |
||
| 2612 | #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 |
||
| 2613 | #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK |
||
| 2614 | #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG |
||
| 2615 | #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE |
||
| 2616 | #endif |
||
| 2617 | |||
| 2618 | #if defined(STM32F7) || defined(STM32L4) |
||
| 2619 | #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET |
||
| 2620 | #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET |
||
| 2621 | #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE |
||
| 2622 | #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE |
||
| 2623 | #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE |
||
| 2624 | #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE |
||
| 2625 | #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED |
||
| 2626 | #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED |
||
| 2627 | #define SdioClockSelection Sdmmc1ClockSelection |
||
| 2628 | #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 |
||
| 2629 | #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG |
||
| 2630 | #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE |
||
| 2631 | #endif |
||
| 2632 | |||
| 2633 | #if defined(STM32F7) |
||
| 2634 | #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 |
||
| 2635 | #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK |
||
| 2636 | #endif |
||
| 2637 | |||
| 2638 | #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG |
||
| 2639 | #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG |
||
| 2640 | |||
| 2641 | #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE |
||
| 2642 | |||
| 2643 | #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE |
||
| 2644 | #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE |
||
| 2645 | #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK |
||
| 2646 | #define IS_RCC_HCLK_DIV IS_RCC_PCLK |
||
| 2647 | #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK |
||
| 2648 | |||
| 2649 | #define RCC_IT_HSI14 RCC_IT_HSI14RDY |
||
| 2650 | |||
| 2651 | #if defined(STM32L0) |
||
| 2652 | #define RCC_IT_LSECSS RCC_IT_CSSLSE |
||
| 2653 | #define RCC_IT_CSS RCC_IT_CSSHSE |
||
| 2654 | #endif |
||
| 2655 | |||
| 2656 | #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE |
||
| 2657 | #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG |
||
| 2658 | #define RCC_MCO_NODIV RCC_MCODIV_1 |
||
| 2659 | #define RCC_MCO_DIV1 RCC_MCODIV_1 |
||
| 2660 | #define RCC_MCO_DIV2 RCC_MCODIV_2 |
||
| 2661 | #define RCC_MCO_DIV4 RCC_MCODIV_4 |
||
| 2662 | #define RCC_MCO_DIV8 RCC_MCODIV_8 |
||
| 2663 | #define RCC_MCO_DIV16 RCC_MCODIV_16 |
||
| 2664 | #define RCC_MCO_DIV32 RCC_MCODIV_32 |
||
| 2665 | #define RCC_MCO_DIV64 RCC_MCODIV_64 |
||
| 2666 | #define RCC_MCO_DIV128 RCC_MCODIV_128 |
||
| 2667 | #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK |
||
| 2668 | #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI |
||
| 2669 | #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE |
||
| 2670 | #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK |
||
| 2671 | #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI |
||
| 2672 | #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 |
||
| 2673 | #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 |
||
| 2674 | #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE |
||
| 2675 | #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK |
||
| 2676 | #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK |
||
| 2677 | #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 |
||
| 2678 | |||
| 2679 | #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK |
||
| 2680 | |||
| 2681 | #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 |
||
| 2682 | #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL |
||
| 2683 | #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI |
||
| 2684 | #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL |
||
| 2685 | #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL |
||
| 2686 | #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 |
||
| 2687 | #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 |
||
| 2688 | #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 |
||
| 2689 | |||
| 2690 | #define HSION_BitNumber RCC_HSION_BIT_NUMBER |
||
| 2691 | #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER |
||
| 2692 | #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER |
||
| 2693 | #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER |
||
| 2694 | #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER |
||
| 2695 | #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER |
||
| 2696 | #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER |
||
| 2697 | #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER |
||
| 2698 | #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER |
||
| 2699 | #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER |
||
| 2700 | #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER |
||
| 2701 | #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER |
||
| 2702 | #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER |
||
| 2703 | #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER |
||
| 2704 | #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER |
||
| 2705 | #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER |
||
| 2706 | #define LSION_BitNumber RCC_LSION_BIT_NUMBER |
||
| 2707 | #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER |
||
| 2708 | #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER |
||
| 2709 | #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER |
||
| 2710 | #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER |
||
| 2711 | #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER |
||
| 2712 | #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER |
||
| 2713 | #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER |
||
| 2714 | #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER |
||
| 2715 | #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER |
||
| 2716 | #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS |
||
| 2717 | #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS |
||
| 2718 | #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS |
||
| 2719 | #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS |
||
| 2720 | #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE |
||
| 2721 | #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE |
||
| 2722 | |||
| 2723 | #define CR_HSION_BB RCC_CR_HSION_BB |
||
| 2724 | #define CR_CSSON_BB RCC_CR_CSSON_BB |
||
| 2725 | #define CR_PLLON_BB RCC_CR_PLLON_BB |
||
| 2726 | #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB |
||
| 2727 | #define CR_MSION_BB RCC_CR_MSION_BB |
||
| 2728 | #define CSR_LSION_BB RCC_CSR_LSION_BB |
||
| 2729 | #define CSR_LSEON_BB RCC_CSR_LSEON_BB |
||
| 2730 | #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB |
||
| 2731 | #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB |
||
| 2732 | #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB |
||
| 2733 | #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB |
||
| 2734 | #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB |
||
| 2735 | #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB |
||
| 2736 | #define CR_HSEON_BB RCC_CR_HSEON_BB |
||
| 2737 | #define CSR_RMVF_BB RCC_CSR_RMVF_BB |
||
| 2738 | #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB |
||
| 2739 | #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB |
||
| 2740 | |||
| 2741 | #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE |
||
| 2742 | #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE |
||
| 2743 | #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE |
||
| 2744 | #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE |
||
| 2745 | #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE |
||
| 2746 | |||
| 2747 | #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT |
||
| 2748 | |||
| 2749 | #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN |
||
| 2750 | #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF |
||
| 2751 | |||
| 2752 | #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 |
||
| 2753 | #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ |
||
| 2754 | #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP |
||
| 2755 | #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ |
||
| 2756 | #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE |
||
| 2757 | #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 |
||
| 2758 | |||
| 2759 | #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE |
||
| 2760 | #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE |
||
| 2761 | #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED |
||
| 2762 | #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED |
||
| 2763 | #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET |
||
| 2764 | #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET |
||
| 2765 | #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE |
||
| 2766 | #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE |
||
| 2767 | #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED |
||
| 2768 | #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED |
||
| 2769 | #define DfsdmClockSelection Dfsdm1ClockSelection |
||
| 2770 | #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 |
||
| 2771 | #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK |
||
| 2772 | #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK |
||
| 2773 | #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG |
||
| 2774 | #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE |
||
| 2775 | |||
| 2776 | /** |
||
| 2777 | * @} |
||
| 2778 | */ |
||
| 2779 | |||
| 2780 | /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose |
||
| 2781 | * @{ |
||
| 2782 | */ |
||
| 2783 | #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) |
||
| 2784 | |||
| 2785 | /** |
||
| 2786 | * @} |
||
| 2787 | */ |
||
| 2788 | |||
| 2789 | /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose |
||
| 2790 | * @{ |
||
| 2791 | */ |
||
| 2792 | |||
| 2793 | #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG |
||
| 2794 | #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT |
||
| 2795 | #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT |
||
| 2796 | |||
| 2797 | #if defined (STM32F1) |
||
| 2798 | #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() |
||
| 2799 | |||
| 2800 | #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() |
||
| 2801 | |||
| 2802 | #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() |
||
| 2803 | |||
| 2804 | #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() |
||
| 2805 | |||
| 2806 | #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() |
||
| 2807 | #else |
||
| 2808 | #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ |
||
| 2809 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ |
||
| 2810 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) |
||
| 2811 | #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ |
||
| 2812 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ |
||
| 2813 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) |
||
| 2814 | #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ |
||
| 2815 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ |
||
| 2816 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) |
||
| 2817 | #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ |
||
| 2818 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ |
||
| 2819 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) |
||
| 2820 | #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ |
||
| 2821 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ |
||
| 2822 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) |
||
| 2823 | #endif /* STM32F1 */ |
||
| 2824 | |||
| 2825 | #define IS_ALARM IS_RTC_ALARM |
||
| 2826 | #define IS_ALARM_MASK IS_RTC_ALARM_MASK |
||
| 2827 | #define IS_TAMPER IS_RTC_TAMPER |
||
| 2828 | #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE |
||
| 2829 | #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER |
||
| 2830 | #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT |
||
| 2831 | #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE |
||
| 2832 | #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION |
||
| 2833 | #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE |
||
| 2834 | #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ |
||
| 2835 | #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION |
||
| 2836 | #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER |
||
| 2837 | #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK |
||
| 2838 | #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER |
||
| 2839 | |||
| 2840 | #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE |
||
| 2841 | #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE |
||
| 2842 | |||
| 2843 | /** |
||
| 2844 | * @} |
||
| 2845 | */ |
||
| 2846 | |||
| 2847 | /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose |
||
| 2848 | * @{ |
||
| 2849 | */ |
||
| 2850 | |||
| 2851 | #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE |
||
| 2852 | #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS |
||
| 2853 | |||
| 2854 | #if defined(STM32F4) |
||
| 2855 | #define SD_SDMMC_DISABLED SD_SDIO_DISABLED |
||
| 2856 | #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY |
||
| 2857 | #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED |
||
| 2858 | #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION |
||
| 2859 | #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND |
||
| 2860 | #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT |
||
| 2861 | #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED |
||
| 2862 | #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE |
||
| 2863 | #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE |
||
| 2864 | #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE |
||
| 2865 | #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL |
||
| 2866 | #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT |
||
| 2867 | #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT |
||
| 2868 | #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG |
||
| 2869 | #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG |
||
| 2870 | #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT |
||
| 2871 | #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT |
||
| 2872 | #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS |
||
| 2873 | #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT |
||
| 2874 | #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND |
||
| 2875 | /* alias CMSIS */ |
||
| 2876 | #define SDMMC1_IRQn SDIO_IRQn |
||
| 2877 | #define SDMMC1_IRQHandler SDIO_IRQHandler |
||
| 2878 | #endif |
||
| 2879 | |||
| 2880 | #if defined(STM32F7) || defined(STM32L4) |
||
| 2881 | #define SD_SDIO_DISABLED SD_SDMMC_DISABLED |
||
| 2882 | #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY |
||
| 2883 | #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED |
||
| 2884 | #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION |
||
| 2885 | #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND |
||
| 2886 | #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT |
||
| 2887 | #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED |
||
| 2888 | #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE |
||
| 2889 | #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE |
||
| 2890 | #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE |
||
| 2891 | #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE |
||
| 2892 | #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT |
||
| 2893 | #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT |
||
| 2894 | #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG |
||
| 2895 | #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG |
||
| 2896 | #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT |
||
| 2897 | #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT |
||
| 2898 | #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS |
||
| 2899 | #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT |
||
| 2900 | #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND |
||
| 2901 | /* alias CMSIS for compatibilities */ |
||
| 2902 | #define SDIO_IRQn SDMMC1_IRQn |
||
| 2903 | #define SDIO_IRQHandler SDMMC1_IRQHandler |
||
| 2904 | #endif |
||
| 2905 | /** |
||
| 2906 | * @} |
||
| 2907 | */ |
||
| 2908 | |||
| 2909 | /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose |
||
| 2910 | * @{ |
||
| 2911 | */ |
||
| 2912 | |||
| 2913 | #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT |
||
| 2914 | #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT |
||
| 2915 | #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE |
||
| 2916 | #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE |
||
| 2917 | #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE |
||
| 2918 | #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE |
||
| 2919 | |||
| 2920 | #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE |
||
| 2921 | #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE |
||
| 2922 | |||
| 2923 | #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE |
||
| 2924 | |||
| 2925 | /** |
||
| 2926 | * @} |
||
| 2927 | */ |
||
| 2928 | |||
| 2929 | /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose |
||
| 2930 | * @{ |
||
| 2931 | */ |
||
| 2932 | #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 |
||
| 2933 | #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 |
||
| 2934 | #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START |
||
| 2935 | #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH |
||
| 2936 | #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR |
||
| 2937 | #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE |
||
| 2938 | #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE |
||
| 2939 | #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED |
||
| 2940 | /** |
||
| 2941 | * @} |
||
| 2942 | */ |
||
| 2943 | |||
| 2944 | /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose |
||
| 2945 | * @{ |
||
| 2946 | */ |
||
| 2947 | |||
| 2948 | #define __HAL_SPI_1LINE_TX SPI_1LINE_TX |
||
| 2949 | #define __HAL_SPI_1LINE_RX SPI_1LINE_RX |
||
| 2950 | #define __HAL_SPI_RESET_CRC SPI_RESET_CRC |
||
| 2951 | |||
| 2952 | /** |
||
| 2953 | * @} |
||
| 2954 | */ |
||
| 2955 | |||
| 2956 | /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose |
||
| 2957 | * @{ |
||
| 2958 | */ |
||
| 2959 | |||
| 2960 | #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE |
||
| 2961 | #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION |
||
| 2962 | #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE |
||
| 2963 | #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION |
||
| 2964 | |||
| 2965 | #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD |
||
| 2966 | |||
| 2967 | #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE |
||
| 2968 | #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE |
||
| 2969 | |||
| 2970 | /** |
||
| 2971 | * @} |
||
| 2972 | */ |
||
| 2973 | |||
| 2974 | |||
| 2975 | /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose |
||
| 2976 | * @{ |
||
| 2977 | */ |
||
| 2978 | |||
| 2979 | #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT |
||
| 2980 | #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT |
||
| 2981 | #define __USART_ENABLE __HAL_USART_ENABLE |
||
| 2982 | #define __USART_DISABLE __HAL_USART_DISABLE |
||
| 2983 | |||
| 2984 | #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE |
||
| 2985 | #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE |
||
| 2986 | |||
| 2987 | /** |
||
| 2988 | * @} |
||
| 2989 | */ |
||
| 2990 | |||
| 2991 | /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose |
||
| 2992 | * @{ |
||
| 2993 | */ |
||
| 2994 | #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE |
||
| 2995 | |||
| 2996 | #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE |
||
| 2997 | #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE |
||
| 2998 | #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE |
||
| 2999 | #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE |
||
| 3000 | |||
| 3001 | #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE |
||
| 3002 | #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE |
||
| 3003 | #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE |
||
| 3004 | #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE |
||
| 3005 | |||
| 3006 | #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT |
||
| 3007 | #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT |
||
| 3008 | #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG |
||
| 3009 | #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG |
||
| 3010 | #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE |
||
| 3011 | #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE |
||
| 3012 | #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE |
||
| 3013 | |||
| 3014 | #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT |
||
| 3015 | #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT |
||
| 3016 | #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG |
||
| 3017 | #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG |
||
| 3018 | #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE |
||
| 3019 | #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE |
||
| 3020 | #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE |
||
| 3021 | #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT |
||
| 3022 | |||
| 3023 | #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT |
||
| 3024 | #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT |
||
| 3025 | #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG |
||
| 3026 | #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG |
||
| 3027 | #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE |
||
| 3028 | #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE |
||
| 3029 | #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE |
||
| 3030 | #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT |
||
| 3031 | |||
| 3032 | #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup |
||
| 3033 | #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup |
||
| 3034 | |||
| 3035 | #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo |
||
| 3036 | #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo |
||
| 3037 | /** |
||
| 3038 | * @} |
||
| 3039 | */ |
||
| 3040 | |||
| 3041 | /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose |
||
| 3042 | * @{ |
||
| 3043 | */ |
||
| 3044 | #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE |
||
| 3045 | #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE |
||
| 3046 | |||
| 3047 | #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE |
||
| 3048 | #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT |
||
| 3049 | |||
| 3050 | #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE |
||
| 3051 | |||
| 3052 | #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN |
||
| 3053 | #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER |
||
| 3054 | #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER |
||
| 3055 | #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER |
||
| 3056 | #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD |
||
| 3057 | #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD |
||
| 3058 | #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION |
||
| 3059 | #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION |
||
| 3060 | #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER |
||
| 3061 | #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER |
||
| 3062 | #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE |
||
| 3063 | #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE |
||
| 3064 | |||
| 3065 | #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 |
||
| 3066 | /** |
||
| 3067 | * @} |
||
| 3068 | */ |
||
| 3069 | |||
| 3070 | /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose |
||
| 3071 | * @{ |
||
| 3072 | */ |
||
| 3073 | |||
| 3074 | #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT |
||
| 3075 | #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT |
||
| 3076 | #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG |
||
| 3077 | #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG |
||
| 3078 | #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER |
||
| 3079 | #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER |
||
| 3080 | #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER |
||
| 3081 | |||
| 3082 | #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE |
||
| 3083 | #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE |
||
| 3084 | #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE |
||
| 3085 | /** |
||
| 3086 | * @} |
||
| 3087 | */ |
||
| 3088 | |||
| 3089 | /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose |
||
| 3090 | * @{ |
||
| 3091 | */ |
||
| 3092 | #define __HAL_LTDC_LAYER LTDC_LAYER |
||
| 3093 | /** |
||
| 3094 | * @} |
||
| 3095 | */ |
||
| 3096 | |||
| 3097 | /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose |
||
| 3098 | * @{ |
||
| 3099 | */ |
||
| 3100 | #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE |
||
| 3101 | #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE |
||
| 3102 | #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE |
||
| 3103 | #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE |
||
| 3104 | #define SAI_STREOMODE SAI_STEREOMODE |
||
| 3105 | #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY |
||
| 3106 | #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL |
||
| 3107 | #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL |
||
| 3108 | #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL |
||
| 3109 | #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL |
||
| 3110 | #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL |
||
| 3111 | #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE |
||
| 3112 | #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 |
||
| 3113 | #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE |
||
| 3114 | /** |
||
| 3115 | * @} |
||
| 3116 | */ |
||
| 3117 | |||
| 3118 | |||
| 3119 | /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose |
||
| 3120 | * @{ |
||
| 3121 | */ |
||
| 3122 | |||
| 3123 | /** |
||
| 3124 | * @} |
||
| 3125 | */ |
||
| 3126 | |||
| 3127 | #ifdef __cplusplus |
||
| 3128 | } |
||
| 3129 | #endif |
||
| 3130 | |||
| 3131 | #endif /* ___STM32_HAL_LEGACY */ |
||
| 3132 | |||
| 3133 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||
| 3134 |