WebSVN – DashDisplay – Blame – /branches/Dashboard_L152_v2/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xb.h

Rev	Author	Line No.	Line
30	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32l151xb.h
		4	* @author MCD Application Team
		5	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
		6	* This file contains all the peripheral register's definitions, bits
		7	* definitions and memory mapping for STM32L1xx devices.
		8	*
		9	* This file contains:
		10	* - Data structures and the address mapping for all peripherals
		11	* - Peripheral's registers declarations and bits definition
		12	* - Macros to access peripheral�s registers hardware
		13	*
		14	******************************************************************************
		15	* @attention
		16	*
50	mjames	17	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
		18	* All rights reserved.</center></h2>
30	mjames	19	*
50	mjames	20	* This software component is licensed by ST under BSD 3-Clause license,
		21	* the "License"; You may not use this file except in compliance with the
		22	* License. You may obtain a copy of the License at:
		23	* opensource.org/licenses/BSD-3-Clause
30	mjames	24	*
		25	******************************************************************************
		26	*/
		27
		28	/** @addtogroup CMSIS
		29	* @{
		30	*/
		31
		32	/** @addtogroup stm32l151xb
		33	* @{
		34	*/
		35
		36	#ifndef __STM32L151xB_H
		37	#define __STM32L151xB_H
		38
		39	#ifdef __cplusplus
		40	extern "C" {
		41	#endif
		42
		43
		44	/** @addtogroup Configuration_section_for_CMSIS
		45	* @{
		46	*/
		47	/**
		48	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
		49	*/
		50	#define __CM3_REV 0x200U /!< Cortex-M3 Revision r2p0 /
		51	#define __MPU_PRESENT 1U /!< STM32L1xx provides MPU /
		52	#define __NVIC_PRIO_BITS 4U /!< STM32L1xx uses 4 Bits for the Priority Levels /
		53	#define __Vendor_SysTickConfig 0U /!< Set to 1 if different SysTick Config is used /
		54
		55	/**
		56	* @}
		57	*/
		58
		59	/** @addtogroup Peripheral_interrupt_number_definition
		60	* @{
		61	*/
		62
		63	/**
		64	* @brief STM32L1xx Interrupt Number Definition, according to the selected device
		65	* in @ref Library_configuration_section
		66	*/
		67
		68	/!< Interrupt Number Definition /
		69	typedef enum
		70	{
		71	/**** Cortex-M3 Processor Exceptions Numbers ****************************************************/
		72	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
		73	HardFault_IRQn = -13, /!< 3 Cortex-M3 Hard Fault Interrupt /
		74	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
		75	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
		76	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
		77	SVC_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
		78	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
		79	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
		80	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
		81
		82	/**** STM32L specific Interrupt Numbers *********************************************************/
		83	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
		84	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
		85	TAMPER_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
		86	RTC_WKUP_IRQn = 3, /!< RTC Wakeup Timer through EXTI Line Interrupt /
		87	FLASH_IRQn = 4, /!< FLASH global Interrupt /
		88	RCC_IRQn = 5, /!< RCC global Interrupt /
		89	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
		90	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
		91	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
		92	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
		93	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
		94	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
		95	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
		96	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
		97	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
		98	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
		99	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
		100	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
		101	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
		102	USB_HP_IRQn = 19, /!< USB High Priority Interrupt /
		103	USB_LP_IRQn = 20, /!< USB Low Priority Interrupt /
		104	DAC_IRQn = 21, /!< DAC Interrupt /
		105	COMP_IRQn = 22, /!< Comparator through EXTI Line Interrupt /
		106	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
		107	TIM9_IRQn = 25, /!< TIM9 global Interrupt /
		108	TIM10_IRQn = 26, /!< TIM10 global Interrupt /
		109	TIM11_IRQn = 27, /!< TIM11 global Interrupt /
		110	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
		111	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
		112	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
		113	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
		114	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
		115	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
		116	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
		117	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
		118	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
		119	USART1_IRQn = 37, /!< USART1 global Interrupt /
		120	USART2_IRQn = 38, /!< USART2 global Interrupt /
		121	USART3_IRQn = 39, /!< USART3 global Interrupt /
		122	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
		123	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
		124	USB_FS_WKUP_IRQn = 42, /!< USB FS WakeUp from suspend through EXTI Line Interrupt /
		125	TIM6_IRQn = 43, /!< TIM6 global Interrupt /
		126	TIM7_IRQn = 44, /!< TIM7 global Interrupt /
		127	} IRQn_Type;
		128
		129	/**
		130	* @}
		131	*/
		132
		133	#include "core_cm3.h"
		134	#include "system_stm32l1xx.h"
		135	#include <stdint.h>
		136
		137	/** @addtogroup Peripheral_registers_structures
		138	* @{
		139	*/
		140
		141	/**
		142	* @brief Analog to Digital Converter
		143	*/
		144
		145	typedef struct
		146	{
		147	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
		148	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
		149	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
		150	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
		151	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
		152	__IO uint32_t SMPR3; /!< ADC sample time register 3, Address offset: 0x14 /
		153	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x18 /
		154	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x1C /
		155	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x20 /
		156	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x24 /
		157	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x28 /
		158	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x2C /
		159	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x30 /
		160	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x34 /
		161	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x38 /
		162	__IO uint32_t SQR4; /!< ADC regular sequence register 4, Address offset: 0x3C /
		163	__IO uint32_t SQR5; /!< ADC regular sequence register 5, Address offset: 0x40 /
		164	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x44 /
		165	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x48 /
		166	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x4C /
		167	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x50 /
		168	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x54 /
		169	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x58 /
		170	uint32_t RESERVED; /!< Reserved, Address offset: 0x5C /
		171	} ADC_TypeDef;
		172
		173	typedef struct
		174	{
		175	__IO uint32_t CSR; /!< ADC common status register, Address offset: ADC1 base address + 0x300 /
		176	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
		177	} ADC_Common_TypeDef;
		178
		179	/**
		180	* @brief Comparator
		181	*/
		182
		183	typedef struct
		184	{
		185	__IO uint32_t CSR; /!< COMP control and status register, Address offset: 0x00 /
		186	} COMP_TypeDef;
		187
		188	typedef struct
		189	{
		190	__IO uint32_t CSR; /!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 /
		191	} COMP_Common_TypeDef;
		192
		193	/**
		194	* @brief CRC calculation unit
		195	*/
		196
		197	typedef struct
		198	{
		199	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
		200	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
		201	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
		202	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
		203	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
		204	} CRC_TypeDef;
		205
		206	/**
		207	* @brief Digital to Analog Converter
		208	*/
		209
		210	typedef struct
		211	{
		212	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
		213	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
		214	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
		215	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
		216	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
		217	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
		218	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
		219	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
		220	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
		221	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
		222	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
		223	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
		224	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
		225	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
		226	} DAC_TypeDef;
		227
		228	/**
		229	* @brief Debug MCU
		230	*/
		231
		232	typedef struct
		233	{
		234	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
		235	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
		236	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
		237	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
		238	}DBGMCU_TypeDef;
		239
		240	/**
		241	* @brief DMA Controller
		242	*/
		243
		244	typedef struct
		245	{
		246	__IO uint32_t CCR; /!< DMA channel x configuration register /
		247	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
		248	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
		249	__IO uint32_t CMAR; /!< DMA channel x memory address register /
		250	} DMA_Channel_TypeDef;
		251
		252	typedef struct
		253	{
		254	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
		255	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
		256	} DMA_TypeDef;
		257
		258	/**
		259	* @brief External Interrupt/Event Controller
		260	*/
		261
		262	typedef struct
		263	{
		264	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
		265	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
		266	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
		267	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
		268	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
		269	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
		270	} EXTI_TypeDef;
		271
		272	/**
		273	* @brief FLASH Registers
		274	*/
		275	typedef struct
		276	{
		277	__IO uint32_t ACR; /!< Access control register, Address offset: 0x00 /
		278	__IO uint32_t PECR; /!< Program/erase control register, Address offset: 0x04 /
		279	__IO uint32_t PDKEYR; /!< Power down key register, Address offset: 0x08 /
		280	__IO uint32_t PEKEYR; /!< Program/erase key register, Address offset: 0x0c /
		281	__IO uint32_t PRGKEYR; /!< Program memory key register, Address offset: 0x10 /
		282	__IO uint32_t OPTKEYR; /!< Option byte key register, Address offset: 0x14 /
		283	__IO uint32_t SR; /!< Status register, Address offset: 0x18 /
		284	__IO uint32_t OBR; /!< Option byte register, Address offset: 0x1c /
		285	__IO uint32_t WRPR1; /!< Write protection register 1, Address offset: 0x20 /
		286	} FLASH_TypeDef;
		287
		288	/**
		289	* @brief Option Bytes Registers
		290	*/
		291	typedef struct
		292	{
		293	__IO uint32_t RDP; /!< Read protection register, Address offset: 0x00 /
		294	__IO uint32_t USER; /!< user register, Address offset: 0x04 /
		295	__IO uint32_t WRP01; /!< write protection register 0 1, Address offset: 0x08 /
		296	__IO uint32_t WRP23; /!< write protection register 2 3, Address offset: 0x0C /
		297	} OB_TypeDef;
		298
		299	/**
		300	* @brief General Purpose IO
		301	*/
		302
		303	typedef struct
		304	{
		305	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
		306	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
		307	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
		308	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
		309	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
		310	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
		311	__IO uint32_t BSRR; /!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 /
		312	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
		313	__IO uint32_t AFR[2]; /!< GPIO alternate function register, Address offset: 0x20-0x24 /
		314	} GPIO_TypeDef;
		315
		316	/**
		317	* @brief SysTem Configuration
		318	*/
		319
		320	typedef struct
		321	{
		322	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
		323	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
		324	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
		325	} SYSCFG_TypeDef;
		326
		327	/**
		328	* @brief Inter-integrated Circuit Interface
		329	*/
		330
		331	typedef struct
		332	{
		333	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
		334	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
		335	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
		336	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
		337	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
		338	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
		339	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
		340	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
		341	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
		342	} I2C_TypeDef;
		343
		344	/**
		345	* @brief Independent WATCHDOG
		346	*/
		347
		348	typedef struct
		349	{
		350	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
		351	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
		352	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
		353	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
		354	} IWDG_TypeDef;
		355
		356	/**
		357	* @brief Power Control
		358	*/
		359
		360	typedef struct
		361	{
		362	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
		363	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
		364	} PWR_TypeDef;
		365
		366	/**
		367	* @brief Reset and Clock Control
		368	*/
		369
		370	typedef struct
		371	{
		372	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
		373	__IO uint32_t ICSCR; /!< RCC Internal clock sources calibration register, Address offset: 0x04 /
		374	__IO uint32_t CFGR; /!< RCC Clock configuration register, Address offset: 0x08 /
		375	__IO uint32_t CIR; /!< RCC Clock interrupt register, Address offset: 0x0C /
		376	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x10 /
		377	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x14 /
		378	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x18 /
		379	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock enable register, Address offset: 0x1C /
		380	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x20 /
		381	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x24 /
		382	__IO uint32_t AHBLPENR; /!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 /
		383	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C /
		384	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 /
		385	__IO uint32_t CSR; /!< RCC Control/status register, Address offset: 0x34 /
		386	} RCC_TypeDef;
		387
		388	/**
		389	* @brief Routing Interface
		390	*/
		391
		392	typedef struct
		393	{
		394	__IO uint32_t ICR; /!< RI input capture register, Address offset: 0x00 /
50	mjames	395	__IO uint32_t ASCR1; /!< RI analog switches control register, Address offset: 0x04 /
		396	__IO uint32_t ASCR2; /!< RI analog switch control register 2, Address offset: 0x08 /
30	mjames	397	__IO uint32_t HYSCR1; /!< RI hysteresis control register, Address offset: 0x0C /
50	mjames	398	__IO uint32_t HYSCR2; /!< RI Hysteresis control register, Address offset: 0x10 /
		399	__IO uint32_t HYSCR3; /!< RI Hysteresis control register, Address offset: 0x14 /
		400	uint32_t RESERVED1; /!< Reserved, Address offset: 0x18 /
30	mjames	401	} RI_TypeDef;
		402
		403	/**
		404	* @brief Real-Time Clock
		405	*/
		406	typedef struct
		407	{
		408	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
		409	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
		410	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
		411	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
		412	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
		413	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
		414	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
		415	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
		416	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
		417	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
		418	uint32_t RESERVED1; /!< Reserved, 0x28 /
		419	uint32_t RESERVED2; /!< Reserved, 0x2C /
		420	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
		421	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
		422	uint32_t RESERVED3; /!< Reserved, 0x38 /
		423	uint32_t RESERVED4; /!< Reserved, 0x3C /
		424	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
		425	uint32_t RESERVED5; /!< Reserved, 0x44 /
		426	uint32_t RESERVED6; /!< Reserved, 0x48 /
		427	uint32_t RESERVED7; /!< Reserved, 0x4C /
		428	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
		429	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
		430	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
		431	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
		432	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
		433	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
		434	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
		435	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
		436	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
		437	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
		438	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
		439	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
		440	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
		441	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
		442	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
		443	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
		444	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
		445	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
		446	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
		447	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
		448	} RTC_TypeDef;
		449
		450	/**
		451	* @brief Serial Peripheral Interface
		452	*/
		453
		454	typedef struct
		455	{
		456	__IO uint32_t CR1; /!< SPI Control register 1 Address offset: 0x00 /
		457	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
		458	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
		459	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
		460	__IO uint32_t CRCPR; /!< SPI CRC polynomial register Address offset: 0x10 /
		461	__IO uint32_t RXCRCR; /!< SPI Rx CRC register Address offset: 0x14 /
		462	__IO uint32_t TXCRCR; /!< SPI Tx CRC register Address offset: 0x18 /
		463	} SPI_TypeDef;
		464
		465	/**
		466	* @brief TIM
		467	*/
		468	typedef struct
		469	{
		470	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
		471	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
		472	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
		473	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
		474	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
		475	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
		476	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
		477	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
		478	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
		479	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
		480	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
		481	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
		482	uint32_t RESERVED12; /!< Reserved, 0x30 /
		483	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
		484	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
		485	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
		486	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
		487	uint32_t RESERVED17; /!< Reserved, 0x44 /
		488	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
		489	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
		490	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
		491	} TIM_TypeDef;
		492	/**
		493	* @brief Universal Synchronous Asynchronous Receiver Transmitter
		494	*/
		495
		496	typedef struct
		497	{
		498	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
		499	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
		500	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
		501	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
		502	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
		503	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
		504	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
		505	} USART_TypeDef;
		506
		507	/**
		508	* @brief Universal Serial Bus Full Speed Device
		509	*/
		510
		511	typedef struct
		512	{
		513	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
		514	__IO uint16_t RESERVED0; /!< Reserved /
		515	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
		516	__IO uint16_t RESERVED1; /!< Reserved /
		517	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
		518	__IO uint16_t RESERVED2; /!< Reserved /
		519	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
		520	__IO uint16_t RESERVED3; /!< Reserved /
		521	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
		522	__IO uint16_t RESERVED4; /!< Reserved /
		523	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
		524	__IO uint16_t RESERVED5; /!< Reserved /
		525	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
		526	__IO uint16_t RESERVED6; /!< Reserved /
		527	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
		528	__IO uint16_t RESERVED7[17]; /!< Reserved /
		529	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
		530	__IO uint16_t RESERVED8; /!< Reserved /
		531	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
		532	__IO uint16_t RESERVED9; /!< Reserved /
		533	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
		534	__IO uint16_t RESERVEDA; /!< Reserved /
		535	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
		536	__IO uint16_t RESERVEDB; /!< Reserved /
		537	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
		538	__IO uint16_t RESERVEDC; /!< Reserved /
		539	} USB_TypeDef;
		540
		541	/**
		542	* @brief Window WATCHDOG
		543	*/
		544	typedef struct
		545	{
		546	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
		547	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
		548	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
		549	} WWDG_TypeDef;
		550
		551	/**
		552	* @brief Universal Serial Bus Full Speed Device
		553	*/
		554	/**
		555	* @}
		556	*/
		557
		558	/** @addtogroup Peripheral_memory_map
		559	* @{
		560	*/
		561
50	mjames	562	#define FLASH_BASE (0x08000000UL) /!< FLASH base address in the alias region /
		563	#define FLASH_EEPROM_BASE (FLASH_BASE + 0x80000UL) /!< FLASH EEPROM base address in the alias region /
		564	#define SRAM_BASE (0x20000000UL) /!< SRAM base address in the alias region /
		565	#define PERIPH_BASE (0x40000000UL) /!< Peripheral base address in the alias region /
		566	#define SRAM_BB_BASE (0x22000000UL) /!< SRAM base address in the bit-band region /
		567	#define PERIPH_BB_BASE (0x42000000UL) /!< Peripheral base address in the bit-band region /
		568	#define FLASH_END (0x0801FFFFUL) /!< Program end FLASH address for Cat1 & Cat2 /
		569	#define FLASH_EEPROM_END (0x08080FFFUL) /!< FLASH EEPROM end address (4KB) /
30	mjames	570
		571	/!< Peripheral memory map /
		572	#define APB1PERIPH_BASE PERIPH_BASE
50	mjames	573	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
		574	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
30	mjames	575
		576	/!< APB1 peripherals /
50	mjames	577	#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
		578	#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
		579	#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
		580	#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)
		581	#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)
		582	#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
		583	#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
		584	#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
		585	#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
		586	#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
		587	#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
		588	#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
		589	#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
30	mjames	590
		591	/* USB device FS */
50	mjames	592	#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /!< USB_IP Peripheral Registers base address /
		593	#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /!< USB_IP Packet Memory Area base address /
30	mjames	594
		595	/* USB device FS SRAM */
50	mjames	596	#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
		597	#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)
		598	#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00UL)
		599	#define RI_BASE (APB1PERIPH_BASE + 0x00007C04UL)
30	mjames	600
		601	/!< APB2 peripherals /
50	mjames	602	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL)
		603	#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
		604	#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800UL)
		605	#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00UL)
		606	#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000UL)
		607	#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
		608	#define ADC_BASE (APB2PERIPH_BASE + 0x00002700UL)
		609	#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
		610	#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
30	mjames	611
		612	/!< AHB peripherals /
50	mjames	613	#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000UL)
		614	#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400UL)
		615	#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800UL)
		616	#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00UL)
		617	#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000UL)
		618	#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400UL)
		619	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
		620	#define RCC_BASE (AHBPERIPH_BASE + 0x00003800UL)
		621	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00UL) /!< FLASH registers base address /
		622	#define OB_BASE (0x1FF80000UL) /!< FLASH Option Bytes base address /
		623	#define FLASHSIZE_BASE (0x1FF8004CUL) /!< FLASH Size register base address for Cat.1 and Cat.2 devices /
		624	#define UID_BASE (0x1FF80050UL) /!< Unique device ID register base address for Cat.1 and Cat.2 devices /
		625	#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL)
		626	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
		627	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
		628	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
		629	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
		630	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
		631	#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
		632	#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
		633	#define DBGMCU_BASE (0xE0042000UL) /!< Debug MCU registers base address /
30	mjames	634
		635	/**
		636	* @}
		637	*/
		638
		639	/** @addtogroup Peripheral_declaration
		640	* @{
		641	*/
		642
		643	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
		644	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
		645	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
		646	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
		647	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
		648	#define RTC ((RTC_TypeDef *) RTC_BASE)
		649	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
		650	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
		651	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
		652	#define USART2 ((USART_TypeDef *) USART2_BASE)
		653	#define USART3 ((USART_TypeDef *) USART3_BASE)
		654	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
		655	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
		656	/* USB device FS */
		657	#define USB ((USB_TypeDef *) USB_BASE)
		658	/* USB device FS SRAM */
		659	#define PWR ((PWR_TypeDef *) PWR_BASE)
		660
		661	#define DAC1 ((DAC_TypeDef *) DAC_BASE)
		662	/* Legacy define */
		663	#define DAC DAC1
		664
		665	#define COMP ((COMP_TypeDef ) COMP_BASE) / COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
		666	#define COMP1 ((COMP_TypeDef ) COMP_BASE) / COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
		667	#define COMP2 ((COMP_TypeDef ) (COMP_BASE + 0x00000001U)) / COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
		668	#define COMP12_COMMON ((COMP_Common_TypeDef ) COMP_BASE) / COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
		669
		670	#define RI ((RI_TypeDef *) RI_BASE)
		671
		672	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
		673	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
		674	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
		675	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
		676	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
		677
		678	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
		679	#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
		680	/* Legacy defines */
		681	#define ADC ADC1_COMMON
		682
		683	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
		684	#define USART1 ((USART_TypeDef *) USART1_BASE)
		685	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
		686	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
		687	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
		688	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
		689	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
		690	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
		691	#define CRC ((CRC_TypeDef *) CRC_BASE)
		692	#define RCC ((RCC_TypeDef *) RCC_BASE)
		693	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
		694	#define OB ((OB_TypeDef *) OB_BASE)
		695	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
		696	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
		697	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
		698	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
		699	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
		700	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
		701	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
		702	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
		703	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
		704
		705	/**
		706	* @}
		707	*/
		708
		709	/** @addtogroup Exported_constants
		710	* @{
		711	*/
		712
61	mjames	713	/** @addtogroup Hardware_Constant_Definition
		714	* @{
		715	*/
		716	#define LSI_STARTUP_TIME 200U /!< LSI Maximum startup time in us /
		717
		718	/**
		719	* @}
		720	*/
		721
30	mjames	722	/** @addtogroup Peripheral_Registers_Bits_Definition
		723	* @{
		724	*/
		725
		726	/******************************************************************************/
		727	/* Peripheral Registers Bits Definition */
		728	/******************************************************************************/
		729	/******************************************************************************/
		730	/* */
		731	/* Analog to Digital Converter (ADC) */
		732	/* */
		733	/******************************************************************************/
50	mjames	734	#define VREFINT_CAL_ADDR_CMSIS 0x1FF80078 /!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). /
		735	#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF8007A /!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). /
		736	#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF8007E /!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). /
30	mjames	737
		738	/****************** Bit definition for ADC_SR register ******************/
		739	#define ADC_SR_AWD_Pos (0U)
50	mjames	740	#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /!< 0x00000001 /
30	mjames	741	#define ADC_SR_AWD ADC_SR_AWD_Msk /!< ADC analog watchdog 1 flag /
		742	#define ADC_SR_EOCS_Pos (1U)
50	mjames	743	#define ADC_SR_EOCS_Msk (0x1UL << ADC_SR_EOCS_Pos) /!< 0x00000002 /
30	mjames	744	#define ADC_SR_EOCS ADC_SR_EOCS_Msk /!< ADC group regular end of unitary conversion or end of sequence conversions flag /
		745	#define ADC_SR_JEOS_Pos (2U)
50	mjames	746	#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /!< 0x00000004 /
30	mjames	747	#define ADC_SR_JEOS ADC_SR_JEOS_Msk /!< ADC group injected end of sequence conversions flag /
		748	#define ADC_SR_JSTRT_Pos (3U)
50	mjames	749	#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /!< 0x00000008 /
30	mjames	750	#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /!< ADC group injected conversion start flag /
		751	#define ADC_SR_STRT_Pos (4U)
50	mjames	752	#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /!< 0x00000010 /
30	mjames	753	#define ADC_SR_STRT ADC_SR_STRT_Msk /!< ADC group regular conversion start flag /
		754	#define ADC_SR_OVR_Pos (5U)
50	mjames	755	#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /!< 0x00000020 /
30	mjames	756	#define ADC_SR_OVR ADC_SR_OVR_Msk /!< ADC group regular overrun flag /
		757	#define ADC_SR_ADONS_Pos (6U)
50	mjames	758	#define ADC_SR_ADONS_Msk (0x1UL << ADC_SR_ADONS_Pos) /!< 0x00000040 /
30	mjames	759	#define ADC_SR_ADONS ADC_SR_ADONS_Msk /!< ADC ready flag /
		760	#define ADC_SR_RCNR_Pos (8U)
50	mjames	761	#define ADC_SR_RCNR_Msk (0x1UL << ADC_SR_RCNR_Pos) /!< 0x00000100 /
30	mjames	762	#define ADC_SR_RCNR ADC_SR_RCNR_Msk /!< ADC group regular not ready flag /
		763	#define ADC_SR_JCNR_Pos (9U)
50	mjames	764	#define ADC_SR_JCNR_Msk (0x1UL << ADC_SR_JCNR_Pos) /!< 0x00000200 /
30	mjames	765	#define ADC_SR_JCNR ADC_SR_JCNR_Msk /!< ADC group injected not ready flag /
		766
		767	/* Legacy defines */
		768	#define ADC_SR_EOC (ADC_SR_EOCS)
		769	#define ADC_SR_JEOC (ADC_SR_JEOS)
		770
		771	/***************** Bit definition for ADC_CR1 register ******************/
		772	#define ADC_CR1_AWDCH_Pos (0U)
50	mjames	773	#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /!< 0x0000001F /
30	mjames	774	#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /!< ADC analog watchdog 1 monitored channel selection /
50	mjames	775	#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /!< 0x00000001 /
		776	#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /!< 0x00000002 /
		777	#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /!< 0x00000004 /
		778	#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /!< 0x00000008 /
		779	#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /!< 0x00000010 /
30	mjames	780
		781	#define ADC_CR1_EOCSIE_Pos (5U)
50	mjames	782	#define ADC_CR1_EOCSIE_Msk (0x1UL << ADC_CR1_EOCSIE_Pos) /!< 0x00000020 /
30	mjames	783	#define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /!< ADC group regular end of unitary conversion or end of sequence conversions interrupt /
		784	#define ADC_CR1_AWDIE_Pos (6U)
50	mjames	785	#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /!< 0x00000040 /
30	mjames	786	#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /!< ADC analog watchdog 1 interrupt /
		787	#define ADC_CR1_JEOSIE_Pos (7U)
50	mjames	788	#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /!< 0x00000080 /
30	mjames	789	#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /!< ADC group injected end of sequence conversions interrupt /
		790	#define ADC_CR1_SCAN_Pos (8U)
50	mjames	791	#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /!< 0x00000100 /
30	mjames	792	#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /!< ADC scan mode /
		793	#define ADC_CR1_AWDSGL_Pos (9U)
50	mjames	794	#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /!< 0x00000200 /
30	mjames	795	#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /!< ADC analog watchdog 1 monitoring a single channel or all channels /
		796	#define ADC_CR1_JAUTO_Pos (10U)
50	mjames	797	#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /!< 0x00000400 /
30	mjames	798	#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /!< ADC group injected automatic trigger mode /
		799	#define ADC_CR1_DISCEN_Pos (11U)
50	mjames	800	#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /!< 0x00000800 /
30	mjames	801	#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /
		802	#define ADC_CR1_JDISCEN_Pos (12U)
50	mjames	803	#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /!< 0x00001000 /
30	mjames	804	#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /!< ADC group injected sequencer discontinuous mode /
		805
		806	#define ADC_CR1_DISCNUM_Pos (13U)
50	mjames	807	#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /!< 0x0000E000 /
30	mjames	808	#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /!< ADC group regular sequencer discontinuous number of ranks /
50	mjames	809	#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /!< 0x00002000 /
		810	#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /!< 0x00004000 /
		811	#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /!< 0x00008000 /
30	mjames	812
		813	#define ADC_CR1_PDD_Pos (16U)
50	mjames	814	#define ADC_CR1_PDD_Msk (0x1UL << ADC_CR1_PDD_Pos) /!< 0x00010000 /
30	mjames	815	#define ADC_CR1_PDD ADC_CR1_PDD_Msk /!< ADC power down during auto delay phase /
		816	#define ADC_CR1_PDI_Pos (17U)
50	mjames	817	#define ADC_CR1_PDI_Msk (0x1UL << ADC_CR1_PDI_Pos) /!< 0x00020000 /
30	mjames	818	#define ADC_CR1_PDI ADC_CR1_PDI_Msk /!< ADC power down during idle phase /
		819
		820	#define ADC_CR1_JAWDEN_Pos (22U)
50	mjames	821	#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /!< 0x00400000 /
30	mjames	822	#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group injected /
		823	#define ADC_CR1_AWDEN_Pos (23U)
50	mjames	824	#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /!< 0x00800000 /
30	mjames	825	#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group regular /
		826
		827	#define ADC_CR1_RES_Pos (24U)
50	mjames	828	#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /!< 0x03000000 /
30	mjames	829	#define ADC_CR1_RES ADC_CR1_RES_Msk /!< ADC resolution /
50	mjames	830	#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /!< 0x01000000 /
		831	#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /!< 0x02000000 /
30	mjames	832
		833	#define ADC_CR1_OVRIE_Pos (26U)
50	mjames	834	#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /!< 0x04000000 /
30	mjames	835	#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /!< ADC group regular overrun interrupt /
		836
		837	/* Legacy defines */
		838	#define ADC_CR1_EOCIE (ADC_CR1_EOCSIE)
		839	#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
		840
		841	/***************** Bit definition for ADC_CR2 register ******************/
		842	#define ADC_CR2_ADON_Pos (0U)
50	mjames	843	#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /!< 0x00000001 /
30	mjames	844	#define ADC_CR2_ADON ADC_CR2_ADON_Msk /!< ADC enable /
		845	#define ADC_CR2_CONT_Pos (1U)
50	mjames	846	#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /!< 0x00000002 /
30	mjames	847	#define ADC_CR2_CONT ADC_CR2_CONT_Msk /!< ADC group regular continuous conversion mode /
		848
		849	#define ADC_CR2_DELS_Pos (4U)
50	mjames	850	#define ADC_CR2_DELS_Msk (0x7UL << ADC_CR2_DELS_Pos) /!< 0x00000070 /
30	mjames	851	#define ADC_CR2_DELS ADC_CR2_DELS_Msk /!< ADC auto delay selection /
50	mjames	852	#define ADC_CR2_DELS_0 (0x1UL << ADC_CR2_DELS_Pos) /!< 0x00000010 /
		853	#define ADC_CR2_DELS_1 (0x2UL << ADC_CR2_DELS_Pos) /!< 0x00000020 /
		854	#define ADC_CR2_DELS_2 (0x4UL << ADC_CR2_DELS_Pos) /!< 0x00000040 /
30	mjames	855
		856	#define ADC_CR2_DMA_Pos (8U)
50	mjames	857	#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /!< 0x00000100 /
30	mjames	858	#define ADC_CR2_DMA ADC_CR2_DMA_Msk /!< ADC DMA transfer enable /
		859	#define ADC_CR2_DDS_Pos (9U)
50	mjames	860	#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /!< 0x00000200 /
30	mjames	861	#define ADC_CR2_DDS ADC_CR2_DDS_Msk /!< ADC DMA transfer configuration /
		862	#define ADC_CR2_EOCS_Pos (10U)
50	mjames	863	#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /!< 0x00000400 /
30	mjames	864	#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /!< ADC end of unitary or end of sequence conversions selection /
		865	#define ADC_CR2_ALIGN_Pos (11U)
50	mjames	866	#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /!< 0x00000800 /
30	mjames	867	#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /!< ADC data alignement /
		868
		869	#define ADC_CR2_JEXTSEL_Pos (16U)
50	mjames	870	#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /!< 0x000F0000 /
30	mjames	871	#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /!< ADC group injected external trigger source /
50	mjames	872	#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00010000 /
		873	#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00020000 /
		874	#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00040000 /
		875	#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /!< 0x00080000 /
30	mjames	876
		877	#define ADC_CR2_JEXTEN_Pos (20U)
50	mjames	878	#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /!< 0x00300000 /
30	mjames	879	#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /!< ADC group injected external trigger polarity /
50	mjames	880	#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /!< 0x00100000 /
		881	#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /!< 0x00200000 /
30	mjames	882
		883	#define ADC_CR2_JSWSTART_Pos (22U)
50	mjames	884	#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /!< 0x00400000 /
30	mjames	885	#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /!< ADC group injected conversion start /
		886
		887	#define ADC_CR2_EXTSEL_Pos (24U)
50	mjames	888	#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /!< 0x0F000000 /
30	mjames	889	#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /!< ADC group regular external trigger source /
50	mjames	890	#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /!< 0x01000000 /
		891	#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /!< 0x02000000 /
		892	#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /!< 0x04000000 /
		893	#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /!< 0x08000000 /
30	mjames	894
		895	#define ADC_CR2_EXTEN_Pos (28U)
50	mjames	896	#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /!< 0x30000000 /
30	mjames	897	#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /!< ADC group regular external trigger polarity /
50	mjames	898	#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /!< 0x10000000 /
		899	#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /!< 0x20000000 /
30	mjames	900
		901	#define ADC_CR2_SWSTART_Pos (30U)
50	mjames	902	#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /!< 0x40000000 /
30	mjames	903	#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /!< ADC group regular conversion start /
		904
		905	/**************** Bit definition for ADC_SMPR1 register *****************/
		906	#define ADC_SMPR1_SMP20_Pos (0U)
50	mjames	907	#define ADC_SMPR1_SMP20_Msk (0x7UL << ADC_SMPR1_SMP20_Pos) /!< 0x00000007 /
30	mjames	908	#define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /!< ADC channel 20 sampling time selection /
50	mjames	909	#define ADC_SMPR1_SMP20_0 (0x1UL << ADC_SMPR1_SMP20_Pos) /!< 0x00000001 /
		910	#define ADC_SMPR1_SMP20_1 (0x2UL << ADC_SMPR1_SMP20_Pos) /!< 0x00000002 /
		911	#define ADC_SMPR1_SMP20_2 (0x4UL << ADC_SMPR1_SMP20_Pos) /!< 0x00000004 /
30	mjames	912
		913	#define ADC_SMPR1_SMP21_Pos (3U)
50	mjames	914	#define ADC_SMPR1_SMP21_Msk (0x7UL << ADC_SMPR1_SMP21_Pos) /!< 0x00000038 /
30	mjames	915	#define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /!< ADC channel 21 sampling time selection /
50	mjames	916	#define ADC_SMPR1_SMP21_0 (0x1UL << ADC_SMPR1_SMP21_Pos) /!< 0x00000008 /
		917	#define ADC_SMPR1_SMP21_1 (0x2UL << ADC_SMPR1_SMP21_Pos) /!< 0x00000010 /
		918	#define ADC_SMPR1_SMP21_2 (0x4UL << ADC_SMPR1_SMP21_Pos) /!< 0x00000020 /
30	mjames	919
		920	#define ADC_SMPR1_SMP22_Pos (6U)
50	mjames	921	#define ADC_SMPR1_SMP22_Msk (0x7UL << ADC_SMPR1_SMP22_Pos) /!< 0x000001C0 /
30	mjames	922	#define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /!< ADC channel 22 sampling time selection /
50	mjames	923	#define ADC_SMPR1_SMP22_0 (0x1UL << ADC_SMPR1_SMP22_Pos) /!< 0x00000040 /
		924	#define ADC_SMPR1_SMP22_1 (0x2UL << ADC_SMPR1_SMP22_Pos) /!< 0x00000080 /
		925	#define ADC_SMPR1_SMP22_2 (0x4UL << ADC_SMPR1_SMP22_Pos) /!< 0x00000100 /
30	mjames	926
		927	#define ADC_SMPR1_SMP23_Pos (9U)
50	mjames	928	#define ADC_SMPR1_SMP23_Msk (0x7UL << ADC_SMPR1_SMP23_Pos) /!< 0x00000E00 /
30	mjames	929	#define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /!< ADC channel 23 sampling time selection /
50	mjames	930	#define ADC_SMPR1_SMP23_0 (0x1UL << ADC_SMPR1_SMP23_Pos) /!< 0x00000200 /
		931	#define ADC_SMPR1_SMP23_1 (0x2UL << ADC_SMPR1_SMP23_Pos) /!< 0x00000400 /
		932	#define ADC_SMPR1_SMP23_2 (0x4UL << ADC_SMPR1_SMP23_Pos) /!< 0x00000800 /
30	mjames	933
		934	#define ADC_SMPR1_SMP24_Pos (12U)
50	mjames	935	#define ADC_SMPR1_SMP24_Msk (0x7UL << ADC_SMPR1_SMP24_Pos) /!< 0x00007000 /
30	mjames	936	#define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /!< ADC channel 24 sampling time selection /
50	mjames	937	#define ADC_SMPR1_SMP24_0 (0x1UL << ADC_SMPR1_SMP24_Pos) /!< 0x00001000 /
		938	#define ADC_SMPR1_SMP24_1 (0x2UL << ADC_SMPR1_SMP24_Pos) /!< 0x00002000 /
		939	#define ADC_SMPR1_SMP24_2 (0x4UL << ADC_SMPR1_SMP24_Pos) /!< 0x00004000 /
30	mjames	940
		941	#define ADC_SMPR1_SMP25_Pos (15U)
50	mjames	942	#define ADC_SMPR1_SMP25_Msk (0x7UL << ADC_SMPR1_SMP25_Pos) /!< 0x00038000 /
30	mjames	943	#define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /!< ADC channel 25 sampling time selection /
50	mjames	944	#define ADC_SMPR1_SMP25_0 (0x1UL << ADC_SMPR1_SMP25_Pos) /!< 0x00008000 /
		945	#define ADC_SMPR1_SMP25_1 (0x2UL << ADC_SMPR1_SMP25_Pos) /!< 0x00010000 /
		946	#define ADC_SMPR1_SMP25_2 (0x4UL << ADC_SMPR1_SMP25_Pos) /!< 0x00020000 /
30	mjames	947
		948	#define ADC_SMPR1_SMP26_Pos (18U)
50	mjames	949	#define ADC_SMPR1_SMP26_Msk (0x7UL << ADC_SMPR1_SMP26_Pos) /!< 0x001C0000 /
30	mjames	950	#define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /!< ADC channel 26 sampling time selection /
50	mjames	951	#define ADC_SMPR1_SMP26_0 (0x1UL << ADC_SMPR1_SMP26_Pos) /!< 0x00040000 /
		952	#define ADC_SMPR1_SMP26_1 (0x2UL << ADC_SMPR1_SMP26_Pos) /!< 0x00080000 /
		953	#define ADC_SMPR1_SMP26_2 (0x4UL << ADC_SMPR1_SMP26_Pos) /!< 0x00100000 /
30	mjames	954
		955	/**************** Bit definition for ADC_SMPR2 register *****************/
		956	#define ADC_SMPR2_SMP10_Pos (0U)
50	mjames	957	#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /!< 0x00000007 /
30	mjames	958	#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /!< ADC channel 10 sampling time selection /
50	mjames	959	#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /!< 0x00000001 /
		960	#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /!< 0x00000002 /
		961	#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /!< 0x00000004 /
30	mjames	962
		963	#define ADC_SMPR2_SMP11_Pos (3U)
50	mjames	964	#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /!< 0x00000038 /
30	mjames	965	#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /!< ADC channel 11 sampling time selection /
50	mjames	966	#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /!< 0x00000008 /
		967	#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /!< 0x00000010 /
		968	#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /!< 0x00000020 /
30	mjames	969
		970	#define ADC_SMPR2_SMP12_Pos (6U)
50	mjames	971	#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /!< 0x000001C0 /
30	mjames	972	#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /!< ADC channel 12 sampling time selection /
50	mjames	973	#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /!< 0x00000040 /
		974	#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /!< 0x00000080 /
		975	#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /!< 0x00000100 /
30	mjames	976
		977	#define ADC_SMPR2_SMP13_Pos (9U)
50	mjames	978	#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /!< 0x00000E00 /
30	mjames	979	#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /!< ADC channel 13 sampling time selection /
50	mjames	980	#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /!< 0x00000200 /
		981	#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /!< 0x00000400 /
		982	#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /!< 0x00000800 /
30	mjames	983
		984	#define ADC_SMPR2_SMP14_Pos (12U)
50	mjames	985	#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /!< 0x00007000 /
30	mjames	986	#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /!< ADC channel 14 sampling time selection /
50	mjames	987	#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /!< 0x00001000 /
		988	#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /!< 0x00002000 /
		989	#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /!< 0x00004000 /
30	mjames	990
		991	#define ADC_SMPR2_SMP15_Pos (15U)
50	mjames	992	#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /!< 0x00038000 /
30	mjames	993	#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /!< ADC channel 5 sampling time selection /
50	mjames	994	#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /!< 0x00008000 /
		995	#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /!< 0x00010000 /
		996	#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /!< 0x00020000 /
30	mjames	997
		998	#define ADC_SMPR2_SMP16_Pos (18U)
50	mjames	999	#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /!< 0x001C0000 /
30	mjames	1000	#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /!< ADC channel 16 sampling time selection /
50	mjames	1001	#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /!< 0x00040000 /
		1002	#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /!< 0x00080000 /
		1003	#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /!< 0x00100000 /
30	mjames	1004
		1005	#define ADC_SMPR2_SMP17_Pos (21U)
50	mjames	1006	#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /!< 0x00E00000 /
30	mjames	1007	#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /!< ADC channel 17 sampling time selection /
50	mjames	1008	#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /!< 0x00200000 /
		1009	#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /!< 0x00400000 /
		1010	#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /!< 0x00800000 /
30	mjames	1011
		1012	#define ADC_SMPR2_SMP18_Pos (24U)
50	mjames	1013	#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /!< 0x07000000 /
30	mjames	1014	#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /!< ADC channel 18 sampling time selection /
50	mjames	1015	#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /!< 0x01000000 /
		1016	#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /!< 0x02000000 /
		1017	#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /!< 0x04000000 /
30	mjames	1018
		1019	#define ADC_SMPR2_SMP19_Pos (27U)
50	mjames	1020	#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /!< 0x38000000 /
30	mjames	1021	#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /!< ADC channel 19 sampling time selection /
50	mjames	1022	#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /!< 0x08000000 /
		1023	#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /!< 0x10000000 /
		1024	#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /!< 0x20000000 /
30	mjames	1025
		1026	/**************** Bit definition for ADC_SMPR3 register *****************/
		1027	#define ADC_SMPR3_SMP0_Pos (0U)
50	mjames	1028	#define ADC_SMPR3_SMP0_Msk (0x7UL << ADC_SMPR3_SMP0_Pos) /!< 0x00000007 /
30	mjames	1029	#define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /!< ADC channel 0 sampling time selection /
50	mjames	1030	#define ADC_SMPR3_SMP0_0 (0x1UL << ADC_SMPR3_SMP0_Pos) /!< 0x00000001 /
		1031	#define ADC_SMPR3_SMP0_1 (0x2UL << ADC_SMPR3_SMP0_Pos) /!< 0x00000002 /
		1032	#define ADC_SMPR3_SMP0_2 (0x4UL << ADC_SMPR3_SMP0_Pos) /!< 0x00000004 /
30	mjames	1033
		1034	#define ADC_SMPR3_SMP1_Pos (3U)
50	mjames	1035	#define ADC_SMPR3_SMP1_Msk (0x7UL << ADC_SMPR3_SMP1_Pos) /!< 0x00000038 /
30	mjames	1036	#define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /!< ADC channel 1 sampling time selection /
50	mjames	1037	#define ADC_SMPR3_SMP1_0 (0x1UL << ADC_SMPR3_SMP1_Pos) /!< 0x00000008 /
		1038	#define ADC_SMPR3_SMP1_1 (0x2UL << ADC_SMPR3_SMP1_Pos) /!< 0x00000010 /
		1039	#define ADC_SMPR3_SMP1_2 (0x4UL << ADC_SMPR3_SMP1_Pos) /!< 0x00000020 /
30	mjames	1040
		1041	#define ADC_SMPR3_SMP2_Pos (6U)
50	mjames	1042	#define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /!< 0x000001C0 /
30	mjames	1043	#define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /!< ADC channel 2 sampling time selection /
50	mjames	1044	#define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /!< 0x00000040 /
		1045	#define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /!< 0x00000080 /
		1046	#define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /!< 0x00000100 /
30	mjames	1047
		1048	#define ADC_SMPR3_SMP3_Pos (9U)
50	mjames	1049	#define ADC_SMPR3_SMP3_Msk (0x7UL << ADC_SMPR3_SMP3_Pos) /!< 0x00000E00 /
30	mjames	1050	#define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /!< ADC channel 3 sampling time selection /
50	mjames	1051	#define ADC_SMPR3_SMP3_0 (0x1UL << ADC_SMPR3_SMP3_Pos) /!< 0x00000200 /
		1052	#define ADC_SMPR3_SMP3_1 (0x2UL << ADC_SMPR3_SMP3_Pos) /!< 0x00000400 /
		1053	#define ADC_SMPR3_SMP3_2 (0x4UL << ADC_SMPR3_SMP3_Pos) /!< 0x00000800 /
30	mjames	1054
		1055	#define ADC_SMPR3_SMP4_Pos (12U)
50	mjames	1056	#define ADC_SMPR3_SMP4_Msk (0x7UL << ADC_SMPR3_SMP4_Pos) /!< 0x00007000 /
30	mjames	1057	#define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /!< ADC channel 4 sampling time selection /
50	mjames	1058	#define ADC_SMPR3_SMP4_0 (0x1UL << ADC_SMPR3_SMP4_Pos) /!< 0x00001000 /
		1059	#define ADC_SMPR3_SMP4_1 (0x2UL << ADC_SMPR3_SMP4_Pos) /!< 0x00002000 /
		1060	#define ADC_SMPR3_SMP4_2 (0x4UL << ADC_SMPR3_SMP4_Pos) /!< 0x00004000 /
30	mjames	1061
		1062	#define ADC_SMPR3_SMP5_Pos (15U)
50	mjames	1063	#define ADC_SMPR3_SMP5_Msk (0x7UL << ADC_SMPR3_SMP5_Pos) /!< 0x00038000 /
30	mjames	1064	#define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /!< ADC channel 5 sampling time selection /
50	mjames	1065	#define ADC_SMPR3_SMP5_0 (0x1UL << ADC_SMPR3_SMP5_Pos) /!< 0x00008000 /
		1066	#define ADC_SMPR3_SMP5_1 (0x2UL << ADC_SMPR3_SMP5_Pos) /!< 0x00010000 /
		1067	#define ADC_SMPR3_SMP5_2 (0x4UL << ADC_SMPR3_SMP5_Pos) /!< 0x00020000 /
30	mjames	1068
		1069	#define ADC_SMPR3_SMP6_Pos (18U)
50	mjames	1070	#define ADC_SMPR3_SMP6_Msk (0x7UL << ADC_SMPR3_SMP6_Pos) /!< 0x001C0000 /
30	mjames	1071	#define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /!< ADC channel 6 sampling time selection /
50	mjames	1072	#define ADC_SMPR3_SMP6_0 (0x1UL << ADC_SMPR3_SMP6_Pos) /!< 0x00040000 /
		1073	#define ADC_SMPR3_SMP6_1 (0x2UL << ADC_SMPR3_SMP6_Pos) /!< 0x00080000 /
		1074	#define ADC_SMPR3_SMP6_2 (0x4UL << ADC_SMPR3_SMP6_Pos) /!< 0x00100000 /
30	mjames	1075
		1076	#define ADC_SMPR3_SMP7_Pos (21U)
50	mjames	1077	#define ADC_SMPR3_SMP7_Msk (0x7UL << ADC_SMPR3_SMP7_Pos) /!< 0x00E00000 /
30	mjames	1078	#define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /!< ADC channel 7 sampling time selection /
50	mjames	1079	#define ADC_SMPR3_SMP7_0 (0x1UL << ADC_SMPR3_SMP7_Pos) /!< 0x00200000 /
		1080	#define ADC_SMPR3_SMP7_1 (0x2UL << ADC_SMPR3_SMP7_Pos) /!< 0x00400000 /
		1081	#define ADC_SMPR3_SMP7_2 (0x4UL << ADC_SMPR3_SMP7_Pos) /!< 0x00800000 /
30	mjames	1082
		1083	#define ADC_SMPR3_SMP8_Pos (24U)
50	mjames	1084	#define ADC_SMPR3_SMP8_Msk (0x7UL << ADC_SMPR3_SMP8_Pos) /!< 0x07000000 /
30	mjames	1085	#define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /!< ADC channel 8 sampling time selection /
50	mjames	1086	#define ADC_SMPR3_SMP8_0 (0x1UL << ADC_SMPR3_SMP8_Pos) /!< 0x01000000 /
		1087	#define ADC_SMPR3_SMP8_1 (0x2UL << ADC_SMPR3_SMP8_Pos) /!< 0x02000000 /
		1088	#define ADC_SMPR3_SMP8_2 (0x4UL << ADC_SMPR3_SMP8_Pos) /!< 0x04000000 /
30	mjames	1089
		1090	#define ADC_SMPR3_SMP9_Pos (27U)
50	mjames	1091	#define ADC_SMPR3_SMP9_Msk (0x7UL << ADC_SMPR3_SMP9_Pos) /!< 0x38000000 /
30	mjames	1092	#define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /!< ADC channel 9 sampling time selection /
50	mjames	1093	#define ADC_SMPR3_SMP9_0 (0x1UL << ADC_SMPR3_SMP9_Pos) /!< 0x08000000 /
		1094	#define ADC_SMPR3_SMP9_1 (0x2UL << ADC_SMPR3_SMP9_Pos) /!< 0x10000000 /
		1095	#define ADC_SMPR3_SMP9_2 (0x4UL << ADC_SMPR3_SMP9_Pos) /!< 0x20000000 /
30	mjames	1096
		1097	/**************** Bit definition for ADC_JOFR1 register *****************/
		1098	#define ADC_JOFR1_JOFFSET1_Pos (0U)
50	mjames	1099	#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /!< 0x00000FFF /
30	mjames	1100	#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /!< ADC group injected sequencer rank 1 offset value /
		1101
		1102	/**************** Bit definition for ADC_JOFR2 register *****************/
		1103	#define ADC_JOFR2_JOFFSET2_Pos (0U)
50	mjames	1104	#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /!< 0x00000FFF /
30	mjames	1105	#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /!< ADC group injected sequencer rank 2 offset value /
		1106
		1107	/**************** Bit definition for ADC_JOFR3 register *****************/
		1108	#define ADC_JOFR3_JOFFSET3_Pos (0U)
50	mjames	1109	#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /!< 0x00000FFF /
30	mjames	1110	#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /!< ADC group injected sequencer rank 3 offset value /
		1111
		1112	/**************** Bit definition for ADC_JOFR4 register *****************/
		1113	#define ADC_JOFR4_JOFFSET4_Pos (0U)
50	mjames	1114	#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /!< 0x00000FFF /
30	mjames	1115	#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /!< ADC group injected sequencer rank 4 offset value /
		1116
		1117	/***************** Bit definition for ADC_HTR register ******************/
		1118	#define ADC_HTR_HT_Pos (0U)
50	mjames	1119	#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /!< 0x00000FFF /
30	mjames	1120	#define ADC_HTR_HT ADC_HTR_HT_Msk /!< ADC analog watchdog 1 threshold high /
		1121
		1122	/***************** Bit definition for ADC_LTR register ******************/
		1123	#define ADC_LTR_LT_Pos (0U)
50	mjames	1124	#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /!< 0x00000FFF /
30	mjames	1125	#define ADC_LTR_LT ADC_LTR_LT_Msk /!< ADC analog watchdog 1 threshold low /
		1126
		1127	/***************** Bit definition for ADC_SQR1 register *****************/
		1128	#define ADC_SQR1_L_Pos (20U)
50	mjames	1129	#define ADC_SQR1_L_Msk (0x1FUL << ADC_SQR1_L_Pos) /!< 0x01F00000 /
30	mjames	1130	#define ADC_SQR1_L ADC_SQR1_L_Msk /!< ADC group regular sequencer scan length /
50	mjames	1131	#define ADC_SQR1_L_0 (0x01UL << ADC_SQR1_L_Pos) /!< 0x00100000 /
		1132	#define ADC_SQR1_L_1 (0x02UL << ADC_SQR1_L_Pos) /!< 0x00200000 /
		1133	#define ADC_SQR1_L_2 (0x04UL << ADC_SQR1_L_Pos) /!< 0x00400000 /
		1134	#define ADC_SQR1_L_3 (0x08UL << ADC_SQR1_L_Pos) /!< 0x00800000 /
		1135	#define ADC_SQR1_L_4 (0x10UL << ADC_SQR1_L_Pos) /!< 0x01000000 /
30	mjames	1136
		1137	#define ADC_SQR1_SQ27_Pos (10U)
50	mjames	1138	#define ADC_SQR1_SQ27_Msk (0x1FUL << ADC_SQR1_SQ27_Pos) /!< 0x00007C00 /
30	mjames	1139	#define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /!< ADC group regular sequencer rank 27 /
50	mjames	1140	#define ADC_SQR1_SQ27_0 (0x01UL << ADC_SQR1_SQ27_Pos) /!< 0x00000400 /
		1141	#define ADC_SQR1_SQ27_1 (0x02UL << ADC_SQR1_SQ27_Pos) /!< 0x00000800 /
		1142	#define ADC_SQR1_SQ27_2 (0x04UL << ADC_SQR1_SQ27_Pos) /!< 0x00001000 /
		1143	#define ADC_SQR1_SQ27_3 (0x08UL << ADC_SQR1_SQ27_Pos) /!< 0x00002000 /
		1144	#define ADC_SQR1_SQ27_4 (0x10UL << ADC_SQR1_SQ27_Pos) /!< 0x00004000 /
30	mjames	1145
		1146	#define ADC_SQR1_SQ26_Pos (5U)
50	mjames	1147	#define ADC_SQR1_SQ26_Msk (0x1FUL << ADC_SQR1_SQ26_Pos) /!< 0x000003E0 /
30	mjames	1148	#define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /!< ADC group regular sequencer rank 26 /
50	mjames	1149	#define ADC_SQR1_SQ26_0 (0x01UL << ADC_SQR1_SQ26_Pos) /!< 0x00000020 /
		1150	#define ADC_SQR1_SQ26_1 (0x02UL << ADC_SQR1_SQ26_Pos) /!< 0x00000040 /
		1151	#define ADC_SQR1_SQ26_2 (0x04UL << ADC_SQR1_SQ26_Pos) /!< 0x00000080 /
		1152	#define ADC_SQR1_SQ26_3 (0x08UL << ADC_SQR1_SQ26_Pos) /!< 0x00000100 /
		1153	#define ADC_SQR1_SQ26_4 (0x10UL << ADC_SQR1_SQ26_Pos) /!< 0x00000200 /
30	mjames	1154
		1155	#define ADC_SQR1_SQ25_Pos (0U)
50	mjames	1156	#define ADC_SQR1_SQ25_Msk (0x1FUL << ADC_SQR1_SQ25_Pos) /!< 0x0000001F /
30	mjames	1157	#define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /!< ADC group regular sequencer rank 25 /
50	mjames	1158	#define ADC_SQR1_SQ25_0 (0x01UL << ADC_SQR1_SQ25_Pos) /!< 0x00000001 /
		1159	#define ADC_SQR1_SQ25_1 (0x02UL << ADC_SQR1_SQ25_Pos) /!< 0x00000002 /
		1160	#define ADC_SQR1_SQ25_2 (0x04UL << ADC_SQR1_SQ25_Pos) /!< 0x00000004 /
		1161	#define ADC_SQR1_SQ25_3 (0x08UL << ADC_SQR1_SQ25_Pos) /!< 0x00000008 /
		1162	#define ADC_SQR1_SQ25_4 (0x10UL << ADC_SQR1_SQ25_Pos) /!< 0x00000010 /
30	mjames	1163
		1164	/***************** Bit definition for ADC_SQR2 register *****************/
		1165	#define ADC_SQR2_SQ19_Pos (0U)
50	mjames	1166	#define ADC_SQR2_SQ19_Msk (0x1FUL << ADC_SQR2_SQ19_Pos) /!< 0x0000001F /
30	mjames	1167	#define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /!< ADC group regular sequencer rank 19 /
50	mjames	1168	#define ADC_SQR2_SQ19_0 (0x01UL << ADC_SQR2_SQ19_Pos) /!< 0x00000001 /
		1169	#define ADC_SQR2_SQ19_1 (0x02UL << ADC_SQR2_SQ19_Pos) /!< 0x00000002 /
		1170	#define ADC_SQR2_SQ19_2 (0x04UL << ADC_SQR2_SQ19_Pos) /!< 0x00000004 /
		1171	#define ADC_SQR2_SQ19_3 (0x08UL << ADC_SQR2_SQ19_Pos) /!< 0x00000008 /
		1172	#define ADC_SQR2_SQ19_4 (0x10UL << ADC_SQR2_SQ19_Pos) /!< 0x00000010 /
30	mjames	1173
		1174	#define ADC_SQR2_SQ20_Pos (5U)
50	mjames	1175	#define ADC_SQR2_SQ20_Msk (0x1FUL << ADC_SQR2_SQ20_Pos) /!< 0x000003E0 /
30	mjames	1176	#define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /!< ADC group regular sequencer rank 20 /
50	mjames	1177	#define ADC_SQR2_SQ20_0 (0x01UL << ADC_SQR2_SQ20_Pos) /!< 0x00000020 /
		1178	#define ADC_SQR2_SQ20_1 (0x02UL << ADC_SQR2_SQ20_Pos) /!< 0x00000040 /
		1179	#define ADC_SQR2_SQ20_2 (0x04UL << ADC_SQR2_SQ20_Pos) /!< 0x00000080 /
		1180	#define ADC_SQR2_SQ20_3 (0x08UL << ADC_SQR2_SQ20_Pos) /!< 0x00000100 /
		1181	#define ADC_SQR2_SQ20_4 (0x10UL << ADC_SQR2_SQ20_Pos) /!< 0x00000200 /
30	mjames	1182
		1183	#define ADC_SQR2_SQ21_Pos (10U)
50	mjames	1184	#define ADC_SQR2_SQ21_Msk (0x1FUL << ADC_SQR2_SQ21_Pos) /!< 0x00007C00 /
30	mjames	1185	#define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /!< ADC group regular sequencer rank 21 /
50	mjames	1186	#define ADC_SQR2_SQ21_0 (0x01UL << ADC_SQR2_SQ21_Pos) /!< 0x00000400 /
		1187	#define ADC_SQR2_SQ21_1 (0x02UL << ADC_SQR2_SQ21_Pos) /!< 0x00000800 /
		1188	#define ADC_SQR2_SQ21_2 (0x04UL << ADC_SQR2_SQ21_Pos) /!< 0x00001000 /
		1189	#define ADC_SQR2_SQ21_3 (0x08UL << ADC_SQR2_SQ21_Pos) /!< 0x00002000 /
		1190	#define ADC_SQR2_SQ21_4 (0x10UL << ADC_SQR2_SQ21_Pos) /!< 0x00004000 /
30	mjames	1191
		1192	#define ADC_SQR2_SQ22_Pos (15U)
50	mjames	1193	#define ADC_SQR2_SQ22_Msk (0x1FUL << ADC_SQR2_SQ22_Pos) /!< 0x000F8000 /
30	mjames	1194	#define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /!< ADC group regular sequencer rank 22 /
50	mjames	1195	#define ADC_SQR2_SQ22_0 (0x01UL << ADC_SQR2_SQ22_Pos) /!< 0x00008000 /
		1196	#define ADC_SQR2_SQ22_1 (0x02UL << ADC_SQR2_SQ22_Pos) /!< 0x00010000 /
		1197	#define ADC_SQR2_SQ22_2 (0x04UL << ADC_SQR2_SQ22_Pos) /!< 0x00020000 /
		1198	#define ADC_SQR2_SQ22_3 (0x08UL << ADC_SQR2_SQ22_Pos) /!< 0x00040000 /
		1199	#define ADC_SQR2_SQ22_4 (0x10UL << ADC_SQR2_SQ22_Pos) /!< 0x00080000 /
30	mjames	1200
		1201	#define ADC_SQR2_SQ23_Pos (20U)
50	mjames	1202	#define ADC_SQR2_SQ23_Msk (0x1FUL << ADC_SQR2_SQ23_Pos) /!< 0x01F00000 /
30	mjames	1203	#define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /!< ADC group regular sequencer rank 23 /
50	mjames	1204	#define ADC_SQR2_SQ23_0 (0x01UL << ADC_SQR2_SQ23_Pos) /!< 0x00100000 /
		1205	#define ADC_SQR2_SQ23_1 (0x02UL << ADC_SQR2_SQ23_Pos) /!< 0x00200000 /
		1206	#define ADC_SQR2_SQ23_2 (0x04UL << ADC_SQR2_SQ23_Pos) /!< 0x00400000 /
		1207	#define ADC_SQR2_SQ23_3 (0x08UL << ADC_SQR2_SQ23_Pos) /!< 0x00800000 /
		1208	#define ADC_SQR2_SQ23_4 (0x10UL << ADC_SQR2_SQ23_Pos) /!< 0x01000000 /
30	mjames	1209
		1210	#define ADC_SQR2_SQ24_Pos (25U)
50	mjames	1211	#define ADC_SQR2_SQ24_Msk (0x1FUL << ADC_SQR2_SQ24_Pos) /!< 0x3E000000 /
30	mjames	1212	#define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /!< ADC group regular sequencer rank 24 /
50	mjames	1213	#define ADC_SQR2_SQ24_0 (0x01UL << ADC_SQR2_SQ24_Pos) /!< 0x02000000 /
		1214	#define ADC_SQR2_SQ24_1 (0x02UL << ADC_SQR2_SQ24_Pos) /!< 0x04000000 /
		1215	#define ADC_SQR2_SQ24_2 (0x04UL << ADC_SQR2_SQ24_Pos) /!< 0x08000000 /
		1216	#define ADC_SQR2_SQ24_3 (0x08UL << ADC_SQR2_SQ24_Pos) /!< 0x10000000 /
		1217	#define ADC_SQR2_SQ24_4 (0x10UL << ADC_SQR2_SQ24_Pos) /!< 0x20000000 /
30	mjames	1218
		1219	/***************** Bit definition for ADC_SQR3 register *****************/
		1220	#define ADC_SQR3_SQ13_Pos (0U)
50	mjames	1221	#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /!< 0x0000001F /
30	mjames	1222	#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /!< ADC group regular sequencer rank 13 /
50	mjames	1223	#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /!< 0x00000001 /
		1224	#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /!< 0x00000002 /
		1225	#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /!< 0x00000004 /
		1226	#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /!< 0x00000008 /
		1227	#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /!< 0x00000010 /
30	mjames	1228
		1229	#define ADC_SQR3_SQ14_Pos (5U)
50	mjames	1230	#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /!< 0x000003E0 /
30	mjames	1231	#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /!< ADC group regular sequencer rank 14 /
50	mjames	1232	#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /!< 0x00000020 /
		1233	#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /!< 0x00000040 /
		1234	#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /!< 0x00000080 /
		1235	#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /!< 0x00000100 /
		1236	#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /!< 0x00000200 /
30	mjames	1237
		1238	#define ADC_SQR3_SQ15_Pos (10U)
50	mjames	1239	#define ADC_SQR3_SQ15_Msk (0x1FUL << ADC_SQR3_SQ15_Pos) /!< 0x00007C00 /
30	mjames	1240	#define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /!< ADC group regular sequencer rank 15 /
50	mjames	1241	#define ADC_SQR3_SQ15_0 (0x01UL << ADC_SQR3_SQ15_Pos) /!< 0x00000400 /
		1242	#define ADC_SQR3_SQ15_1 (0x02UL << ADC_SQR3_SQ15_Pos) /!< 0x00000800 /
		1243	#define ADC_SQR3_SQ15_2 (0x04UL << ADC_SQR3_SQ15_Pos) /!< 0x00001000 /
		1244	#define ADC_SQR3_SQ15_3 (0x08UL << ADC_SQR3_SQ15_Pos) /!< 0x00002000 /
		1245	#define ADC_SQR3_SQ15_4 (0x10UL << ADC_SQR3_SQ15_Pos) /!< 0x00004000 /
30	mjames	1246
		1247	#define ADC_SQR3_SQ16_Pos (15U)
50	mjames	1248	#define ADC_SQR3_SQ16_Msk (0x1FUL << ADC_SQR3_SQ16_Pos) /!< 0x000F8000 /
30	mjames	1249	#define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /!< ADC group regular sequencer rank 16 /
50	mjames	1250	#define ADC_SQR3_SQ16_0 (0x01UL << ADC_SQR3_SQ16_Pos) /!< 0x00008000 /
		1251	#define ADC_SQR3_SQ16_1 (0x02UL << ADC_SQR3_SQ16_Pos) /!< 0x00010000 /
		1252	#define ADC_SQR3_SQ16_2 (0x04UL << ADC_SQR3_SQ16_Pos) /!< 0x00020000 /
		1253	#define ADC_SQR3_SQ16_3 (0x08UL << ADC_SQR3_SQ16_Pos) /!< 0x00040000 /
		1254	#define ADC_SQR3_SQ16_4 (0x10UL << ADC_SQR3_SQ16_Pos) /!< 0x00080000 /
30	mjames	1255
		1256	#define ADC_SQR3_SQ17_Pos (20U)
50	mjames	1257	#define ADC_SQR3_SQ17_Msk (0x1FUL << ADC_SQR3_SQ17_Pos) /!< 0x01F00000 /
30	mjames	1258	#define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /!< ADC group regular sequencer rank 17 /
50	mjames	1259	#define ADC_SQR3_SQ17_0 (0x01UL << ADC_SQR3_SQ17_Pos) /!< 0x00100000 /
		1260	#define ADC_SQR3_SQ17_1 (0x02UL << ADC_SQR3_SQ17_Pos) /!< 0x00200000 /
		1261	#define ADC_SQR3_SQ17_2 (0x04UL << ADC_SQR3_SQ17_Pos) /!< 0x00400000 /
		1262	#define ADC_SQR3_SQ17_3 (0x08UL << ADC_SQR3_SQ17_Pos) /!< 0x00800000 /
		1263	#define ADC_SQR3_SQ17_4 (0x10UL << ADC_SQR3_SQ17_Pos) /!< 0x01000000 /
30	mjames	1264
		1265	#define ADC_SQR3_SQ18_Pos (25U)
50	mjames	1266	#define ADC_SQR3_SQ18_Msk (0x1FUL << ADC_SQR3_SQ18_Pos) /!< 0x3E000000 /
30	mjames	1267	#define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /!< ADC group regular sequencer rank 18 /
50	mjames	1268	#define ADC_SQR3_SQ18_0 (0x01UL << ADC_SQR3_SQ18_Pos) /!< 0x02000000 /
		1269	#define ADC_SQR3_SQ18_1 (0x02UL << ADC_SQR3_SQ18_Pos) /!< 0x04000000 /
		1270	#define ADC_SQR3_SQ18_2 (0x04UL << ADC_SQR3_SQ18_Pos) /!< 0x08000000 /
		1271	#define ADC_SQR3_SQ18_3 (0x08UL << ADC_SQR3_SQ18_Pos) /!< 0x10000000 /
		1272	#define ADC_SQR3_SQ18_4 (0x10UL << ADC_SQR3_SQ18_Pos) /!< 0x20000000 /
30	mjames	1273
		1274	/***************** Bit definition for ADC_SQR4 register *****************/
		1275	#define ADC_SQR4_SQ7_Pos (0U)
50	mjames	1276	#define ADC_SQR4_SQ7_Msk (0x1FUL << ADC_SQR4_SQ7_Pos) /!< 0x0000001F /
30	mjames	1277	#define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /!< ADC group regular sequencer rank 7 /
50	mjames	1278	#define ADC_SQR4_SQ7_0 (0x01UL << ADC_SQR4_SQ7_Pos) /!< 0x00000001 /
		1279	#define ADC_SQR4_SQ7_1 (0x02UL << ADC_SQR4_SQ7_Pos) /!< 0x00000002 /
		1280	#define ADC_SQR4_SQ7_2 (0x04UL << ADC_SQR4_SQ7_Pos) /!< 0x00000004 /
		1281	#define ADC_SQR4_SQ7_3 (0x08UL << ADC_SQR4_SQ7_Pos) /!< 0x00000008 /
		1282	#define ADC_SQR4_SQ7_4 (0x10UL << ADC_SQR4_SQ7_Pos) /!< 0x00000010 /
30	mjames	1283
		1284	#define ADC_SQR4_SQ8_Pos (5U)
50	mjames	1285	#define ADC_SQR4_SQ8_Msk (0x1FUL << ADC_SQR4_SQ8_Pos) /!< 0x000003E0 /
30	mjames	1286	#define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /!< ADC group regular sequencer rank 8 /
50	mjames	1287	#define ADC_SQR4_SQ8_0 (0x01UL << ADC_SQR4_SQ8_Pos) /!< 0x00000020 /
		1288	#define ADC_SQR4_SQ8_1 (0x02UL << ADC_SQR4_SQ8_Pos) /!< 0x00000040 /
		1289	#define ADC_SQR4_SQ8_2 (0x04UL << ADC_SQR4_SQ8_Pos) /!< 0x00000080 /
		1290	#define ADC_SQR4_SQ8_3 (0x08UL << ADC_SQR4_SQ8_Pos) /!< 0x00000100 /
		1291	#define ADC_SQR4_SQ8_4 (0x10UL << ADC_SQR4_SQ8_Pos) /!< 0x00000200 /
30	mjames	1292
		1293	#define ADC_SQR4_SQ9_Pos (10U)
50	mjames	1294	#define ADC_SQR4_SQ9_Msk (0x1FUL << ADC_SQR4_SQ9_Pos) /!< 0x00007C00 /
30	mjames	1295	#define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /!< ADC group regular sequencer rank 9 /
50	mjames	1296	#define ADC_SQR4_SQ9_0 (0x01UL << ADC_SQR4_SQ9_Pos) /!< 0x00000400 /
		1297	#define ADC_SQR4_SQ9_1 (0x02UL << ADC_SQR4_SQ9_Pos) /!< 0x00000800 /
		1298	#define ADC_SQR4_SQ9_2 (0x04UL << ADC_SQR4_SQ9_Pos) /!< 0x00001000 /
		1299	#define ADC_SQR4_SQ9_3 (0x08UL << ADC_SQR4_SQ9_Pos) /!< 0x00002000 /
		1300	#define ADC_SQR4_SQ9_4 (0x10UL << ADC_SQR4_SQ9_Pos) /!< 0x00004000 /
30	mjames	1301
		1302	#define ADC_SQR4_SQ10_Pos (15U)
50	mjames	1303	#define ADC_SQR4_SQ10_Msk (0x1FUL << ADC_SQR4_SQ10_Pos) /!< 0x000F8000 /
30	mjames	1304	#define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /!< ADC group regular sequencer rank 10 /
50	mjames	1305	#define ADC_SQR4_SQ10_0 (0x01UL << ADC_SQR4_SQ10_Pos) /!< 0x00008000 /
		1306	#define ADC_SQR4_SQ10_1 (0x02UL << ADC_SQR4_SQ10_Pos) /!< 0x00010000 /
		1307	#define ADC_SQR4_SQ10_2 (0x04UL << ADC_SQR4_SQ10_Pos) /!< 0x00020000 /
		1308	#define ADC_SQR4_SQ10_3 (0x08UL << ADC_SQR4_SQ10_Pos) /!< 0x00040000 /
		1309	#define ADC_SQR4_SQ10_4 (0x10UL << ADC_SQR4_SQ10_Pos) /!< 0x00080000 /
30	mjames	1310
		1311	#define ADC_SQR4_SQ11_Pos (20U)
50	mjames	1312	#define ADC_SQR4_SQ11_Msk (0x1FUL << ADC_SQR4_SQ11_Pos) /!< 0x01F00000 /
30	mjames	1313	#define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /!< ADC group regular sequencer rank 11 /
50	mjames	1314	#define ADC_SQR4_SQ11_0 (0x01UL << ADC_SQR4_SQ11_Pos) /!< 0x00100000 /
		1315	#define ADC_SQR4_SQ11_1 (0x02UL << ADC_SQR4_SQ11_Pos) /!< 0x00200000 /
		1316	#define ADC_SQR4_SQ11_2 (0x04UL << ADC_SQR4_SQ11_Pos) /!< 0x00400000 /
		1317	#define ADC_SQR4_SQ11_3 (0x08UL << ADC_SQR4_SQ11_Pos) /!< 0x00800000 /
		1318	#define ADC_SQR4_SQ11_4 (0x10UL << ADC_SQR4_SQ11_Pos) /!< 0x01000000 /
30	mjames	1319
		1320	#define ADC_SQR4_SQ12_Pos (25U)
50	mjames	1321	#define ADC_SQR4_SQ12_Msk (0x1FUL << ADC_SQR4_SQ12_Pos) /!< 0x3E000000 /
30	mjames	1322	#define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /!< ADC group regular sequencer rank 12 /
50	mjames	1323	#define ADC_SQR4_SQ12_0 (0x01UL << ADC_SQR4_SQ12_Pos) /!< 0x02000000 /
		1324	#define ADC_SQR4_SQ12_1 (0x02UL << ADC_SQR4_SQ12_Pos) /!< 0x04000000 /
		1325	#define ADC_SQR4_SQ12_2 (0x04UL << ADC_SQR4_SQ12_Pos) /!< 0x08000000 /
		1326	#define ADC_SQR4_SQ12_3 (0x08UL << ADC_SQR4_SQ12_Pos) /!< 0x10000000 /
		1327	#define ADC_SQR4_SQ12_4 (0x10UL << ADC_SQR4_SQ12_Pos) /!< 0x20000000 /
30	mjames	1328
		1329	/***************** Bit definition for ADC_SQR5 register *****************/
		1330	#define ADC_SQR5_SQ1_Pos (0U)
50	mjames	1331	#define ADC_SQR5_SQ1_Msk (0x1FUL << ADC_SQR5_SQ1_Pos) /!< 0x0000001F /
30	mjames	1332	#define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /!< ADC group regular sequencer rank 1 /
50	mjames	1333	#define ADC_SQR5_SQ1_0 (0x01UL << ADC_SQR5_SQ1_Pos) /!< 0x00000001 /
		1334	#define ADC_SQR5_SQ1_1 (0x02UL << ADC_SQR5_SQ1_Pos) /!< 0x00000002 /
		1335	#define ADC_SQR5_SQ1_2 (0x04UL << ADC_SQR5_SQ1_Pos) /!< 0x00000004 /
		1336	#define ADC_SQR5_SQ1_3 (0x08UL << ADC_SQR5_SQ1_Pos) /!< 0x00000008 /
		1337	#define ADC_SQR5_SQ1_4 (0x10UL << ADC_SQR5_SQ1_Pos) /!< 0x00000010 /
30	mjames	1338
		1339	#define ADC_SQR5_SQ2_Pos (5U)
50	mjames	1340	#define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /!< 0x000003E0 /
30	mjames	1341	#define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /!< ADC group regular sequencer rank 2 /
50	mjames	1342	#define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /!< 0x00000020 /
		1343	#define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /!< 0x00000040 /
		1344	#define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /!< 0x00000080 /
		1345	#define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /!< 0x00000100 /
		1346	#define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /!< 0x00000200 /
30	mjames	1347
		1348	#define ADC_SQR5_SQ3_Pos (10U)
50	mjames	1349	#define ADC_SQR5_SQ3_Msk (0x1FUL << ADC_SQR5_SQ3_Pos) /!< 0x00007C00 /
30	mjames	1350	#define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /!< ADC group regular sequencer rank 3 /
50	mjames	1351	#define ADC_SQR5_SQ3_0 (0x01UL << ADC_SQR5_SQ3_Pos) /!< 0x00000400 /
		1352	#define ADC_SQR5_SQ3_1 (0x02UL << ADC_SQR5_SQ3_Pos) /!< 0x00000800 /
		1353	#define ADC_SQR5_SQ3_2 (0x04UL << ADC_SQR5_SQ3_Pos) /!< 0x00001000 /
		1354	#define ADC_SQR5_SQ3_3 (0x08UL << ADC_SQR5_SQ3_Pos) /!< 0x00002000 /
		1355	#define ADC_SQR5_SQ3_4 (0x10UL << ADC_SQR5_SQ3_Pos) /!< 0x00004000 /
30	mjames	1356
		1357	#define ADC_SQR5_SQ4_Pos (15U)
50	mjames	1358	#define ADC_SQR5_SQ4_Msk (0x1FUL << ADC_SQR5_SQ4_Pos) /!< 0x000F8000 /
30	mjames	1359	#define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /!< ADC group regular sequencer rank 4 /
50	mjames	1360	#define ADC_SQR5_SQ4_0 (0x01UL << ADC_SQR5_SQ4_Pos) /!< 0x00008000 /
		1361	#define ADC_SQR5_SQ4_1 (0x02UL << ADC_SQR5_SQ4_Pos) /!< 0x00010000 /
		1362	#define ADC_SQR5_SQ4_2 (0x04UL << ADC_SQR5_SQ4_Pos) /!< 0x00020000 /
		1363	#define ADC_SQR5_SQ4_3 (0x08UL << ADC_SQR5_SQ4_Pos) /!< 0x00040000 /
		1364	#define ADC_SQR5_SQ4_4 (0x10UL << ADC_SQR5_SQ4_Pos) /!< 0x00080000 /
30	mjames	1365
		1366	#define ADC_SQR5_SQ5_Pos (20U)
50	mjames	1367	#define ADC_SQR5_SQ5_Msk (0x1FUL << ADC_SQR5_SQ5_Pos) /!< 0x01F00000 /
30	mjames	1368	#define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /!< ADC group regular sequencer rank 5 /
50	mjames	1369	#define ADC_SQR5_SQ5_0 (0x01UL << ADC_SQR5_SQ5_Pos) /!< 0x00100000 /
		1370	#define ADC_SQR5_SQ5_1 (0x02UL << ADC_SQR5_SQ5_Pos) /!< 0x00200000 /
		1371	#define ADC_SQR5_SQ5_2 (0x04UL << ADC_SQR5_SQ5_Pos) /!< 0x00400000 /
		1372	#define ADC_SQR5_SQ5_3 (0x08UL << ADC_SQR5_SQ5_Pos) /!< 0x00800000 /
		1373	#define ADC_SQR5_SQ5_4 (0x10UL << ADC_SQR5_SQ5_Pos) /!< 0x01000000 /
30	mjames	1374
		1375	#define ADC_SQR5_SQ6_Pos (25U)
50	mjames	1376	#define ADC_SQR5_SQ6_Msk (0x1FUL << ADC_SQR5_SQ6_Pos) /!< 0x3E000000 /
30	mjames	1377	#define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /!< ADC group regular sequencer rank 6 /
50	mjames	1378	#define ADC_SQR5_SQ6_0 (0x01UL << ADC_SQR5_SQ6_Pos) /!< 0x02000000 /
		1379	#define ADC_SQR5_SQ6_1 (0x02UL << ADC_SQR5_SQ6_Pos) /!< 0x04000000 /
		1380	#define ADC_SQR5_SQ6_2 (0x04UL << ADC_SQR5_SQ6_Pos) /!< 0x08000000 /
		1381	#define ADC_SQR5_SQ6_3 (0x08UL << ADC_SQR5_SQ6_Pos) /!< 0x10000000 /
		1382	#define ADC_SQR5_SQ6_4 (0x10UL << ADC_SQR5_SQ6_Pos) /!< 0x20000000 /
30	mjames	1383
		1384
		1385	/***************** Bit definition for ADC_JSQR register *****************/
		1386	#define ADC_JSQR_JSQ1_Pos (0U)
50	mjames	1387	#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /!< 0x0000001F /
30	mjames	1388	#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /!< ADC group injected sequencer rank 1 /
50	mjames	1389	#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000001 /
		1390	#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000002 /
		1391	#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000004 /
		1392	#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000008 /
		1393	#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /!< 0x00000010 /
30	mjames	1394
		1395	#define ADC_JSQR_JSQ2_Pos (5U)
50	mjames	1396	#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /!< 0x000003E0 /
30	mjames	1397	#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /!< ADC group injected sequencer rank 2 /
50	mjames	1398	#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000020 /
		1399	#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000040 /
		1400	#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000080 /
		1401	#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000100 /
		1402	#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /!< 0x00000200 /
30	mjames	1403
		1404	#define ADC_JSQR_JSQ3_Pos (10U)
50	mjames	1405	#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /!< 0x00007C00 /
30	mjames	1406	#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /!< ADC group injected sequencer rank 3 /
50	mjames	1407	#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /!< 0x00000400 /
		1408	#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /!< 0x00000800 /
		1409	#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /!< 0x00001000 /
		1410	#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /!< 0x00002000 /
		1411	#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /!< 0x00004000 /
30	mjames	1412
		1413	#define ADC_JSQR_JSQ4_Pos (15U)
50	mjames	1414	#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /!< 0x000F8000 /
30	mjames	1415	#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /!< ADC group injected sequencer rank 4 /
50	mjames	1416	#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /!< 0x00008000 /
		1417	#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /!< 0x00010000 /
		1418	#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /!< 0x00020000 /
		1419	#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /!< 0x00040000 /
		1420	#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /!< 0x00080000 /
30	mjames	1421
		1422	#define ADC_JSQR_JL_Pos (20U)
50	mjames	1423	#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /!< 0x00300000 /
30	mjames	1424	#define ADC_JSQR_JL ADC_JSQR_JL_Msk /!< ADC group injected sequencer scan length /
50	mjames	1425	#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /!< 0x00100000 /
		1426	#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /!< 0x00200000 /
30	mjames	1427
		1428	/***************** Bit definition for ADC_JDR1 register *****************/
		1429	#define ADC_JDR1_JDATA_Pos (0U)
50	mjames	1430	#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /!< 0x0000FFFF /
30	mjames	1431	#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /!< ADC group injected sequencer rank 1 conversion data /
		1432
		1433	/***************** Bit definition for ADC_JDR2 register *****************/
		1434	#define ADC_JDR2_JDATA_Pos (0U)
50	mjames	1435	#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /!< 0x0000FFFF /
30	mjames	1436	#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /!< ADC group injected sequencer rank 2 conversion data /
		1437
		1438	/***************** Bit definition for ADC_JDR3 register *****************/
		1439	#define ADC_JDR3_JDATA_Pos (0U)
50	mjames	1440	#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /!< 0x0000FFFF /
30	mjames	1441	#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /!< ADC group injected sequencer rank 3 conversion data /
		1442
		1443	/***************** Bit definition for ADC_JDR4 register *****************/
		1444	#define ADC_JDR4_JDATA_Pos (0U)
50	mjames	1445	#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /!< 0x0000FFFF /
30	mjames	1446	#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /!< ADC group injected sequencer rank 4 conversion data /
		1447
		1448	/****************** Bit definition for ADC_DR register ******************/
		1449	#define ADC_DR_DATA_Pos (0U)
50	mjames	1450	#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /!< 0x0000FFFF /
30	mjames	1451	#define ADC_DR_DATA ADC_DR_DATA_Msk /!< ADC group regular conversion data /
		1452
		1453	/***************** Bit definition for ADC_CSR register ******************/
		1454	#define ADC_CSR_AWD1_Pos (0U)
50	mjames	1455	#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /!< 0x00000001 /
30	mjames	1456	#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /!< ADC multimode master analog watchdog 1 flag /
		1457	#define ADC_CSR_EOCS1_Pos (1U)
50	mjames	1458	#define ADC_CSR_EOCS1_Msk (0x1UL << ADC_CSR_EOCS1_Pos) /!< 0x00000002 /
30	mjames	1459	#define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag /
		1460	#define ADC_CSR_JEOS1_Pos (2U)
50	mjames	1461	#define ADC_CSR_JEOS1_Msk (0x1UL << ADC_CSR_JEOS1_Pos) /!< 0x00000004 /
30	mjames	1462	#define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /!< ADC multimode master group injected end of sequence conversions flag /
		1463	#define ADC_CSR_JSTRT1_Pos (3U)
50	mjames	1464	#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /!< 0x00000008 /
30	mjames	1465	#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /!< ADC multimode master group injected conversion start flag /
		1466	#define ADC_CSR_STRT1_Pos (4U)
50	mjames	1467	#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /!< 0x00000010 /
30	mjames	1468	#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /!< ADC multimode master group regular conversion start flag /
		1469	#define ADC_CSR_OVR1_Pos (5U)
50	mjames	1470	#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /!< 0x00000020 /
30	mjames	1471	#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /!< ADC multimode master group regular overrun flag /
		1472	#define ADC_CSR_ADONS1_Pos (6U)
50	mjames	1473	#define ADC_CSR_ADONS1_Msk (0x1UL << ADC_CSR_ADONS1_Pos) /!< 0x00000040 /
30	mjames	1474	#define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /!< ADC multimode master ready flag /
		1475
		1476	/* Legacy defines */
		1477	#define ADC_CSR_EOC1 (ADC_CSR_EOCS1)
		1478	#define ADC_CSR_JEOC1 (ADC_CSR_JEOS1)
		1479
		1480	/***************** Bit definition for ADC_CCR register ******************/
		1481	#define ADC_CCR_ADCPRE_Pos (16U)
50	mjames	1482	#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /!< 0x00030000 /
30	mjames	1483	#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /!< ADC clock source asynchronous prescaler /
50	mjames	1484	#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /!< 0x00010000 /
		1485	#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /!< 0x00020000 /
30	mjames	1486	#define ADC_CCR_TSVREFE_Pos (23U)
50	mjames	1487	#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /!< 0x00800000 /
30	mjames	1488	#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /!< ADC internal path to VrefInt and temperature sensor enable /
		1489
		1490	/******************************************************************************/
		1491	/* */
		1492	/* Analog Comparators (COMP) */
		1493	/* */
		1494	/******************************************************************************/
		1495
		1496	/**************** Bit definition for COMP_CSR register ******************/
		1497	#define COMP_CSR_10KPU (0x00000001U) /!< Comparator 1 input plus 10K pull-up resistor /
		1498	#define COMP_CSR_400KPU (0x00000002U) /!< Comparator 1 input plus 400K pull-up resistor /
		1499	#define COMP_CSR_10KPD (0x00000004U) /!< Comparator 1 input plus 10K pull-down resistor /
		1500	#define COMP_CSR_400KPD (0x00000008U) /!< Comparator 1 input plus 400K pull-down resistor /
		1501	#define COMP_CSR_CMP1EN_Pos (4U)
50	mjames	1502	#define COMP_CSR_CMP1EN_Msk (0x1UL << COMP_CSR_CMP1EN_Pos) /!< 0x00000010 /
30	mjames	1503	#define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /!< Comparator 1 enable /
		1504	#define COMP_CSR_CMP1OUT_Pos (7U)
50	mjames	1505	#define COMP_CSR_CMP1OUT_Msk (0x1UL << COMP_CSR_CMP1OUT_Pos) /!< 0x00000080 /
30	mjames	1506	#define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /!< Comparator 1 output level /
		1507	#define COMP_CSR_SPEED_Pos (12U)
50	mjames	1508	#define COMP_CSR_SPEED_Msk (0x1UL << COMP_CSR_SPEED_Pos) /!< 0x00001000 /
30	mjames	1509	#define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /!< Comparator 2 power mode /
		1510	#define COMP_CSR_CMP2OUT_Pos (13U)
50	mjames	1511	#define COMP_CSR_CMP2OUT_Msk (0x1UL << COMP_CSR_CMP2OUT_Pos) /!< 0x00002000 /
30	mjames	1512	#define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /!< Comparator 2 output level /
		1513
		1514	#define COMP_CSR_WNDWE_Pos (17U)
50	mjames	1515	#define COMP_CSR_WNDWE_Msk (0x1UL << COMP_CSR_WNDWE_Pos) /!< 0x00020000 /
30	mjames	1516	#define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) /
		1517
		1518	#define COMP_CSR_INSEL_Pos (18U)
50	mjames	1519	#define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /!< 0x001C0000 /
30	mjames	1520	#define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /!< Comparator 2 input minus selection /
50	mjames	1521	#define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /!< 0x00040000 /
		1522	#define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /!< 0x00080000 /
		1523	#define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /!< 0x00100000 /
30	mjames	1524	#define COMP_CSR_OUTSEL_Pos (21U)
50	mjames	1525	#define COMP_CSR_OUTSEL_Msk (0x7UL << COMP_CSR_OUTSEL_Pos) /!< 0x00E00000 /
30	mjames	1526	#define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /!< Comparator 2 output redirection /
50	mjames	1527	#define COMP_CSR_OUTSEL_0 (0x1UL << COMP_CSR_OUTSEL_Pos) /!< 0x00200000 /
		1528	#define COMP_CSR_OUTSEL_1 (0x2UL << COMP_CSR_OUTSEL_Pos) /!< 0x00400000 /
		1529	#define COMP_CSR_OUTSEL_2 (0x4UL << COMP_CSR_OUTSEL_Pos) /!< 0x00800000 /
30	mjames	1530
		1531	/* Bits present in COMP register but not related to comparator */
		1532	/* (or partially related to comparator, in addition to other peripherals) */
		1533	#define COMP_CSR_VREFOUTEN_Pos (16U)
50	mjames	1534	#define COMP_CSR_VREFOUTEN_Msk (0x1UL << COMP_CSR_VREFOUTEN_Pos) /!< 0x00010000 /
30	mjames	1535	#define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /!< VrefInt output enable on GPIO group 3 /
		1536
		1537	/******************************************************************************/
		1538	/* */
		1539	/* CRC calculation unit (CRC) */
		1540	/* */
		1541	/******************************************************************************/
		1542
		1543	/***************** Bit definition for CRC_DR register *******************/
		1544	#define CRC_DR_DR_Pos (0U)
50	mjames	1545	#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /!< 0xFFFFFFFF /
30	mjames	1546	#define CRC_DR_DR CRC_DR_DR_Msk /!< Data register bits /
		1547
		1548	/***************** Bit definition for CRC_IDR register ******************/
		1549	#define CRC_IDR_IDR_Pos (0U)
50	mjames	1550	#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /!< 0x000000FF /
30	mjames	1551	#define CRC_IDR_IDR CRC_IDR_IDR_Msk /!< General-purpose 8-bit data register bits /
		1552
		1553	/****************** Bit definition for CRC_CR register ******************/
		1554	#define CRC_CR_RESET_Pos (0U)
50	mjames	1555	#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /!< 0x00000001 /
30	mjames	1556	#define CRC_CR_RESET CRC_CR_RESET_Msk /!< RESET bit /
		1557
		1558	/******************************************************************************/
		1559	/* */
		1560	/* Digital to Analog Converter (DAC) */
		1561	/* */
		1562	/******************************************************************************/
		1563
		1564	/****************** Bit definition for DAC_CR register ******************/
		1565	#define DAC_CR_EN1_Pos (0U)
50	mjames	1566	#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /!< 0x00000001 /
30	mjames	1567	#define DAC_CR_EN1 DAC_CR_EN1_Msk /!<DAC channel1 enable /
		1568	#define DAC_CR_BOFF1_Pos (1U)
50	mjames	1569	#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /!< 0x00000002 /
30	mjames	1570	#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /!<DAC channel1 output buffer disable /
		1571	#define DAC_CR_TEN1_Pos (2U)
50	mjames	1572	#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /!< 0x00000004 /
30	mjames	1573	#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /!<DAC channel1 Trigger enable /
		1574
		1575	#define DAC_CR_TSEL1_Pos (3U)
50	mjames	1576	#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /!< 0x00000038 /
30	mjames	1577	#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
50	mjames	1578	#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /!< 0x00000008 /
		1579	#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /!< 0x00000010 /
		1580	#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /!< 0x00000020 /
30	mjames	1581
		1582	#define DAC_CR_WAVE1_Pos (6U)
50	mjames	1583	#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /!< 0x000000C0 /
30	mjames	1584	#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
50	mjames	1585	#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /!< 0x00000040 /
		1586	#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /!< 0x00000080 /
30	mjames	1587
		1588	#define DAC_CR_MAMP1_Pos (8U)
50	mjames	1589	#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /!< 0x00000F00 /
30	mjames	1590	#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
50	mjames	1591	#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /!< 0x00000100 /
		1592	#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /!< 0x00000200 /
		1593	#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /!< 0x00000400 /
		1594	#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /!< 0x00000800 /
30	mjames	1595
		1596	#define DAC_CR_DMAEN1_Pos (12U)
50	mjames	1597	#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /!< 0x00001000 /
30	mjames	1598	#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /!<DAC channel1 DMA enable /
		1599	#define DAC_CR_DMAUDRIE1_Pos (13U)
50	mjames	1600	#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /!< 0x00002000 /
30	mjames	1601	#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /!<DAC channel1 DMA Interrupt enable /
		1602	#define DAC_CR_EN2_Pos (16U)
50	mjames	1603	#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /!< 0x00010000 /
30	mjames	1604	#define DAC_CR_EN2 DAC_CR_EN2_Msk /!<DAC channel2 enable /
		1605	#define DAC_CR_BOFF2_Pos (17U)
50	mjames	1606	#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /!< 0x00020000 /
30	mjames	1607	#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /!<DAC channel2 output buffer disable /
		1608	#define DAC_CR_TEN2_Pos (18U)
50	mjames	1609	#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /!< 0x00040000 /
30	mjames	1610	#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /!<DAC channel2 Trigger enable /
		1611
		1612	#define DAC_CR_TSEL2_Pos (19U)
50	mjames	1613	#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /!< 0x00380000 /
30	mjames	1614	#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
50	mjames	1615	#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /!< 0x00080000 /
		1616	#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /!< 0x00100000 /
		1617	#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /!< 0x00200000 /
30	mjames	1618
		1619	#define DAC_CR_WAVE2_Pos (22U)
50	mjames	1620	#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /!< 0x00C00000 /
30	mjames	1621	#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
50	mjames	1622	#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /!< 0x00400000 /
		1623	#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /!< 0x00800000 /
30	mjames	1624
		1625	#define DAC_CR_MAMP2_Pos (24U)
50	mjames	1626	#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /!< 0x0F000000 /
30	mjames	1627	#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
50	mjames	1628	#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /!< 0x01000000 /
		1629	#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /!< 0x02000000 /
		1630	#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /!< 0x04000000 /
		1631	#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /!< 0x08000000 /
30	mjames	1632
		1633	#define DAC_CR_DMAEN2_Pos (28U)
50	mjames	1634	#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /!< 0x10000000 /
30	mjames	1635	#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /!<DAC channel2 DMA enabled /
		1636	#define DAC_CR_DMAUDRIE2_Pos (29U)
50	mjames	1637	#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /!< 0x20000000 /
30	mjames	1638	#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /!<DAC channel2 DMA underrun interrupt enable /
		1639	/*************** Bit definition for DAC_SWTRIGR register ****************/
		1640	#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
50	mjames	1641	#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /!< 0x00000001 /
30	mjames	1642	#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /!<DAC channel1 software trigger /
		1643	#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
50	mjames	1644	#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /!< 0x00000002 /
30	mjames	1645	#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /!<DAC channel2 software trigger /
		1646
		1647	/*************** Bit definition for DAC_DHR12R1 register ****************/
		1648	#define DAC_DHR12R1_DACC1DHR_Pos (0U)
50	mjames	1649	#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /!< 0x00000FFF /
30	mjames	1650	#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /!<DAC channel1 12-bit Right aligned data /
		1651
		1652	/*************** Bit definition for DAC_DHR12L1 register ****************/
		1653	#define DAC_DHR12L1_DACC1DHR_Pos (4U)
50	mjames	1654	#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /!< 0x0000FFF0 /
30	mjames	1655	#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /!<DAC channel1 12-bit Left aligned data /
		1656
		1657	/**************** Bit definition for DAC_DHR8R1 register ****************/
		1658	#define DAC_DHR8R1_DACC1DHR_Pos (0U)
50	mjames	1659	#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /!< 0x000000FF /
30	mjames	1660	#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /!<DAC channel1 8-bit Right aligned data /
		1661
		1662	/*************** Bit definition for DAC_DHR12R2 register ****************/
		1663	#define DAC_DHR12R2_DACC2DHR_Pos (0U)
50	mjames	1664	#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /!< 0x00000FFF /
30	mjames	1665	#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /!<DAC channel2 12-bit Right aligned data /
		1666
		1667	/*************** Bit definition for DAC_DHR12L2 register ****************/
		1668	#define DAC_DHR12L2_DACC2DHR_Pos (4U)
50	mjames	1669	#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /!< 0x0000FFF0 /
30	mjames	1670	#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /!<DAC channel2 12-bit Left aligned data /
		1671
		1672	/**************** Bit definition for DAC_DHR8R2 register ****************/
		1673	#define DAC_DHR8R2_DACC2DHR_Pos (0U)
50	mjames	1674	#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /!< 0x000000FF /
30	mjames	1675	#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /!<DAC channel2 8-bit Right aligned data /
		1676
		1677	/*************** Bit definition for DAC_DHR12RD register ****************/
		1678	#define DAC_DHR12RD_DACC1DHR_Pos (0U)
50	mjames	1679	#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /!< 0x00000FFF /
30	mjames	1680	#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /!<DAC channel1 12-bit Right aligned data /
		1681	#define DAC_DHR12RD_DACC2DHR_Pos (16U)
50	mjames	1682	#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /!< 0x0FFF0000 /
30	mjames	1683	#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /!<DAC channel2 12-bit Right aligned data /
		1684
		1685	/*************** Bit definition for DAC_DHR12LD register ****************/
		1686	#define DAC_DHR12LD_DACC1DHR_Pos (4U)
50	mjames	1687	#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /!< 0x0000FFF0 /
30	mjames	1688	#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /!<DAC channel1 12-bit Left aligned data /
		1689	#define DAC_DHR12LD_DACC2DHR_Pos (20U)
50	mjames	1690	#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /!< 0xFFF00000 /
30	mjames	1691	#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /!<DAC channel2 12-bit Left aligned data /
		1692
		1693	/**************** Bit definition for DAC_DHR8RD register ****************/
		1694	#define DAC_DHR8RD_DACC1DHR_Pos (0U)
50	mjames	1695	#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /!< 0x000000FF /
30	mjames	1696	#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /!<DAC channel1 8-bit Right aligned data /
		1697	#define DAC_DHR8RD_DACC2DHR_Pos (8U)
50	mjames	1698	#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /!< 0x0000FF00 /
30	mjames	1699	#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /!<DAC channel2 8-bit Right aligned data /
		1700
		1701	/***************** Bit definition for DAC_DOR1 register *****************/
		1702	#define DAC_DOR1_DACC1DOR_Pos (0U)
50	mjames	1703	#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /!< 0x00000FFF /
30	mjames	1704	#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /!<DAC channel1 data output /
		1705
		1706	/***************** Bit definition for DAC_DOR2 register *****************/
		1707	#define DAC_DOR2_DACC2DOR_Pos (0U)
50	mjames	1708	#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /!< 0x00000FFF /
30	mjames	1709	#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /!<DAC channel2 data output /
		1710
		1711	/****************** Bit definition for DAC_SR register ******************/
		1712	#define DAC_SR_DMAUDR1_Pos (13U)
50	mjames	1713	#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /!< 0x00002000 /
30	mjames	1714	#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /!<DAC channel1 DMA underrun flag /
		1715	#define DAC_SR_DMAUDR2_Pos (29U)
50	mjames	1716	#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /!< 0x20000000 /
30	mjames	1717	#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /!<DAC channel2 DMA underrun flag /
		1718
		1719	/******************************************************************************/
		1720	/* */
		1721	/* Debug MCU (DBGMCU) */
		1722	/* */
		1723	/******************************************************************************/
		1724
		1725	/************** Bit definition for DBGMCU_IDCODE register ***************/
		1726	#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
50	mjames	1727	#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /!< 0x00000FFF /
30	mjames	1728	#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /!< Device Identifier /
		1729
		1730	#define DBGMCU_IDCODE_REV_ID_Pos (16U)
50	mjames	1731	#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0xFFFF0000 /
30	mjames	1732	#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /!< REV_ID[15:0] bits (Revision Identifier) /
50	mjames	1733	#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00010000 /
		1734	#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00020000 /
		1735	#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00040000 /
		1736	#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00080000 /
		1737	#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00100000 /
		1738	#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00200000 /
		1739	#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00400000 /
		1740	#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00800000 /
		1741	#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x01000000 /
		1742	#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x02000000 /
		1743	#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x04000000 /
		1744	#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x08000000 /
		1745	#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x10000000 /
		1746	#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x20000000 /
		1747	#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x40000000 /
		1748	#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x80000000 /
30	mjames	1749
		1750	/**************** Bit definition for DBGMCU_CR register *****************/
		1751	#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
50	mjames	1752	#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /!< 0x00000001 /
30	mjames	1753	#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /!< Debug Sleep Mode /
		1754	#define DBGMCU_CR_DBG_STOP_Pos (1U)
50	mjames	1755	#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /!< 0x00000002 /
30	mjames	1756	#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /!< Debug Stop Mode /
		1757	#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
50	mjames	1758	#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /!< 0x00000004 /
30	mjames	1759	#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /!< Debug Standby mode /
		1760	#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
50	mjames	1761	#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /!< 0x00000020 /
30	mjames	1762	#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /!< Trace Pin Assignment Control /
		1763
		1764	#define DBGMCU_CR_TRACE_MODE_Pos (6U)
50	mjames	1765	#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x000000C0 /
30	mjames	1766	#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
50	mjames	1767	#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000040 /
		1768	#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000080 /
30	mjames	1769
		1770	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
		1771
		1772	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
50	mjames	1773	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /!< 0x00000001 /
30	mjames	1774	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /!< TIM2 counter stopped when core is halted /
		1775	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
50	mjames	1776	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /!< 0x00000002 /
30	mjames	1777	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /!< TIM3 counter stopped when core is halted /
		1778	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
50	mjames	1779	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /!< 0x00000004 /
30	mjames	1780	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /!< TIM4 counter stopped when core is halted /
		1781	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
50	mjames	1782	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /!< 0x00000010 /
30	mjames	1783	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /!< TIM6 counter stopped when core is halted /
		1784	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
50	mjames	1785	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /!< 0x00000020 /
30	mjames	1786	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /!< TIM7 counter stopped when core is halted /
		1787	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
50	mjames	1788	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /!< 0x00000800 /
30	mjames	1789	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /!< Debug Window Watchdog stopped when Core is halted /
		1790	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
50	mjames	1791	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /!< 0x00001000 /
30	mjames	1792	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /!< Debug Independent Watchdog stopped when Core is halted /
		1793	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
50	mjames	1794	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /!< 0x00200000 /
30	mjames	1795	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		1796	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
50	mjames	1797	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /!< 0x00400000 /
30	mjames	1798	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		1799
		1800	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
		1801
		1802	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U)
50	mjames	1803	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /!< 0x00000004 /
30	mjames	1804	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /!< TIM9 counter stopped when core is halted /
		1805	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U)
50	mjames	1806	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /!< 0x00000008 /
30	mjames	1807	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /!< TIM10 counter stopped when core is halted /
		1808	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U)
50	mjames	1809	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /!< 0x00000010 /
30	mjames	1810	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /!< TIM11 counter stopped when core is halted /
		1811
		1812	/******************************************************************************/
		1813	/* */
		1814	/* DMA Controller (DMA) */
		1815	/* */
		1816	/******************************************************************************/
		1817
		1818	/***************** Bit definition for DMA_ISR register ******************/
		1819	#define DMA_ISR_GIF1_Pos (0U)
50	mjames	1820	#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /!< 0x00000001 /
30	mjames	1821	#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /!< Channel 1 Global interrupt flag /
		1822	#define DMA_ISR_TCIF1_Pos (1U)
50	mjames	1823	#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /!< 0x00000002 /
30	mjames	1824	#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /!< Channel 1 Transfer Complete flag /
		1825	#define DMA_ISR_HTIF1_Pos (2U)
50	mjames	1826	#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /!< 0x00000004 /
30	mjames	1827	#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /!< Channel 1 Half Transfer flag /
		1828	#define DMA_ISR_TEIF1_Pos (3U)
50	mjames	1829	#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /!< 0x00000008 /
30	mjames	1830	#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /!< Channel 1 Transfer Error flag /
		1831	#define DMA_ISR_GIF2_Pos (4U)
50	mjames	1832	#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /!< 0x00000010 /
30	mjames	1833	#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /!< Channel 2 Global interrupt flag /
		1834	#define DMA_ISR_TCIF2_Pos (5U)
50	mjames	1835	#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /!< 0x00000020 /
30	mjames	1836	#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /!< Channel 2 Transfer Complete flag /
		1837	#define DMA_ISR_HTIF2_Pos (6U)
50	mjames	1838	#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /!< 0x00000040 /
30	mjames	1839	#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /!< Channel 2 Half Transfer flag /
		1840	#define DMA_ISR_TEIF2_Pos (7U)
50	mjames	1841	#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /!< 0x00000080 /
30	mjames	1842	#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /!< Channel 2 Transfer Error flag /
		1843	#define DMA_ISR_GIF3_Pos (8U)
50	mjames	1844	#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /!< 0x00000100 /
30	mjames	1845	#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /!< Channel 3 Global interrupt flag /
		1846	#define DMA_ISR_TCIF3_Pos (9U)
50	mjames	1847	#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /!< 0x00000200 /
30	mjames	1848	#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /!< Channel 3 Transfer Complete flag /
		1849	#define DMA_ISR_HTIF3_Pos (10U)
50	mjames	1850	#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /!< 0x00000400 /
30	mjames	1851	#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /!< Channel 3 Half Transfer flag /
		1852	#define DMA_ISR_TEIF3_Pos (11U)
50	mjames	1853	#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /!< 0x00000800 /
30	mjames	1854	#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /!< Channel 3 Transfer Error flag /
		1855	#define DMA_ISR_GIF4_Pos (12U)
50	mjames	1856	#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /!< 0x00001000 /
30	mjames	1857	#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /!< Channel 4 Global interrupt flag /
		1858	#define DMA_ISR_TCIF4_Pos (13U)
50	mjames	1859	#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /!< 0x00002000 /
30	mjames	1860	#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /!< Channel 4 Transfer Complete flag /
		1861	#define DMA_ISR_HTIF4_Pos (14U)
50	mjames	1862	#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /!< 0x00004000 /
30	mjames	1863	#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /!< Channel 4 Half Transfer flag /
		1864	#define DMA_ISR_TEIF4_Pos (15U)
50	mjames	1865	#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /!< 0x00008000 /
30	mjames	1866	#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /!< Channel 4 Transfer Error flag /
		1867	#define DMA_ISR_GIF5_Pos (16U)
50	mjames	1868	#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /!< 0x00010000 /
30	mjames	1869	#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /!< Channel 5 Global interrupt flag /
		1870	#define DMA_ISR_TCIF5_Pos (17U)
50	mjames	1871	#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /!< 0x00020000 /
30	mjames	1872	#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /!< Channel 5 Transfer Complete flag /
		1873	#define DMA_ISR_HTIF5_Pos (18U)
50	mjames	1874	#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /!< 0x00040000 /
30	mjames	1875	#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /!< Channel 5 Half Transfer flag /
		1876	#define DMA_ISR_TEIF5_Pos (19U)
50	mjames	1877	#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /!< 0x00080000 /
30	mjames	1878	#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /!< Channel 5 Transfer Error flag /
		1879	#define DMA_ISR_GIF6_Pos (20U)
50	mjames	1880	#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /!< 0x00100000 /
30	mjames	1881	#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /!< Channel 6 Global interrupt flag /
		1882	#define DMA_ISR_TCIF6_Pos (21U)
50	mjames	1883	#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /!< 0x00200000 /
30	mjames	1884	#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /!< Channel 6 Transfer Complete flag /
		1885	#define DMA_ISR_HTIF6_Pos (22U)
50	mjames	1886	#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /!< 0x00400000 /
30	mjames	1887	#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /!< Channel 6 Half Transfer flag /
		1888	#define DMA_ISR_TEIF6_Pos (23U)
50	mjames	1889	#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /!< 0x00800000 /
30	mjames	1890	#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /!< Channel 6 Transfer Error flag /
		1891	#define DMA_ISR_GIF7_Pos (24U)
50	mjames	1892	#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /!< 0x01000000 /
30	mjames	1893	#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /!< Channel 7 Global interrupt flag /
		1894	#define DMA_ISR_TCIF7_Pos (25U)
50	mjames	1895	#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /!< 0x02000000 /
30	mjames	1896	#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /!< Channel 7 Transfer Complete flag /
		1897	#define DMA_ISR_HTIF7_Pos (26U)
50	mjames	1898	#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /!< 0x04000000 /
30	mjames	1899	#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /!< Channel 7 Half Transfer flag /
		1900	#define DMA_ISR_TEIF7_Pos (27U)
50	mjames	1901	#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /!< 0x08000000 /
30	mjames	1902	#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /!< Channel 7 Transfer Error flag /
		1903
		1904	/***************** Bit definition for DMA_IFCR register *****************/
		1905	#define DMA_IFCR_CGIF1_Pos (0U)
50	mjames	1906	#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /!< 0x00000001 /
30	mjames	1907	#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /!< Channel 1 Global interrupt clear /
		1908	#define DMA_IFCR_CTCIF1_Pos (1U)
50	mjames	1909	#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /!< 0x00000002 /
30	mjames	1910	#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /!< Channel 1 Transfer Complete clear /
		1911	#define DMA_IFCR_CHTIF1_Pos (2U)
50	mjames	1912	#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /!< 0x00000004 /
30	mjames	1913	#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /!< Channel 1 Half Transfer clear /
		1914	#define DMA_IFCR_CTEIF1_Pos (3U)
50	mjames	1915	#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /!< 0x00000008 /
30	mjames	1916	#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /!< Channel 1 Transfer Error clear /
		1917	#define DMA_IFCR_CGIF2_Pos (4U)
50	mjames	1918	#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /!< 0x00000010 /
30	mjames	1919	#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /!< Channel 2 Global interrupt clear /
		1920	#define DMA_IFCR_CTCIF2_Pos (5U)
50	mjames	1921	#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /!< 0x00000020 /
30	mjames	1922	#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /!< Channel 2 Transfer Complete clear /
		1923	#define DMA_IFCR_CHTIF2_Pos (6U)
50	mjames	1924	#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /!< 0x00000040 /
30	mjames	1925	#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /!< Channel 2 Half Transfer clear /
		1926	#define DMA_IFCR_CTEIF2_Pos (7U)
50	mjames	1927	#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /!< 0x00000080 /
30	mjames	1928	#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /!< Channel 2 Transfer Error clear /
		1929	#define DMA_IFCR_CGIF3_Pos (8U)
50	mjames	1930	#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /!< 0x00000100 /
30	mjames	1931	#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /!< Channel 3 Global interrupt clear /
		1932	#define DMA_IFCR_CTCIF3_Pos (9U)
50	mjames	1933	#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /!< 0x00000200 /
30	mjames	1934	#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /!< Channel 3 Transfer Complete clear /
		1935	#define DMA_IFCR_CHTIF3_Pos (10U)
50	mjames	1936	#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /!< 0x00000400 /
30	mjames	1937	#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /!< Channel 3 Half Transfer clear /
		1938	#define DMA_IFCR_CTEIF3_Pos (11U)
50	mjames	1939	#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /!< 0x00000800 /
30	mjames	1940	#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /!< Channel 3 Transfer Error clear /
		1941	#define DMA_IFCR_CGIF4_Pos (12U)
50	mjames	1942	#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /!< 0x00001000 /
30	mjames	1943	#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /!< Channel 4 Global interrupt clear /
		1944	#define DMA_IFCR_CTCIF4_Pos (13U)
50	mjames	1945	#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /!< 0x00002000 /
30	mjames	1946	#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /!< Channel 4 Transfer Complete clear /
		1947	#define DMA_IFCR_CHTIF4_Pos (14U)
50	mjames	1948	#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /!< 0x00004000 /
30	mjames	1949	#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /!< Channel 4 Half Transfer clear /
		1950	#define DMA_IFCR_CTEIF4_Pos (15U)
50	mjames	1951	#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /!< 0x00008000 /
30	mjames	1952	#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /!< Channel 4 Transfer Error clear /
		1953	#define DMA_IFCR_CGIF5_Pos (16U)
50	mjames	1954	#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /!< 0x00010000 /
30	mjames	1955	#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /!< Channel 5 Global interrupt clear /
		1956	#define DMA_IFCR_CTCIF5_Pos (17U)
50	mjames	1957	#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /!< 0x00020000 /
30	mjames	1958	#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /!< Channel 5 Transfer Complete clear /
		1959	#define DMA_IFCR_CHTIF5_Pos (18U)
50	mjames	1960	#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /!< 0x00040000 /
30	mjames	1961	#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /!< Channel 5 Half Transfer clear /
		1962	#define DMA_IFCR_CTEIF5_Pos (19U)
50	mjames	1963	#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /!< 0x00080000 /
30	mjames	1964	#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /!< Channel 5 Transfer Error clear /
		1965	#define DMA_IFCR_CGIF6_Pos (20U)
50	mjames	1966	#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /!< 0x00100000 /
30	mjames	1967	#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /!< Channel 6 Global interrupt clear /
		1968	#define DMA_IFCR_CTCIF6_Pos (21U)
50	mjames	1969	#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /!< 0x00200000 /
30	mjames	1970	#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /!< Channel 6 Transfer Complete clear /
		1971	#define DMA_IFCR_CHTIF6_Pos (22U)
50	mjames	1972	#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /!< 0x00400000 /
30	mjames	1973	#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /!< Channel 6 Half Transfer clear /
		1974	#define DMA_IFCR_CTEIF6_Pos (23U)
50	mjames	1975	#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /!< 0x00800000 /
30	mjames	1976	#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /!< Channel 6 Transfer Error clear /
		1977	#define DMA_IFCR_CGIF7_Pos (24U)
50	mjames	1978	#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /!< 0x01000000 /
30	mjames	1979	#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /!< Channel 7 Global interrupt clear /
		1980	#define DMA_IFCR_CTCIF7_Pos (25U)
50	mjames	1981	#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /!< 0x02000000 /
30	mjames	1982	#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /!< Channel 7 Transfer Complete clear /
		1983	#define DMA_IFCR_CHTIF7_Pos (26U)
50	mjames	1984	#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /!< 0x04000000 /
30	mjames	1985	#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /!< Channel 7 Half Transfer clear /
		1986	#define DMA_IFCR_CTEIF7_Pos (27U)
50	mjames	1987	#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /!< 0x08000000 /
30	mjames	1988	#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /!< Channel 7 Transfer Error clear /
		1989
		1990	/***************** Bit definition for DMA_CCR register *****************/
		1991	#define DMA_CCR_EN_Pos (0U)
50	mjames	1992	#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /!< 0x00000001 /
30	mjames	1993	#define DMA_CCR_EN DMA_CCR_EN_Msk /!< Channel enable/
		1994	#define DMA_CCR_TCIE_Pos (1U)
50	mjames	1995	#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /!< 0x00000002 /
30	mjames	1996	#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /!< Transfer complete interrupt enable /
		1997	#define DMA_CCR_HTIE_Pos (2U)
50	mjames	1998	#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /!< 0x00000004 /
30	mjames	1999	#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /!< Half Transfer interrupt enable /
		2000	#define DMA_CCR_TEIE_Pos (3U)
50	mjames	2001	#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /!< 0x00000008 /
30	mjames	2002	#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /!< Transfer error interrupt enable /
		2003	#define DMA_CCR_DIR_Pos (4U)
50	mjames	2004	#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /!< 0x00000010 /
30	mjames	2005	#define DMA_CCR_DIR DMA_CCR_DIR_Msk /!< Data transfer direction /
		2006	#define DMA_CCR_CIRC_Pos (5U)
50	mjames	2007	#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /!< 0x00000020 /
30	mjames	2008	#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /!< Circular mode /
		2009	#define DMA_CCR_PINC_Pos (6U)
50	mjames	2010	#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /!< 0x00000040 /
30	mjames	2011	#define DMA_CCR_PINC DMA_CCR_PINC_Msk /!< Peripheral increment mode /
		2012	#define DMA_CCR_MINC_Pos (7U)
50	mjames	2013	#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /!< 0x00000080 /
30	mjames	2014	#define DMA_CCR_MINC DMA_CCR_MINC_Msk /!< Memory increment mode /
		2015
		2016	#define DMA_CCR_PSIZE_Pos (8U)
50	mjames	2017	#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /!< 0x00000300 /
30	mjames	2018	#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /!< PSIZE[1:0] bits (Peripheral size) /
50	mjames	2019	#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /!< 0x00000100 /
		2020	#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /!< 0x00000200 /
30	mjames	2021
		2022	#define DMA_CCR_MSIZE_Pos (10U)
50	mjames	2023	#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /!< 0x00000C00 /
30	mjames	2024	#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /!< MSIZE[1:0] bits (Memory size) /
50	mjames	2025	#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /!< 0x00000400 /
		2026	#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /!< 0x00000800 /
30	mjames	2027
		2028	#define DMA_CCR_PL_Pos (12U)
50	mjames	2029	#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /!< 0x00003000 /
30	mjames	2030	#define DMA_CCR_PL DMA_CCR_PL_Msk /!< PL[1:0] bits(Channel Priority level) /
50	mjames	2031	#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /!< 0x00001000 /
		2032	#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /!< 0x00002000 /
30	mjames	2033
		2034	#define DMA_CCR_MEM2MEM_Pos (14U)
50	mjames	2035	#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /!< 0x00004000 /
30	mjames	2036	#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /!< Memory to memory mode /
		2037
		2038	/**************** Bit definition generic for DMA_CNDTR register *****************/
		2039	#define DMA_CNDTR_NDT_Pos (0U)
50	mjames	2040	#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /!< 0x0000FFFF /
30	mjames	2041	#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /!< Number of data to Transfer /
		2042
		2043	/**************** Bit definition for DMA_CNDTR1 register ****************/
		2044	#define DMA_CNDTR1_NDT_Pos (0U)
50	mjames	2045	#define DMA_CNDTR1_NDT_Msk (0xFFFFUL << DMA_CNDTR1_NDT_Pos) /!< 0x0000FFFF /
30	mjames	2046	#define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /!< Number of data to Transfer /
		2047
		2048	/**************** Bit definition for DMA_CNDTR2 register ****************/
		2049	#define DMA_CNDTR2_NDT_Pos (0U)
50	mjames	2050	#define DMA_CNDTR2_NDT_Msk (0xFFFFUL << DMA_CNDTR2_NDT_Pos) /!< 0x0000FFFF /
30	mjames	2051	#define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /!< Number of data to Transfer /
		2052
		2053	/**************** Bit definition for DMA_CNDTR3 register ****************/
		2054	#define DMA_CNDTR3_NDT_Pos (0U)
50	mjames	2055	#define DMA_CNDTR3_NDT_Msk (0xFFFFUL << DMA_CNDTR3_NDT_Pos) /!< 0x0000FFFF /
30	mjames	2056	#define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /!< Number of data to Transfer /
		2057
		2058	/**************** Bit definition for DMA_CNDTR4 register ****************/
		2059	#define DMA_CNDTR4_NDT_Pos (0U)
50	mjames	2060	#define DMA_CNDTR4_NDT_Msk (0xFFFFUL << DMA_CNDTR4_NDT_Pos) /!< 0x0000FFFF /
30	mjames	2061	#define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /!< Number of data to Transfer /
		2062
		2063	/**************** Bit definition for DMA_CNDTR5 register ****************/
		2064	#define DMA_CNDTR5_NDT_Pos (0U)
50	mjames	2065	#define DMA_CNDTR5_NDT_Msk (0xFFFFUL << DMA_CNDTR5_NDT_Pos) /!< 0x0000FFFF /
30	mjames	2066	#define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /!< Number of data to Transfer /
		2067
		2068	/**************** Bit definition for DMA_CNDTR6 register ****************/
		2069	#define DMA_CNDTR6_NDT_Pos (0U)
50	mjames	2070	#define DMA_CNDTR6_NDT_Msk (0xFFFFUL << DMA_CNDTR6_NDT_Pos) /!< 0x0000FFFF /
30	mjames	2071	#define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /!< Number of data to Transfer /
		2072
		2073	/**************** Bit definition for DMA_CNDTR7 register ****************/
		2074	#define DMA_CNDTR7_NDT_Pos (0U)
50	mjames	2075	#define DMA_CNDTR7_NDT_Msk (0xFFFFUL << DMA_CNDTR7_NDT_Pos) /!< 0x0000FFFF /
30	mjames	2076	#define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /!< Number of data to Transfer /
		2077
		2078	/**************** Bit definition generic for DMA_CPAR register ******************/
		2079	#define DMA_CPAR_PA_Pos (0U)
50	mjames	2080	#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /!< 0xFFFFFFFF /
30	mjames	2081	#define DMA_CPAR_PA DMA_CPAR_PA_Msk /!< Peripheral Address /
		2082
		2083	/**************** Bit definition for DMA_CPAR1 register *****************/
		2084	#define DMA_CPAR1_PA_Pos (0U)
50	mjames	2085	#define DMA_CPAR1_PA_Msk (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos) /!< 0xFFFFFFFF /
30	mjames	2086	#define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /!< Peripheral Address /
		2087
		2088	/**************** Bit definition for DMA_CPAR2 register *****************/
		2089	#define DMA_CPAR2_PA_Pos (0U)
50	mjames	2090	#define DMA_CPAR2_PA_Msk (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos) /!< 0xFFFFFFFF /
30	mjames	2091	#define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /!< Peripheral Address /
		2092
		2093	/**************** Bit definition for DMA_CPAR3 register *****************/
		2094	#define DMA_CPAR3_PA_Pos (0U)
50	mjames	2095	#define DMA_CPAR3_PA_Msk (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos) /!< 0xFFFFFFFF /
30	mjames	2096	#define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /!< Peripheral Address /
		2097
		2098
		2099	/**************** Bit definition for DMA_CPAR4 register *****************/
		2100	#define DMA_CPAR4_PA_Pos (0U)
50	mjames	2101	#define DMA_CPAR4_PA_Msk (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos) /!< 0xFFFFFFFF /
30	mjames	2102	#define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /!< Peripheral Address /
		2103
		2104	/**************** Bit definition for DMA_CPAR5 register *****************/
		2105	#define DMA_CPAR5_PA_Pos (0U)
50	mjames	2106	#define DMA_CPAR5_PA_Msk (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos) /!< 0xFFFFFFFF /
30	mjames	2107	#define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /!< Peripheral Address /
		2108
		2109	/**************** Bit definition for DMA_CPAR6 register *****************/
		2110	#define DMA_CPAR6_PA_Pos (0U)
50	mjames	2111	#define DMA_CPAR6_PA_Msk (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos) /!< 0xFFFFFFFF /
30	mjames	2112	#define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /!< Peripheral Address /
		2113
		2114
		2115	/**************** Bit definition for DMA_CPAR7 register *****************/
		2116	#define DMA_CPAR7_PA_Pos (0U)
50	mjames	2117	#define DMA_CPAR7_PA_Msk (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos) /!< 0xFFFFFFFF /
30	mjames	2118	#define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /!< Peripheral Address /
		2119
		2120	/**************** Bit definition generic for DMA_CMAR register ******************/
		2121	#define DMA_CMAR_MA_Pos (0U)
50	mjames	2122	#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /!< 0xFFFFFFFF /
30	mjames	2123	#define DMA_CMAR_MA DMA_CMAR_MA_Msk /!< Memory Address /
		2124
		2125	/**************** Bit definition for DMA_CMAR1 register *****************/
		2126	#define DMA_CMAR1_MA_Pos (0U)
50	mjames	2127	#define DMA_CMAR1_MA_Msk (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos) /!< 0xFFFFFFFF /
30	mjames	2128	#define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /!< Memory Address /
		2129
		2130	/**************** Bit definition for DMA_CMAR2 register *****************/
		2131	#define DMA_CMAR2_MA_Pos (0U)
50	mjames	2132	#define DMA_CMAR2_MA_Msk (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos) /!< 0xFFFFFFFF /
30	mjames	2133	#define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /!< Memory Address /
		2134
		2135	/**************** Bit definition for DMA_CMAR3 register *****************/
		2136	#define DMA_CMAR3_MA_Pos (0U)
50	mjames	2137	#define DMA_CMAR3_MA_Msk (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos) /!< 0xFFFFFFFF /
30	mjames	2138	#define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /!< Memory Address /
		2139
		2140
		2141	/**************** Bit definition for DMA_CMAR4 register *****************/
		2142	#define DMA_CMAR4_MA_Pos (0U)
50	mjames	2143	#define DMA_CMAR4_MA_Msk (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos) /!< 0xFFFFFFFF /
30	mjames	2144	#define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /!< Memory Address /
		2145
		2146	/**************** Bit definition for DMA_CMAR5 register *****************/
		2147	#define DMA_CMAR5_MA_Pos (0U)
50	mjames	2148	#define DMA_CMAR5_MA_Msk (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos) /!< 0xFFFFFFFF /
30	mjames	2149	#define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /!< Memory Address /
		2150
		2151	/**************** Bit definition for DMA_CMAR6 register *****************/
		2152	#define DMA_CMAR6_MA_Pos (0U)
50	mjames	2153	#define DMA_CMAR6_MA_Msk (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos) /!< 0xFFFFFFFF /
30	mjames	2154	#define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /!< Memory Address /
		2155
		2156	/**************** Bit definition for DMA_CMAR7 register *****************/
		2157	#define DMA_CMAR7_MA_Pos (0U)
50	mjames	2158	#define DMA_CMAR7_MA_Msk (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos) /!< 0xFFFFFFFF /
30	mjames	2159	#define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /!< Memory Address /
		2160
		2161	/******************************************************************************/
		2162	/* */
		2163	/* External Interrupt/Event Controller (EXTI) */
		2164	/* */
		2165	/******************************************************************************/
		2166
		2167	/***************** Bit definition for EXTI_IMR register *****************/
		2168	#define EXTI_IMR_MR0_Pos (0U)
50	mjames	2169	#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /!< 0x00000001 /
30	mjames	2170	#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /!< Interrupt Mask on line 0 /
		2171	#define EXTI_IMR_MR1_Pos (1U)
50	mjames	2172	#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /!< 0x00000002 /
30	mjames	2173	#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /!< Interrupt Mask on line 1 /
		2174	#define EXTI_IMR_MR2_Pos (2U)
50	mjames	2175	#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /!< 0x00000004 /
30	mjames	2176	#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /!< Interrupt Mask on line 2 /
		2177	#define EXTI_IMR_MR3_Pos (3U)
50	mjames	2178	#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /!< 0x00000008 /
30	mjames	2179	#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /!< Interrupt Mask on line 3 /
		2180	#define EXTI_IMR_MR4_Pos (4U)
50	mjames	2181	#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /!< 0x00000010 /
30	mjames	2182	#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /!< Interrupt Mask on line 4 /
		2183	#define EXTI_IMR_MR5_Pos (5U)
50	mjames	2184	#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /!< 0x00000020 /
30	mjames	2185	#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /!< Interrupt Mask on line 5 /
		2186	#define EXTI_IMR_MR6_Pos (6U)
50	mjames	2187	#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /!< 0x00000040 /
30	mjames	2188	#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /!< Interrupt Mask on line 6 /
		2189	#define EXTI_IMR_MR7_Pos (7U)
50	mjames	2190	#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /!< 0x00000080 /
30	mjames	2191	#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /!< Interrupt Mask on line 7 /
		2192	#define EXTI_IMR_MR8_Pos (8U)
50	mjames	2193	#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /!< 0x00000100 /
30	mjames	2194	#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /!< Interrupt Mask on line 8 /
		2195	#define EXTI_IMR_MR9_Pos (9U)
50	mjames	2196	#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /!< 0x00000200 /
30	mjames	2197	#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /!< Interrupt Mask on line 9 /
		2198	#define EXTI_IMR_MR10_Pos (10U)
50	mjames	2199	#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /!< 0x00000400 /
30	mjames	2200	#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /!< Interrupt Mask on line 10 /
		2201	#define EXTI_IMR_MR11_Pos (11U)
50	mjames	2202	#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /!< 0x00000800 /
30	mjames	2203	#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /!< Interrupt Mask on line 11 /
		2204	#define EXTI_IMR_MR12_Pos (12U)
50	mjames	2205	#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /!< 0x00001000 /
30	mjames	2206	#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /!< Interrupt Mask on line 12 /
		2207	#define EXTI_IMR_MR13_Pos (13U)
50	mjames	2208	#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /!< 0x00002000 /
30	mjames	2209	#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /!< Interrupt Mask on line 13 /
		2210	#define EXTI_IMR_MR14_Pos (14U)
50	mjames	2211	#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /!< 0x00004000 /
30	mjames	2212	#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /!< Interrupt Mask on line 14 /
		2213	#define EXTI_IMR_MR15_Pos (15U)
50	mjames	2214	#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /!< 0x00008000 /
30	mjames	2215	#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /!< Interrupt Mask on line 15 /
		2216	#define EXTI_IMR_MR16_Pos (16U)
50	mjames	2217	#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /!< 0x00010000 /
30	mjames	2218	#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /!< Interrupt Mask on line 16 /
		2219	#define EXTI_IMR_MR17_Pos (17U)
50	mjames	2220	#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /!< 0x00020000 /
30	mjames	2221	#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /!< Interrupt Mask on line 17 /
		2222	#define EXTI_IMR_MR18_Pos (18U)
50	mjames	2223	#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /!< 0x00040000 /
30	mjames	2224	#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /!< Interrupt Mask on line 18 /
		2225	#define EXTI_IMR_MR19_Pos (19U)
50	mjames	2226	#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /!< 0x00080000 /
30	mjames	2227	#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /!< Interrupt Mask on line 19 /
		2228	#define EXTI_IMR_MR20_Pos (20U)
50	mjames	2229	#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /!< 0x00100000 /
30	mjames	2230	#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /!< Interrupt Mask on line 20 /
		2231	#define EXTI_IMR_MR21_Pos (21U)
50	mjames	2232	#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /!< 0x00200000 /
30	mjames	2233	#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /!< Interrupt Mask on line 21 /
		2234	#define EXTI_IMR_MR22_Pos (22U)
50	mjames	2235	#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /!< 0x00400000 /
30	mjames	2236	#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /!< Interrupt Mask on line 22 /
		2237	/* Catgeroy 1 & 2 */
		2238
		2239	/* References Defines */
		2240	#define EXTI_IMR_IM0 EXTI_IMR_MR0
		2241	#define EXTI_IMR_IM1 EXTI_IMR_MR1
		2242	#define EXTI_IMR_IM2 EXTI_IMR_MR2
		2243	#define EXTI_IMR_IM3 EXTI_IMR_MR3
		2244	#define EXTI_IMR_IM4 EXTI_IMR_MR4
		2245	#define EXTI_IMR_IM5 EXTI_IMR_MR5
		2246	#define EXTI_IMR_IM6 EXTI_IMR_MR6
		2247	#define EXTI_IMR_IM7 EXTI_IMR_MR7
		2248	#define EXTI_IMR_IM8 EXTI_IMR_MR8
		2249	#define EXTI_IMR_IM9 EXTI_IMR_MR9
		2250	#define EXTI_IMR_IM10 EXTI_IMR_MR10
		2251	#define EXTI_IMR_IM11 EXTI_IMR_MR11
		2252	#define EXTI_IMR_IM12 EXTI_IMR_MR12
		2253	#define EXTI_IMR_IM13 EXTI_IMR_MR13
		2254	#define EXTI_IMR_IM14 EXTI_IMR_MR14
		2255	#define EXTI_IMR_IM15 EXTI_IMR_MR15
		2256	#define EXTI_IMR_IM16 EXTI_IMR_MR16
		2257	#define EXTI_IMR_IM17 EXTI_IMR_MR17
		2258	#define EXTI_IMR_IM18 EXTI_IMR_MR18
		2259	#define EXTI_IMR_IM19 EXTI_IMR_MR19
		2260	#define EXTI_IMR_IM20 EXTI_IMR_MR20
		2261	#define EXTI_IMR_IM21 EXTI_IMR_MR21
		2262	#define EXTI_IMR_IM22 EXTI_IMR_MR22
		2263	/* Catgeroy 1 & 2 */
		2264	#define EXTI_IMR_IM_Pos (0U)
50	mjames	2265	#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos) /!< 0x007FFFFF /
30	mjames	2266	#define EXTI_IMR_IM EXTI_IMR_IM_Msk /!< Interrupt Mask All /
		2267
		2268	/***************** Bit definition for EXTI_EMR register *****************/
		2269	#define EXTI_EMR_MR0_Pos (0U)
50	mjames	2270	#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /!< 0x00000001 /
30	mjames	2271	#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /!< Event Mask on line 0 /
		2272	#define EXTI_EMR_MR1_Pos (1U)
50	mjames	2273	#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /!< 0x00000002 /
30	mjames	2274	#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /!< Event Mask on line 1 /
		2275	#define EXTI_EMR_MR2_Pos (2U)
50	mjames	2276	#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /!< 0x00000004 /
30	mjames	2277	#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /!< Event Mask on line 2 /
		2278	#define EXTI_EMR_MR3_Pos (3U)
50	mjames	2279	#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /!< 0x00000008 /
30	mjames	2280	#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /!< Event Mask on line 3 /
		2281	#define EXTI_EMR_MR4_Pos (4U)
50	mjames	2282	#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /!< 0x00000010 /
30	mjames	2283	#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /!< Event Mask on line 4 /
		2284	#define EXTI_EMR_MR5_Pos (5U)
50	mjames	2285	#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /!< 0x00000020 /
30	mjames	2286	#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /!< Event Mask on line 5 /
		2287	#define EXTI_EMR_MR6_Pos (6U)
50	mjames	2288	#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /!< 0x00000040 /
30	mjames	2289	#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /!< Event Mask on line 6 /
		2290	#define EXTI_EMR_MR7_Pos (7U)
50	mjames	2291	#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /!< 0x00000080 /
30	mjames	2292	#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /!< Event Mask on line 7 /
		2293	#define EXTI_EMR_MR8_Pos (8U)
50	mjames	2294	#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /!< 0x00000100 /
30	mjames	2295	#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /!< Event Mask on line 8 /
		2296	#define EXTI_EMR_MR9_Pos (9U)
50	mjames	2297	#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /!< 0x00000200 /
30	mjames	2298	#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /!< Event Mask on line 9 /
		2299	#define EXTI_EMR_MR10_Pos (10U)
50	mjames	2300	#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /!< 0x00000400 /
30	mjames	2301	#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /!< Event Mask on line 10 /
		2302	#define EXTI_EMR_MR11_Pos (11U)
50	mjames	2303	#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /!< 0x00000800 /
30	mjames	2304	#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /!< Event Mask on line 11 /
		2305	#define EXTI_EMR_MR12_Pos (12U)
50	mjames	2306	#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /!< 0x00001000 /
30	mjames	2307	#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /!< Event Mask on line 12 /
		2308	#define EXTI_EMR_MR13_Pos (13U)
50	mjames	2309	#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /!< 0x00002000 /
30	mjames	2310	#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /!< Event Mask on line 13 /
		2311	#define EXTI_EMR_MR14_Pos (14U)
50	mjames	2312	#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /!< 0x00004000 /
30	mjames	2313	#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /!< Event Mask on line 14 /
		2314	#define EXTI_EMR_MR15_Pos (15U)
50	mjames	2315	#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /!< 0x00008000 /
30	mjames	2316	#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /!< Event Mask on line 15 /
		2317	#define EXTI_EMR_MR16_Pos (16U)
50	mjames	2318	#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /!< 0x00010000 /
30	mjames	2319	#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /!< Event Mask on line 16 /
		2320	#define EXTI_EMR_MR17_Pos (17U)
50	mjames	2321	#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /!< 0x00020000 /
30	mjames	2322	#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /!< Event Mask on line 17 /
		2323	#define EXTI_EMR_MR18_Pos (18U)
50	mjames	2324	#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /!< 0x00040000 /
30	mjames	2325	#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /!< Event Mask on line 18 /
		2326	#define EXTI_EMR_MR19_Pos (19U)
50	mjames	2327	#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /!< 0x00080000 /
30	mjames	2328	#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /!< Event Mask on line 19 /
		2329	#define EXTI_EMR_MR20_Pos (20U)
50	mjames	2330	#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /!< 0x00100000 /
30	mjames	2331	#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /!< Event Mask on line 20 /
		2332	#define EXTI_EMR_MR21_Pos (21U)
50	mjames	2333	#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /!< 0x00200000 /
30	mjames	2334	#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /!< Event Mask on line 21 /
		2335	#define EXTI_EMR_MR22_Pos (22U)
50	mjames	2336	#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /!< 0x00400000 /
30	mjames	2337	#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /!< Event Mask on line 22 /
		2338
		2339	/* References Defines */
		2340	#define EXTI_EMR_EM0 EXTI_EMR_MR0
		2341	#define EXTI_EMR_EM1 EXTI_EMR_MR1
		2342	#define EXTI_EMR_EM2 EXTI_EMR_MR2
		2343	#define EXTI_EMR_EM3 EXTI_EMR_MR3
		2344	#define EXTI_EMR_EM4 EXTI_EMR_MR4
		2345	#define EXTI_EMR_EM5 EXTI_EMR_MR5
		2346	#define EXTI_EMR_EM6 EXTI_EMR_MR6
		2347	#define EXTI_EMR_EM7 EXTI_EMR_MR7
		2348	#define EXTI_EMR_EM8 EXTI_EMR_MR8
		2349	#define EXTI_EMR_EM9 EXTI_EMR_MR9
		2350	#define EXTI_EMR_EM10 EXTI_EMR_MR10
		2351	#define EXTI_EMR_EM11 EXTI_EMR_MR11
		2352	#define EXTI_EMR_EM12 EXTI_EMR_MR12
		2353	#define EXTI_EMR_EM13 EXTI_EMR_MR13
		2354	#define EXTI_EMR_EM14 EXTI_EMR_MR14
		2355	#define EXTI_EMR_EM15 EXTI_EMR_MR15
		2356	#define EXTI_EMR_EM16 EXTI_EMR_MR16
		2357	#define EXTI_EMR_EM17 EXTI_EMR_MR17
		2358	#define EXTI_EMR_EM18 EXTI_EMR_MR18
		2359	#define EXTI_EMR_EM19 EXTI_EMR_MR19
		2360	#define EXTI_EMR_EM20 EXTI_EMR_MR20
		2361	#define EXTI_EMR_EM21 EXTI_EMR_MR21
		2362	#define EXTI_EMR_EM22 EXTI_EMR_MR22
		2363
		2364	/**************** Bit definition for EXTI_RTSR register *****************/
		2365	#define EXTI_RTSR_TR0_Pos (0U)
50	mjames	2366	#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /!< 0x00000001 /
30	mjames	2367	#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /!< Rising trigger event configuration bit of line 0 /
		2368	#define EXTI_RTSR_TR1_Pos (1U)
50	mjames	2369	#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /!< 0x00000002 /
30	mjames	2370	#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /!< Rising trigger event configuration bit of line 1 /
		2371	#define EXTI_RTSR_TR2_Pos (2U)
50	mjames	2372	#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /!< 0x00000004 /
30	mjames	2373	#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /!< Rising trigger event configuration bit of line 2 /
		2374	#define EXTI_RTSR_TR3_Pos (3U)
50	mjames	2375	#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /!< 0x00000008 /
30	mjames	2376	#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /!< Rising trigger event configuration bit of line 3 /
		2377	#define EXTI_RTSR_TR4_Pos (4U)
50	mjames	2378	#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /!< 0x00000010 /
30	mjames	2379	#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /!< Rising trigger event configuration bit of line 4 /
		2380	#define EXTI_RTSR_TR5_Pos (5U)
50	mjames	2381	#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /!< 0x00000020 /
30	mjames	2382	#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /!< Rising trigger event configuration bit of line 5 /
		2383	#define EXTI_RTSR_TR6_Pos (6U)
50	mjames	2384	#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /!< 0x00000040 /
30	mjames	2385	#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /!< Rising trigger event configuration bit of line 6 /
		2386	#define EXTI_RTSR_TR7_Pos (7U)
50	mjames	2387	#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /!< 0x00000080 /
30	mjames	2388	#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /!< Rising trigger event configuration bit of line 7 /
		2389	#define EXTI_RTSR_TR8_Pos (8U)
50	mjames	2390	#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /!< 0x00000100 /
30	mjames	2391	#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /!< Rising trigger event configuration bit of line 8 /
		2392	#define EXTI_RTSR_TR9_Pos (9U)
50	mjames	2393	#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /!< 0x00000200 /
30	mjames	2394	#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /!< Rising trigger event configuration bit of line 9 /
		2395	#define EXTI_RTSR_TR10_Pos (10U)
50	mjames	2396	#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /!< 0x00000400 /
30	mjames	2397	#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /!< Rising trigger event configuration bit of line 10 /
		2398	#define EXTI_RTSR_TR11_Pos (11U)
50	mjames	2399	#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /!< 0x00000800 /
30	mjames	2400	#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /!< Rising trigger event configuration bit of line 11 /
		2401	#define EXTI_RTSR_TR12_Pos (12U)
50	mjames	2402	#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /!< 0x00001000 /
30	mjames	2403	#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /!< Rising trigger event configuration bit of line 12 /
		2404	#define EXTI_RTSR_TR13_Pos (13U)
50	mjames	2405	#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /!< 0x00002000 /
30	mjames	2406	#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /!< Rising trigger event configuration bit of line 13 /
		2407	#define EXTI_RTSR_TR14_Pos (14U)
50	mjames	2408	#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /!< 0x00004000 /
30	mjames	2409	#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /!< Rising trigger event configuration bit of line 14 /
		2410	#define EXTI_RTSR_TR15_Pos (15U)
50	mjames	2411	#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /!< 0x00008000 /
30	mjames	2412	#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /!< Rising trigger event configuration bit of line 15 /
		2413	#define EXTI_RTSR_TR16_Pos (16U)
50	mjames	2414	#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /!< 0x00010000 /
30	mjames	2415	#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /!< Rising trigger event configuration bit of line 16 /
		2416	#define EXTI_RTSR_TR17_Pos (17U)
50	mjames	2417	#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /!< 0x00020000 /
30	mjames	2418	#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /!< Rising trigger event configuration bit of line 17 /
		2419	#define EXTI_RTSR_TR18_Pos (18U)
50	mjames	2420	#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /!< 0x00040000 /
30	mjames	2421	#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /!< Rising trigger event configuration bit of line 18 /
		2422	#define EXTI_RTSR_TR19_Pos (19U)
50	mjames	2423	#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /!< 0x00080000 /
30	mjames	2424	#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /!< Rising trigger event configuration bit of line 19 /
		2425	#define EXTI_RTSR_TR20_Pos (20U)
50	mjames	2426	#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /!< 0x00100000 /
30	mjames	2427	#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /!< Rising trigger event configuration bit of line 20 /
		2428	#define EXTI_RTSR_TR21_Pos (21U)
50	mjames	2429	#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /!< 0x00200000 /
30	mjames	2430	#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /!< Rising trigger event configuration bit of line 21 /
		2431	#define EXTI_RTSR_TR22_Pos (22U)
50	mjames	2432	#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /!< 0x00400000 /
30	mjames	2433	#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /!< Rising trigger event configuration bit of line 22 /
		2434
		2435	/* References Defines */
		2436	#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
		2437	#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
		2438	#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
		2439	#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
		2440	#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
		2441	#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
		2442	#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
		2443	#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
		2444	#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
		2445	#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
		2446	#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
		2447	#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
		2448	#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
		2449	#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
		2450	#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
		2451	#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
		2452	#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
		2453	#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
		2454	#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
		2455	#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
		2456	#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
		2457	#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
		2458	#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
		2459
		2460	/**************** Bit definition for EXTI_FTSR register *****************/
		2461	#define EXTI_FTSR_TR0_Pos (0U)
50	mjames	2462	#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /!< 0x00000001 /
30	mjames	2463	#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /!< Falling trigger event configuration bit of line 0 /
		2464	#define EXTI_FTSR_TR1_Pos (1U)
50	mjames	2465	#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /!< 0x00000002 /
30	mjames	2466	#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /!< Falling trigger event configuration bit of line 1 /
		2467	#define EXTI_FTSR_TR2_Pos (2U)
50	mjames	2468	#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /!< 0x00000004 /
30	mjames	2469	#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /!< Falling trigger event configuration bit of line 2 /
		2470	#define EXTI_FTSR_TR3_Pos (3U)
50	mjames	2471	#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /!< 0x00000008 /
30	mjames	2472	#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /!< Falling trigger event configuration bit of line 3 /
		2473	#define EXTI_FTSR_TR4_Pos (4U)
50	mjames	2474	#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /!< 0x00000010 /
30	mjames	2475	#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /!< Falling trigger event configuration bit of line 4 /
		2476	#define EXTI_FTSR_TR5_Pos (5U)
50	mjames	2477	#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /!< 0x00000020 /
30	mjames	2478	#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /!< Falling trigger event configuration bit of line 5 /
		2479	#define EXTI_FTSR_TR6_Pos (6U)
50	mjames	2480	#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /!< 0x00000040 /
30	mjames	2481	#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /!< Falling trigger event configuration bit of line 6 /
		2482	#define EXTI_FTSR_TR7_Pos (7U)
50	mjames	2483	#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /!< 0x00000080 /
30	mjames	2484	#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /!< Falling trigger event configuration bit of line 7 /
		2485	#define EXTI_FTSR_TR8_Pos (8U)
50	mjames	2486	#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /!< 0x00000100 /
30	mjames	2487	#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /!< Falling trigger event configuration bit of line 8 /
		2488	#define EXTI_FTSR_TR9_Pos (9U)
50	mjames	2489	#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /!< 0x00000200 /
30	mjames	2490	#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /!< Falling trigger event configuration bit of line 9 /
		2491	#define EXTI_FTSR_TR10_Pos (10U)
50	mjames	2492	#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /!< 0x00000400 /
30	mjames	2493	#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /!< Falling trigger event configuration bit of line 10 /
		2494	#define EXTI_FTSR_TR11_Pos (11U)
50	mjames	2495	#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /!< 0x00000800 /
30	mjames	2496	#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /!< Falling trigger event configuration bit of line 11 /
		2497	#define EXTI_FTSR_TR12_Pos (12U)
50	mjames	2498	#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /!< 0x00001000 /
30	mjames	2499	#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /!< Falling trigger event configuration bit of line 12 /
		2500	#define EXTI_FTSR_TR13_Pos (13U)
50	mjames	2501	#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /!< 0x00002000 /
30	mjames	2502	#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /!< Falling trigger event configuration bit of line 13 /
		2503	#define EXTI_FTSR_TR14_Pos (14U)
50	mjames	2504	#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /!< 0x00004000 /
30	mjames	2505	#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /!< Falling trigger event configuration bit of line 14 /
		2506	#define EXTI_FTSR_TR15_Pos (15U)
50	mjames	2507	#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /!< 0x00008000 /
30	mjames	2508	#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /!< Falling trigger event configuration bit of line 15 /
		2509	#define EXTI_FTSR_TR16_Pos (16U)
50	mjames	2510	#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /!< 0x00010000 /
30	mjames	2511	#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /!< Falling trigger event configuration bit of line 16 /
		2512	#define EXTI_FTSR_TR17_Pos (17U)
50	mjames	2513	#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /!< 0x00020000 /
30	mjames	2514	#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /!< Falling trigger event configuration bit of line 17 /
		2515	#define EXTI_FTSR_TR18_Pos (18U)
50	mjames	2516	#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /!< 0x00040000 /
30	mjames	2517	#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /!< Falling trigger event configuration bit of line 18 /
		2518	#define EXTI_FTSR_TR19_Pos (19U)
50	mjames	2519	#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /!< 0x00080000 /
30	mjames	2520	#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /!< Falling trigger event configuration bit of line 19 /
		2521	#define EXTI_FTSR_TR20_Pos (20U)
50	mjames	2522	#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /!< 0x00100000 /
30	mjames	2523	#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /!< Falling trigger event configuration bit of line 20 /
		2524	#define EXTI_FTSR_TR21_Pos (21U)
50	mjames	2525	#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /!< 0x00200000 /
30	mjames	2526	#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /!< Falling trigger event configuration bit of line 21 /
		2527	#define EXTI_FTSR_TR22_Pos (22U)
50	mjames	2528	#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /!< 0x00400000 /
30	mjames	2529	#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /!< Falling trigger event configuration bit of line 22 /
		2530
		2531	/* References Defines */
		2532	#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
		2533	#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
		2534	#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
		2535	#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
		2536	#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
		2537	#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
		2538	#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
		2539	#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
		2540	#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
		2541	#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
		2542	#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
		2543	#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
		2544	#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
		2545	#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
		2546	#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
		2547	#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
		2548	#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
		2549	#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
		2550	#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
		2551	#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
		2552	#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
		2553	#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
		2554	#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
		2555
		2556	/**************** Bit definition for EXTI_SWIER register ****************/
		2557	#define EXTI_SWIER_SWIER0_Pos (0U)
50	mjames	2558	#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /!< 0x00000001 /
30	mjames	2559	#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /!< Software Interrupt on line 0 /
		2560	#define EXTI_SWIER_SWIER1_Pos (1U)
50	mjames	2561	#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /!< 0x00000002 /
30	mjames	2562	#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /!< Software Interrupt on line 1 /
		2563	#define EXTI_SWIER_SWIER2_Pos (2U)
50	mjames	2564	#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /!< 0x00000004 /
30	mjames	2565	#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /!< Software Interrupt on line 2 /
		2566	#define EXTI_SWIER_SWIER3_Pos (3U)
50	mjames	2567	#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /!< 0x00000008 /
30	mjames	2568	#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /!< Software Interrupt on line 3 /
		2569	#define EXTI_SWIER_SWIER4_Pos (4U)
50	mjames	2570	#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /!< 0x00000010 /
30	mjames	2571	#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /!< Software Interrupt on line 4 /
		2572	#define EXTI_SWIER_SWIER5_Pos (5U)
50	mjames	2573	#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /!< 0x00000020 /
30	mjames	2574	#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /!< Software Interrupt on line 5 /
		2575	#define EXTI_SWIER_SWIER6_Pos (6U)
50	mjames	2576	#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /!< 0x00000040 /
30	mjames	2577	#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /!< Software Interrupt on line 6 /
		2578	#define EXTI_SWIER_SWIER7_Pos (7U)
50	mjames	2579	#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /!< 0x00000080 /
30	mjames	2580	#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /!< Software Interrupt on line 7 /
		2581	#define EXTI_SWIER_SWIER8_Pos (8U)
50	mjames	2582	#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /!< 0x00000100 /
30	mjames	2583	#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /!< Software Interrupt on line 8 /
		2584	#define EXTI_SWIER_SWIER9_Pos (9U)
50	mjames	2585	#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /!< 0x00000200 /
30	mjames	2586	#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /!< Software Interrupt on line 9 /
		2587	#define EXTI_SWIER_SWIER10_Pos (10U)
50	mjames	2588	#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /!< 0x00000400 /
30	mjames	2589	#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /!< Software Interrupt on line 10 /
		2590	#define EXTI_SWIER_SWIER11_Pos (11U)
50	mjames	2591	#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /!< 0x00000800 /
30	mjames	2592	#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /!< Software Interrupt on line 11 /
		2593	#define EXTI_SWIER_SWIER12_Pos (12U)
50	mjames	2594	#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /!< 0x00001000 /
30	mjames	2595	#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /!< Software Interrupt on line 12 /
		2596	#define EXTI_SWIER_SWIER13_Pos (13U)
50	mjames	2597	#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /!< 0x00002000 /
30	mjames	2598	#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /!< Software Interrupt on line 13 /
		2599	#define EXTI_SWIER_SWIER14_Pos (14U)
50	mjames	2600	#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /!< 0x00004000 /
30	mjames	2601	#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /!< Software Interrupt on line 14 /
		2602	#define EXTI_SWIER_SWIER15_Pos (15U)
50	mjames	2603	#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /!< 0x00008000 /
30	mjames	2604	#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /!< Software Interrupt on line 15 /
		2605	#define EXTI_SWIER_SWIER16_Pos (16U)
50	mjames	2606	#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /!< 0x00010000 /
30	mjames	2607	#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /!< Software Interrupt on line 16 /
		2608	#define EXTI_SWIER_SWIER17_Pos (17U)
50	mjames	2609	#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /!< 0x00020000 /
30	mjames	2610	#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /!< Software Interrupt on line 17 /
		2611	#define EXTI_SWIER_SWIER18_Pos (18U)
50	mjames	2612	#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /!< 0x00040000 /
30	mjames	2613	#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /!< Software Interrupt on line 18 /
		2614	#define EXTI_SWIER_SWIER19_Pos (19U)
50	mjames	2615	#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /!< 0x00080000 /
30	mjames	2616	#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /!< Software Interrupt on line 19 /
		2617	#define EXTI_SWIER_SWIER20_Pos (20U)
50	mjames	2618	#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /!< 0x00100000 /
30	mjames	2619	#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /!< Software Interrupt on line 20 /
		2620	#define EXTI_SWIER_SWIER21_Pos (21U)
50	mjames	2621	#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /!< 0x00200000 /
30	mjames	2622	#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /!< Software Interrupt on line 21 /
		2623	#define EXTI_SWIER_SWIER22_Pos (22U)
50	mjames	2624	#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /!< 0x00400000 /
30	mjames	2625	#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /!< Software Interrupt on line 22 /
		2626
		2627	/* References Defines */
		2628	#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
		2629	#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
		2630	#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
		2631	#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
		2632	#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
		2633	#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
		2634	#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
		2635	#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
		2636	#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
		2637	#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
		2638	#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
		2639	#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
		2640	#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
		2641	#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
		2642	#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
		2643	#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
		2644	#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
		2645	#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
		2646	#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
		2647	#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
		2648	#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
		2649	#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
		2650	#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
		2651
		2652	/***************** Bit definition for EXTI_PR register ******************/
		2653	#define EXTI_PR_PR0_Pos (0U)
50	mjames	2654	#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /!< 0x00000001 /
30	mjames	2655	#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /!< Pending bit for line 0 /
		2656	#define EXTI_PR_PR1_Pos (1U)
50	mjames	2657	#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /!< 0x00000002 /
30	mjames	2658	#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /!< Pending bit for line 1 /
		2659	#define EXTI_PR_PR2_Pos (2U)
50	mjames	2660	#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /!< 0x00000004 /
30	mjames	2661	#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /!< Pending bit for line 2 /
		2662	#define EXTI_PR_PR3_Pos (3U)
50	mjames	2663	#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /!< 0x00000008 /
30	mjames	2664	#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /!< Pending bit for line 3 /
		2665	#define EXTI_PR_PR4_Pos (4U)
50	mjames	2666	#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /!< 0x00000010 /
30	mjames	2667	#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /!< Pending bit for line 4 /
		2668	#define EXTI_PR_PR5_Pos (5U)
50	mjames	2669	#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /!< 0x00000020 /
30	mjames	2670	#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /!< Pending bit for line 5 /
		2671	#define EXTI_PR_PR6_Pos (6U)
50	mjames	2672	#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /!< 0x00000040 /
30	mjames	2673	#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /!< Pending bit for line 6 /
		2674	#define EXTI_PR_PR7_Pos (7U)
50	mjames	2675	#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /!< 0x00000080 /
30	mjames	2676	#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /!< Pending bit for line 7 /
		2677	#define EXTI_PR_PR8_Pos (8U)
50	mjames	2678	#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /!< 0x00000100 /
30	mjames	2679	#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /!< Pending bit for line 8 /
		2680	#define EXTI_PR_PR9_Pos (9U)
50	mjames	2681	#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /!< 0x00000200 /
30	mjames	2682	#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /!< Pending bit for line 9 /
		2683	#define EXTI_PR_PR10_Pos (10U)
50	mjames	2684	#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /!< 0x00000400 /
30	mjames	2685	#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /!< Pending bit for line 10 /
		2686	#define EXTI_PR_PR11_Pos (11U)
50	mjames	2687	#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /!< 0x00000800 /
30	mjames	2688	#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /!< Pending bit for line 11 /
		2689	#define EXTI_PR_PR12_Pos (12U)
50	mjames	2690	#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /!< 0x00001000 /
30	mjames	2691	#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /!< Pending bit for line 12 /
		2692	#define EXTI_PR_PR13_Pos (13U)
50	mjames	2693	#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /!< 0x00002000 /
30	mjames	2694	#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /!< Pending bit for line 13 /
		2695	#define EXTI_PR_PR14_Pos (14U)
50	mjames	2696	#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /!< 0x00004000 /
30	mjames	2697	#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /!< Pending bit for line 14 /
		2698	#define EXTI_PR_PR15_Pos (15U)
50	mjames	2699	#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /!< 0x00008000 /
30	mjames	2700	#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /!< Pending bit for line 15 /
		2701	#define EXTI_PR_PR16_Pos (16U)
50	mjames	2702	#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /!< 0x00010000 /
30	mjames	2703	#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /!< Pending bit for line 16 /
		2704	#define EXTI_PR_PR17_Pos (17U)
50	mjames	2705	#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /!< 0x00020000 /
30	mjames	2706	#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /!< Pending bit for line 17 /
		2707	#define EXTI_PR_PR18_Pos (18U)
50	mjames	2708	#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /!< 0x00040000 /
30	mjames	2709	#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /!< Pending bit for line 18 /
		2710	#define EXTI_PR_PR19_Pos (19U)
50	mjames	2711	#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /!< 0x00080000 /
30	mjames	2712	#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /!< Pending bit for line 19 /
		2713	#define EXTI_PR_PR20_Pos (20U)
50	mjames	2714	#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /!< 0x00100000 /
30	mjames	2715	#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /!< Pending bit for line 20 /
		2716	#define EXTI_PR_PR21_Pos (21U)
50	mjames	2717	#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /!< 0x00200000 /
30	mjames	2718	#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /!< Pending bit for line 21 /
		2719	#define EXTI_PR_PR22_Pos (22U)
50	mjames	2720	#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /!< 0x00400000 /
30	mjames	2721	#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /!< Pending bit for line 22 /
		2722
		2723	/* References Defines */
		2724	#define EXTI_PR_PIF0 EXTI_PR_PR0
		2725	#define EXTI_PR_PIF1 EXTI_PR_PR1
		2726	#define EXTI_PR_PIF2 EXTI_PR_PR2
		2727	#define EXTI_PR_PIF3 EXTI_PR_PR3
		2728	#define EXTI_PR_PIF4 EXTI_PR_PR4
		2729	#define EXTI_PR_PIF5 EXTI_PR_PR5
		2730	#define EXTI_PR_PIF6 EXTI_PR_PR6
		2731	#define EXTI_PR_PIF7 EXTI_PR_PR7
		2732	#define EXTI_PR_PIF8 EXTI_PR_PR8
		2733	#define EXTI_PR_PIF9 EXTI_PR_PR9
		2734	#define EXTI_PR_PIF10 EXTI_PR_PR10
		2735	#define EXTI_PR_PIF11 EXTI_PR_PR11
		2736	#define EXTI_PR_PIF12 EXTI_PR_PR12
		2737	#define EXTI_PR_PIF13 EXTI_PR_PR13
		2738	#define EXTI_PR_PIF14 EXTI_PR_PR14
		2739	#define EXTI_PR_PIF15 EXTI_PR_PR15
		2740	#define EXTI_PR_PIF16 EXTI_PR_PR16
		2741	#define EXTI_PR_PIF17 EXTI_PR_PR17
		2742	#define EXTI_PR_PIF18 EXTI_PR_PR18
		2743	#define EXTI_PR_PIF19 EXTI_PR_PR19
		2744	#define EXTI_PR_PIF20 EXTI_PR_PR20
		2745	#define EXTI_PR_PIF21 EXTI_PR_PR21
		2746	#define EXTI_PR_PIF22 EXTI_PR_PR22
		2747
		2748	/******************************************************************************/
		2749	/* */
		2750	/* FLASH, DATA EEPROM and Option Bytes Registers */
		2751	/* (FLASH, DATA_EEPROM, OB) */
		2752	/* */
		2753	/******************************************************************************/
61	mjames	2754	/*
		2755	* @brief Specific device feature definitions (not present on all devices in the STM32L1 serie)
		2756	*/
		2757	#define FLASH_CUT1
30	mjames	2758
		2759	/***************** Bit definition for FLASH_ACR register ****************/
		2760	#define FLASH_ACR_LATENCY_Pos (0U)
50	mjames	2761	#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /!< 0x00000001 /
30	mjames	2762	#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /!< Latency /
		2763	#define FLASH_ACR_PRFTEN_Pos (1U)
50	mjames	2764	#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /!< 0x00000002 /
30	mjames	2765	#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /!< Prefetch Buffer Enable /
		2766	#define FLASH_ACR_ACC64_Pos (2U)
50	mjames	2767	#define FLASH_ACR_ACC64_Msk (0x1UL << FLASH_ACR_ACC64_Pos) /!< 0x00000004 /
30	mjames	2768	#define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /!< Access 64 bits /
		2769	#define FLASH_ACR_SLEEP_PD_Pos (3U)
50	mjames	2770	#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /!< 0x00000008 /
30	mjames	2771	#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /!< Flash mode during sleep mode /
		2772	#define FLASH_ACR_RUN_PD_Pos (4U)
50	mjames	2773	#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /!< 0x00000010 /
30	mjames	2774	#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /!< Flash mode during RUN mode /
		2775
		2776	/***************** Bit definition for FLASH_PECR register ****************/
		2777	#define FLASH_PECR_PELOCK_Pos (0U)
50	mjames	2778	#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /!< 0x00000001 /
30	mjames	2779	#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /!< FLASH_PECR and Flash data Lock /
		2780	#define FLASH_PECR_PRGLOCK_Pos (1U)
50	mjames	2781	#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /!< 0x00000002 /
30	mjames	2782	#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /!< Program matrix Lock /
		2783	#define FLASH_PECR_OPTLOCK_Pos (2U)
50	mjames	2784	#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /!< 0x00000004 /
30	mjames	2785	#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /!< Option byte matrix Lock /
		2786	#define FLASH_PECR_PROG_Pos (3U)
50	mjames	2787	#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /!< 0x00000008 /
30	mjames	2788	#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /!< Program matrix selection /
		2789	#define FLASH_PECR_DATA_Pos (4U)
50	mjames	2790	#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /!< 0x00000010 /
30	mjames	2791	#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /!< Data matrix selection /
		2792	#define FLASH_PECR_FTDW_Pos (8U)
50	mjames	2793	#define FLASH_PECR_FTDW_Msk (0x1UL << FLASH_PECR_FTDW_Pos) /!< 0x00000100 /
30	mjames	2794	#define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /!< Fixed Time Data write for Word/Half Word/Byte programming /
		2795	#define FLASH_PECR_ERASE_Pos (9U)
50	mjames	2796	#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /!< 0x00000200 /
30	mjames	2797	#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /!< Page erasing mode /
		2798	#define FLASH_PECR_FPRG_Pos (10U)
50	mjames	2799	#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /!< 0x00000400 /
30	mjames	2800	#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /!< Fast Page/Half Page programming mode /
		2801	#define FLASH_PECR_EOPIE_Pos (16U)
50	mjames	2802	#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /!< 0x00010000 /
30	mjames	2803	#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /!< End of programming interrupt /
		2804	#define FLASH_PECR_ERRIE_Pos (17U)
50	mjames	2805	#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /!< 0x00020000 /
30	mjames	2806	#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /!< Error interrupt /
		2807	#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
50	mjames	2808	#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /!< 0x00040000 /
30	mjames	2809	#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /!< Launch the option byte loading /
		2810
		2811	/**************** Bit definition for FLASH_PDKEYR register ****************/
		2812	#define FLASH_PDKEYR_PDKEYR_Pos (0U)
50	mjames	2813	#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /!< 0xFFFFFFFF /
30	mjames	2814	#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /!< FLASH_PEC and data matrix Key /
		2815
		2816	/**************** Bit definition for FLASH_PEKEYR register ****************/
		2817	#define FLASH_PEKEYR_PEKEYR_Pos (0U)
50	mjames	2818	#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /!< 0xFFFFFFFF /
30	mjames	2819	#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /!< FLASH_PEC and data matrix Key /
		2820
		2821	/**************** Bit definition for FLASH_PRGKEYR register ****************/
		2822	#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
50	mjames	2823	#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /!< 0xFFFFFFFF /
30	mjames	2824	#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /!< Program matrix Key /
		2825
		2826	/**************** Bit definition for FLASH_OPTKEYR register ****************/
		2827	#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
50	mjames	2828	#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /!< 0xFFFFFFFF /
30	mjames	2829	#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /!< Option bytes matrix Key /
		2830
		2831	/**************** Bit definition for FLASH_SR register *****************/
		2832	#define FLASH_SR_BSY_Pos (0U)
50	mjames	2833	#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /!< 0x00000001 /
30	mjames	2834	#define FLASH_SR_BSY FLASH_SR_BSY_Msk /!< Busy /
		2835	#define FLASH_SR_EOP_Pos (1U)
50	mjames	2836	#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /!< 0x00000002 /
30	mjames	2837	#define FLASH_SR_EOP FLASH_SR_EOP_Msk /!< End Of Programming/
		2838	#define FLASH_SR_ENDHV_Pos (2U)
50	mjames	2839	#define FLASH_SR_ENDHV_Msk (0x1UL << FLASH_SR_ENDHV_Pos) /!< 0x00000004 /
30	mjames	2840	#define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /!< End of high voltage /
		2841	#define FLASH_SR_READY_Pos (3U)
50	mjames	2842	#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /!< 0x00000008 /
30	mjames	2843	#define FLASH_SR_READY FLASH_SR_READY_Msk /!< Flash ready after low power mode /
		2844
		2845	#define FLASH_SR_WRPERR_Pos (8U)
50	mjames	2846	#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /!< 0x00000100 /
30	mjames	2847	#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /!< Write protected error /
		2848	#define FLASH_SR_PGAERR_Pos (9U)
50	mjames	2849	#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /!< 0x00000200 /
30	mjames	2850	#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /!< Programming Alignment Error /
		2851	#define FLASH_SR_SIZERR_Pos (10U)
50	mjames	2852	#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /!< 0x00000400 /
30	mjames	2853	#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /!< Size error /
		2854	#define FLASH_SR_OPTVERR_Pos (11U)
50	mjames	2855	#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /!< 0x00000800 /
30	mjames	2856	#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /!< Option validity error /
		2857
		2858	/**************** Bit definition for FLASH_OBR register *****************/
		2859	#define FLASH_OBR_RDPRT_Pos (0U)
50	mjames	2860	#define FLASH_OBR_RDPRT_Msk (0xFFUL << FLASH_OBR_RDPRT_Pos) /!< 0x000000FF /
30	mjames	2861	#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /!< Read Protection /
		2862	#define FLASH_OBR_BOR_LEV_Pos (16U)
50	mjames	2863	#define FLASH_OBR_BOR_LEV_Msk (0xFUL << FLASH_OBR_BOR_LEV_Pos) /!< 0x000F0000 /
30	mjames	2864	#define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /!< BOR_LEV[3:0] Brown Out Reset Threshold Level/
		2865	#define FLASH_OBR_USER_Pos (20U)
50	mjames	2866	#define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /!< 0x00700000 /
30	mjames	2867	#define FLASH_OBR_USER FLASH_OBR_USER_Msk /!< User Option Bytes /
		2868	#define FLASH_OBR_IWDG_SW_Pos (20U)
50	mjames	2869	#define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /!< 0x00100000 /
30	mjames	2870	#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /!< IWDG_SW /
		2871	#define FLASH_OBR_nRST_STOP_Pos (21U)
50	mjames	2872	#define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /!< 0x00200000 /
30	mjames	2873	#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /!< nRST_STOP /
		2874	#define FLASH_OBR_nRST_STDBY_Pos (22U)
50	mjames	2875	#define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /!< 0x00400000 /
30	mjames	2876	#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /!< nRST_STDBY /
		2877
		2878	/**************** Bit definition for FLASH_WRPR register ****************/
		2879	#define FLASH_WRPR1_WRP_Pos (0U)
50	mjames	2880	#define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /!< 0xFFFFFFFF /
30	mjames	2881	#define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /!< Write Protect sectors 0 to 31 /
		2882
		2883	/******************************************************************************/
		2884	/* */
		2885	/* General Purpose I/O */
		2886	/* */
		2887	/******************************************************************************/
		2888	/**************** Bits definition for GPIO_MODER register ***************/
		2889	#define GPIO_MODER_MODER0_Pos (0U)
50	mjames	2890	#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /!< 0x00000003 /
30	mjames	2891	#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
50	mjames	2892	#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /!< 0x00000001 /
		2893	#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /!< 0x00000002 /
30	mjames	2894
		2895	#define GPIO_MODER_MODER1_Pos (2U)
50	mjames	2896	#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /!< 0x0000000C /
30	mjames	2897	#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
50	mjames	2898	#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /!< 0x00000004 /
		2899	#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /!< 0x00000008 /
30	mjames	2900
		2901	#define GPIO_MODER_MODER2_Pos (4U)
50	mjames	2902	#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /!< 0x00000030 /
30	mjames	2903	#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
50	mjames	2904	#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /!< 0x00000010 /
		2905	#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /!< 0x00000020 /
30	mjames	2906
		2907	#define GPIO_MODER_MODER3_Pos (6U)
50	mjames	2908	#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /!< 0x000000C0 /
30	mjames	2909	#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
50	mjames	2910	#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /!< 0x00000040 /
		2911	#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /!< 0x00000080 /
30	mjames	2912
		2913	#define GPIO_MODER_MODER4_Pos (8U)
50	mjames	2914	#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /!< 0x00000300 /
30	mjames	2915	#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
50	mjames	2916	#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /!< 0x00000100 /
		2917	#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /!< 0x00000200 /
30	mjames	2918
		2919	#define GPIO_MODER_MODER5_Pos (10U)
50	mjames	2920	#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /!< 0x00000C00 /
30	mjames	2921	#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
50	mjames	2922	#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /!< 0x00000400 /
		2923	#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /!< 0x00000800 /
30	mjames	2924
		2925	#define GPIO_MODER_MODER6_Pos (12U)
50	mjames	2926	#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /!< 0x00003000 /
30	mjames	2927	#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
50	mjames	2928	#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /!< 0x00001000 /
		2929	#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /!< 0x00002000 /
30	mjames	2930
		2931	#define GPIO_MODER_MODER7_Pos (14U)
50	mjames	2932	#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /!< 0x0000C000 /
30	mjames	2933	#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
50	mjames	2934	#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /!< 0x00004000 /
		2935	#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /!< 0x00008000 /
30	mjames	2936
		2937	#define GPIO_MODER_MODER8_Pos (16U)
50	mjames	2938	#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /!< 0x00030000 /
30	mjames	2939	#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
50	mjames	2940	#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /!< 0x00010000 /
		2941	#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /!< 0x00020000 /
30	mjames	2942
		2943	#define GPIO_MODER_MODER9_Pos (18U)
50	mjames	2944	#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /!< 0x000C0000 /
30	mjames	2945	#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
50	mjames	2946	#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /!< 0x00040000 /
		2947	#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /!< 0x00080000 /
30	mjames	2948
		2949	#define GPIO_MODER_MODER10_Pos (20U)
50	mjames	2950	#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /!< 0x00300000 /
30	mjames	2951	#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
50	mjames	2952	#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /!< 0x00100000 /
		2953	#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /!< 0x00200000 /
30	mjames	2954
		2955	#define GPIO_MODER_MODER11_Pos (22U)
50	mjames	2956	#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /!< 0x00C00000 /
30	mjames	2957	#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
50	mjames	2958	#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /!< 0x00400000 /
		2959	#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /!< 0x00800000 /
30	mjames	2960
		2961	#define GPIO_MODER_MODER12_Pos (24U)
50	mjames	2962	#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /!< 0x03000000 /
30	mjames	2963	#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
50	mjames	2964	#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /!< 0x01000000 /
		2965	#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /!< 0x02000000 /
30	mjames	2966
		2967	#define GPIO_MODER_MODER13_Pos (26U)
50	mjames	2968	#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /!< 0x0C000000 /
30	mjames	2969	#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
50	mjames	2970	#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /!< 0x04000000 /
		2971	#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /!< 0x08000000 /
30	mjames	2972
		2973	#define GPIO_MODER_MODER14_Pos (28U)
50	mjames	2974	#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /!< 0x30000000 /
30	mjames	2975	#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
50	mjames	2976	#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /!< 0x10000000 /
		2977	#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /!< 0x20000000 /
30	mjames	2978
		2979	#define GPIO_MODER_MODER15_Pos (30U)
50	mjames	2980	#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /!< 0xC0000000 /
30	mjames	2981	#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
50	mjames	2982	#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /!< 0x40000000 /
		2983	#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /!< 0x80000000 /
30	mjames	2984
		2985	/**************** Bits definition for GPIO_OTYPER register **************/
		2986	#define GPIO_OTYPER_OT_0 (0x00000001U)
		2987	#define GPIO_OTYPER_OT_1 (0x00000002U)
		2988	#define GPIO_OTYPER_OT_2 (0x00000004U)
		2989	#define GPIO_OTYPER_OT_3 (0x00000008U)
		2990	#define GPIO_OTYPER_OT_4 (0x00000010U)
		2991	#define GPIO_OTYPER_OT_5 (0x00000020U)
		2992	#define GPIO_OTYPER_OT_6 (0x00000040U)
		2993	#define GPIO_OTYPER_OT_7 (0x00000080U)
		2994	#define GPIO_OTYPER_OT_8 (0x00000100U)
		2995	#define GPIO_OTYPER_OT_9 (0x00000200U)
		2996	#define GPIO_OTYPER_OT_10 (0x00000400U)
		2997	#define GPIO_OTYPER_OT_11 (0x00000800U)
		2998	#define GPIO_OTYPER_OT_12 (0x00001000U)
		2999	#define GPIO_OTYPER_OT_13 (0x00002000U)
		3000	#define GPIO_OTYPER_OT_14 (0x00004000U)
		3001	#define GPIO_OTYPER_OT_15 (0x00008000U)
		3002
		3003	/**************** Bits definition for GPIO_OSPEEDR register *************/
		3004	#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
50	mjames	3005	#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /!< 0x00000003 /
30	mjames	3006	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
50	mjames	3007	#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /!< 0x00000001 /
		3008	#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /!< 0x00000002 /
30	mjames	3009
		3010	#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
50	mjames	3011	#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /!< 0x0000000C /
30	mjames	3012	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
50	mjames	3013	#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /!< 0x00000004 /
		3014	#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /!< 0x00000008 /
30	mjames	3015
		3016	#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
50	mjames	3017	#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /!< 0x00000030 /
30	mjames	3018	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
50	mjames	3019	#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /!< 0x00000010 /
		3020	#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /!< 0x00000020 /
30	mjames	3021
		3022	#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
50	mjames	3023	#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /!< 0x000000C0 /
30	mjames	3024	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
50	mjames	3025	#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /!< 0x00000040 /
		3026	#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /!< 0x00000080 /
30	mjames	3027
		3028	#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
50	mjames	3029	#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /!< 0x00000300 /
30	mjames	3030	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
50	mjames	3031	#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /!< 0x00000100 /
		3032	#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /!< 0x00000200 /
30	mjames	3033
		3034	#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
50	mjames	3035	#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /!< 0x00000C00 /
30	mjames	3036	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
50	mjames	3037	#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /!< 0x00000400 /
		3038	#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /!< 0x00000800 /
30	mjames	3039
		3040	#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
50	mjames	3041	#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /!< 0x00003000 /
30	mjames	3042	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
50	mjames	3043	#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /!< 0x00001000 /
		3044	#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /!< 0x00002000 /
30	mjames	3045
		3046	#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
50	mjames	3047	#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /!< 0x0000C000 /
30	mjames	3048	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
50	mjames	3049	#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /!< 0x00004000 /
		3050	#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /!< 0x00008000 /
30	mjames	3051
		3052	#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
50	mjames	3053	#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /!< 0x00030000 /
30	mjames	3054	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
50	mjames	3055	#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /!< 0x00010000 /
		3056	#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /!< 0x00020000 /
30	mjames	3057
		3058	#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
50	mjames	3059	#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /!< 0x000C0000 /
30	mjames	3060	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
50	mjames	3061	#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /!< 0x00040000 /
		3062	#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /!< 0x00080000 /
30	mjames	3063
		3064	#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
50	mjames	3065	#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /!< 0x00300000 /
30	mjames	3066	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
50	mjames	3067	#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /!< 0x00100000 /
		3068	#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /!< 0x00200000 /
30	mjames	3069
		3070	#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
50	mjames	3071	#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /!< 0x00C00000 /
30	mjames	3072	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
50	mjames	3073	#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /!< 0x00400000 /
		3074	#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /!< 0x00800000 /
30	mjames	3075
		3076	#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
50	mjames	3077	#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /!< 0x03000000 /
30	mjames	3078	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
50	mjames	3079	#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /!< 0x01000000 /
		3080	#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /!< 0x02000000 /
30	mjames	3081
		3082	#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
50	mjames	3083	#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /!< 0x0C000000 /
30	mjames	3084	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
50	mjames	3085	#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /!< 0x04000000 /
		3086	#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /!< 0x08000000 /
30	mjames	3087
		3088	#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
50	mjames	3089	#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /!< 0x30000000 /
30	mjames	3090	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
50	mjames	3091	#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /!< 0x10000000 /
		3092	#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /!< 0x20000000 /
30	mjames	3093
		3094	#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
50	mjames	3095	#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /!< 0xC0000000 /
30	mjames	3096	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
50	mjames	3097	#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /!< 0x40000000 /
		3098	#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /!< 0x80000000 /
30	mjames	3099
		3100	/**************** Bits definition for GPIO_PUPDR register ***************/
		3101	#define GPIO_PUPDR_PUPDR0_Pos (0U)
50	mjames	3102	#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /!< 0x00000003 /
30	mjames	3103	#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
50	mjames	3104	#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /!< 0x00000001 /
		3105	#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /!< 0x00000002 /
30	mjames	3106
		3107	#define GPIO_PUPDR_PUPDR1_Pos (2U)
50	mjames	3108	#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /!< 0x0000000C /
30	mjames	3109	#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
50	mjames	3110	#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /!< 0x00000004 /
		3111	#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /!< 0x00000008 /
30	mjames	3112
		3113	#define GPIO_PUPDR_PUPDR2_Pos (4U)
50	mjames	3114	#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /!< 0x00000030 /
30	mjames	3115	#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
50	mjames	3116	#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /!< 0x00000010 /
		3117	#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /!< 0x00000020 /
30	mjames	3118
		3119	#define GPIO_PUPDR_PUPDR3_Pos (6U)
50	mjames	3120	#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /!< 0x000000C0 /
30	mjames	3121	#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
50	mjames	3122	#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /!< 0x00000040 /
		3123	#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /!< 0x00000080 /
30	mjames	3124
		3125	#define GPIO_PUPDR_PUPDR4_Pos (8U)
50	mjames	3126	#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /!< 0x00000300 /
30	mjames	3127	#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
50	mjames	3128	#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /!< 0x00000100 /
		3129	#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /!< 0x00000200 /
30	mjames	3130
		3131	#define GPIO_PUPDR_PUPDR5_Pos (10U)
50	mjames	3132	#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /!< 0x00000C00 /
30	mjames	3133	#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
50	mjames	3134	#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /!< 0x00000400 /
		3135	#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /!< 0x00000800 /
30	mjames	3136
		3137	#define GPIO_PUPDR_PUPDR6_Pos (12U)
50	mjames	3138	#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /!< 0x00003000 /
30	mjames	3139	#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
50	mjames	3140	#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /!< 0x00001000 /
		3141	#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /!< 0x00002000 /
30	mjames	3142
		3143	#define GPIO_PUPDR_PUPDR7_Pos (14U)
50	mjames	3144	#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /!< 0x0000C000 /
30	mjames	3145	#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
50	mjames	3146	#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /!< 0x00004000 /
		3147	#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /!< 0x00008000 /
30	mjames	3148
		3149	#define GPIO_PUPDR_PUPDR8_Pos (16U)
50	mjames	3150	#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /!< 0x00030000 /
30	mjames	3151	#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
50	mjames	3152	#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /!< 0x00010000 /
		3153	#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /!< 0x00020000 /
30	mjames	3154
		3155	#define GPIO_PUPDR_PUPDR9_Pos (18U)
50	mjames	3156	#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /!< 0x000C0000 /
30	mjames	3157	#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
50	mjames	3158	#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /!< 0x00040000 /
		3159	#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /!< 0x00080000 /
30	mjames	3160
		3161	#define GPIO_PUPDR_PUPDR10_Pos (20U)
50	mjames	3162	#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /!< 0x00300000 /
30	mjames	3163	#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
50	mjames	3164	#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /!< 0x00100000 /
		3165	#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /!< 0x00200000 /
30	mjames	3166
		3167	#define GPIO_PUPDR_PUPDR11_Pos (22U)
50	mjames	3168	#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /!< 0x00C00000 /
30	mjames	3169	#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
50	mjames	3170	#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /!< 0x00400000 /
		3171	#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /!< 0x00800000 /
30	mjames	3172
		3173	#define GPIO_PUPDR_PUPDR12_Pos (24U)
50	mjames	3174	#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /!< 0x03000000 /
30	mjames	3175	#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
50	mjames	3176	#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /!< 0x01000000 /
		3177	#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /!< 0x02000000 /
30	mjames	3178
		3179	#define GPIO_PUPDR_PUPDR13_Pos (26U)
50	mjames	3180	#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /!< 0x0C000000 /
30	mjames	3181	#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
50	mjames	3182	#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /!< 0x04000000 /
		3183	#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /!< 0x08000000 /
30	mjames	3184
		3185	#define GPIO_PUPDR_PUPDR14_Pos (28U)
50	mjames	3186	#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /!< 0x30000000 /
30	mjames	3187	#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
50	mjames	3188	#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /!< 0x10000000 /
		3189	#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /!< 0x20000000 /
30	mjames	3190	#define GPIO_PUPDR_PUPDR15_Pos (30U)
50	mjames	3191	#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /!< 0xC0000000 /
30	mjames	3192	#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
50	mjames	3193	#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /!< 0x40000000 /
		3194	#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /!< 0x80000000 /
30	mjames	3195
		3196	/**************** Bits definition for GPIO_IDR register *****************/
		3197	#define GPIO_IDR_IDR_0 (0x00000001U)
		3198	#define GPIO_IDR_IDR_1 (0x00000002U)
		3199	#define GPIO_IDR_IDR_2 (0x00000004U)
		3200	#define GPIO_IDR_IDR_3 (0x00000008U)
		3201	#define GPIO_IDR_IDR_4 (0x00000010U)
		3202	#define GPIO_IDR_IDR_5 (0x00000020U)
		3203	#define GPIO_IDR_IDR_6 (0x00000040U)
		3204	#define GPIO_IDR_IDR_7 (0x00000080U)
		3205	#define GPIO_IDR_IDR_8 (0x00000100U)
		3206	#define GPIO_IDR_IDR_9 (0x00000200U)
		3207	#define GPIO_IDR_IDR_10 (0x00000400U)
		3208	#define GPIO_IDR_IDR_11 (0x00000800U)
		3209	#define GPIO_IDR_IDR_12 (0x00001000U)
		3210	#define GPIO_IDR_IDR_13 (0x00002000U)
		3211	#define GPIO_IDR_IDR_14 (0x00004000U)
		3212	#define GPIO_IDR_IDR_15 (0x00008000U)
		3213
		3214	/**************** Bits definition for GPIO_ODR register *****************/
		3215	#define GPIO_ODR_ODR_0 (0x00000001U)
		3216	#define GPIO_ODR_ODR_1 (0x00000002U)
		3217	#define GPIO_ODR_ODR_2 (0x00000004U)
		3218	#define GPIO_ODR_ODR_3 (0x00000008U)
		3219	#define GPIO_ODR_ODR_4 (0x00000010U)
		3220	#define GPIO_ODR_ODR_5 (0x00000020U)
		3221	#define GPIO_ODR_ODR_6 (0x00000040U)
		3222	#define GPIO_ODR_ODR_7 (0x00000080U)
		3223	#define GPIO_ODR_ODR_8 (0x00000100U)
		3224	#define GPIO_ODR_ODR_9 (0x00000200U)
		3225	#define GPIO_ODR_ODR_10 (0x00000400U)
		3226	#define GPIO_ODR_ODR_11 (0x00000800U)
		3227	#define GPIO_ODR_ODR_12 (0x00001000U)
		3228	#define GPIO_ODR_ODR_13 (0x00002000U)
		3229	#define GPIO_ODR_ODR_14 (0x00004000U)
		3230	#define GPIO_ODR_ODR_15 (0x00008000U)
		3231
		3232	/**************** Bits definition for GPIO_BSRR register ****************/
		3233	#define GPIO_BSRR_BS_0 (0x00000001U)
		3234	#define GPIO_BSRR_BS_1 (0x00000002U)
		3235	#define GPIO_BSRR_BS_2 (0x00000004U)
		3236	#define GPIO_BSRR_BS_3 (0x00000008U)
		3237	#define GPIO_BSRR_BS_4 (0x00000010U)
		3238	#define GPIO_BSRR_BS_5 (0x00000020U)
		3239	#define GPIO_BSRR_BS_6 (0x00000040U)
		3240	#define GPIO_BSRR_BS_7 (0x00000080U)
		3241	#define GPIO_BSRR_BS_8 (0x00000100U)
		3242	#define GPIO_BSRR_BS_9 (0x00000200U)
		3243	#define GPIO_BSRR_BS_10 (0x00000400U)
		3244	#define GPIO_BSRR_BS_11 (0x00000800U)
		3245	#define GPIO_BSRR_BS_12 (0x00001000U)
		3246	#define GPIO_BSRR_BS_13 (0x00002000U)
		3247	#define GPIO_BSRR_BS_14 (0x00004000U)
		3248	#define GPIO_BSRR_BS_15 (0x00008000U)
		3249	#define GPIO_BSRR_BR_0 (0x00010000U)
		3250	#define GPIO_BSRR_BR_1 (0x00020000U)
		3251	#define GPIO_BSRR_BR_2 (0x00040000U)
		3252	#define GPIO_BSRR_BR_3 (0x00080000U)
		3253	#define GPIO_BSRR_BR_4 (0x00100000U)
		3254	#define GPIO_BSRR_BR_5 (0x00200000U)
		3255	#define GPIO_BSRR_BR_6 (0x00400000U)
		3256	#define GPIO_BSRR_BR_7 (0x00800000U)
		3257	#define GPIO_BSRR_BR_8 (0x01000000U)
		3258	#define GPIO_BSRR_BR_9 (0x02000000U)
		3259	#define GPIO_BSRR_BR_10 (0x04000000U)
		3260	#define GPIO_BSRR_BR_11 (0x08000000U)
		3261	#define GPIO_BSRR_BR_12 (0x10000000U)
		3262	#define GPIO_BSRR_BR_13 (0x20000000U)
		3263	#define GPIO_BSRR_BR_14 (0x40000000U)
		3264	#define GPIO_BSRR_BR_15 (0x80000000U)
		3265
		3266	/**************** Bit definition for GPIO_LCKR register ******************/
		3267	#define GPIO_LCKR_LCK0_Pos (0U)
50	mjames	3268	#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /!< 0x00000001 /
30	mjames	3269	#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
		3270	#define GPIO_LCKR_LCK1_Pos (1U)
50	mjames	3271	#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /!< 0x00000002 /
30	mjames	3272	#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
		3273	#define GPIO_LCKR_LCK2_Pos (2U)
50	mjames	3274	#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /!< 0x00000004 /
30	mjames	3275	#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
		3276	#define GPIO_LCKR_LCK3_Pos (3U)
50	mjames	3277	#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /!< 0x00000008 /
30	mjames	3278	#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
		3279	#define GPIO_LCKR_LCK4_Pos (4U)
50	mjames	3280	#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /!< 0x00000010 /
30	mjames	3281	#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
		3282	#define GPIO_LCKR_LCK5_Pos (5U)
50	mjames	3283	#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /!< 0x00000020 /
30	mjames	3284	#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
		3285	#define GPIO_LCKR_LCK6_Pos (6U)
50	mjames	3286	#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /!< 0x00000040 /
30	mjames	3287	#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
		3288	#define GPIO_LCKR_LCK7_Pos (7U)
50	mjames	3289	#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /!< 0x00000080 /
30	mjames	3290	#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
		3291	#define GPIO_LCKR_LCK8_Pos (8U)
50	mjames	3292	#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /!< 0x00000100 /
30	mjames	3293	#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
		3294	#define GPIO_LCKR_LCK9_Pos (9U)
50	mjames	3295	#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /!< 0x00000200 /
30	mjames	3296	#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
		3297	#define GPIO_LCKR_LCK10_Pos (10U)
50	mjames	3298	#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /!< 0x00000400 /
30	mjames	3299	#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
		3300	#define GPIO_LCKR_LCK11_Pos (11U)
50	mjames	3301	#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /!< 0x00000800 /
30	mjames	3302	#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
		3303	#define GPIO_LCKR_LCK12_Pos (12U)
50	mjames	3304	#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /!< 0x00001000 /
30	mjames	3305	#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
		3306	#define GPIO_LCKR_LCK13_Pos (13U)
50	mjames	3307	#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /!< 0x00002000 /
30	mjames	3308	#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
		3309	#define GPIO_LCKR_LCK14_Pos (14U)
50	mjames	3310	#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /!< 0x00004000 /
30	mjames	3311	#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
		3312	#define GPIO_LCKR_LCK15_Pos (15U)
50	mjames	3313	#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /!< 0x00008000 /
30	mjames	3314	#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
		3315	#define GPIO_LCKR_LCKK_Pos (16U)
50	mjames	3316	#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /!< 0x00010000 /
30	mjames	3317	#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
		3318
		3319	/**************** Bit definition for GPIO_AFRL register ******************/
50	mjames	3320	#define GPIO_AFRL_AFSEL0_Pos (0U)
		3321	#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /!< 0x0000000F /
		3322	#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
		3323	#define GPIO_AFRL_AFSEL1_Pos (4U)
		3324	#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /!< 0x000000F0 /
		3325	#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
		3326	#define GPIO_AFRL_AFSEL2_Pos (8U)
		3327	#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /!< 0x00000F00 /
		3328	#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
		3329	#define GPIO_AFRL_AFSEL3_Pos (12U)
		3330	#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /!< 0x0000F000 /
		3331	#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
		3332	#define GPIO_AFRL_AFSEL4_Pos (16U)
		3333	#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /!< 0x000F0000 /
		3334	#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
		3335	#define GPIO_AFRL_AFSEL5_Pos (20U)
		3336	#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /!< 0x00F00000 /
		3337	#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
		3338	#define GPIO_AFRL_AFSEL6_Pos (24U)
		3339	#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /!< 0x0F000000 /
		3340	#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
		3341	#define GPIO_AFRL_AFSEL7_Pos (28U)
		3342	#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /!< 0xF0000000 /
		3343	#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
30	mjames	3344
		3345	/**************** Bit definition for GPIO_AFRH register ******************/
50	mjames	3346	#define GPIO_AFRH_AFSEL8_Pos (0U)
		3347	#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /!< 0x0000000F /
		3348	#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
		3349	#define GPIO_AFRH_AFSEL9_Pos (4U)
		3350	#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /!< 0x000000F0 /
		3351	#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
		3352	#define GPIO_AFRH_AFSEL10_Pos (8U)
		3353	#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /!< 0x00000F00 /
		3354	#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
		3355	#define GPIO_AFRH_AFSEL11_Pos (12U)
		3356	#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /!< 0x0000F000 /
		3357	#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
		3358	#define GPIO_AFRH_AFSEL12_Pos (16U)
		3359	#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /!< 0x000F0000 /
		3360	#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
		3361	#define GPIO_AFRH_AFSEL13_Pos (20U)
		3362	#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /!< 0x00F00000 /
		3363	#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
		3364	#define GPIO_AFRH_AFSEL14_Pos (24U)
		3365	#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /!< 0x0F000000 /
		3366	#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
		3367	#define GPIO_AFRH_AFSEL15_Pos (28U)
		3368	#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /!< 0xF0000000 /
		3369	#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
30	mjames	3370
		3371	/******************************************************************************/
		3372	/* */
		3373	/* Inter-integrated Circuit Interface (I2C) */
		3374	/* */
		3375	/******************************************************************************/
		3376
		3377	/***************** Bit definition for I2C_CR1 register ******************/
		3378	#define I2C_CR1_PE_Pos (0U)
50	mjames	3379	#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /!< 0x00000001 /
30	mjames	3380	#define I2C_CR1_PE I2C_CR1_PE_Msk /!< Peripheral Enable /
		3381	#define I2C_CR1_SMBUS_Pos (1U)
50	mjames	3382	#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /!< 0x00000002 /
30	mjames	3383	#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /!< SMBus Mode /
		3384	#define I2C_CR1_SMBTYPE_Pos (3U)
50	mjames	3385	#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /!< 0x00000008 /
30	mjames	3386	#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /!< SMBus Type /
		3387	#define I2C_CR1_ENARP_Pos (4U)
50	mjames	3388	#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /!< 0x00000010 /
30	mjames	3389	#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /!< ARP Enable /
		3390	#define I2C_CR1_ENPEC_Pos (5U)
50	mjames	3391	#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /!< 0x00000020 /
30	mjames	3392	#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /!< PEC Enable /
		3393	#define I2C_CR1_ENGC_Pos (6U)
50	mjames	3394	#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /!< 0x00000040 /
30	mjames	3395	#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /!< General Call Enable /
		3396	#define I2C_CR1_NOSTRETCH_Pos (7U)
50	mjames	3397	#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /!< 0x00000080 /
30	mjames	3398	#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /!< Clock Stretching Disable (Slave mode) /
		3399	#define I2C_CR1_START_Pos (8U)
50	mjames	3400	#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /!< 0x00000100 /
30	mjames	3401	#define I2C_CR1_START I2C_CR1_START_Msk /!< Start Generation /
		3402	#define I2C_CR1_STOP_Pos (9U)
50	mjames	3403	#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /!< 0x00000200 /
30	mjames	3404	#define I2C_CR1_STOP I2C_CR1_STOP_Msk /!< Stop Generation /
		3405	#define I2C_CR1_ACK_Pos (10U)
50	mjames	3406	#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /!< 0x00000400 /
30	mjames	3407	#define I2C_CR1_ACK I2C_CR1_ACK_Msk /!< Acknowledge Enable /
		3408	#define I2C_CR1_POS_Pos (11U)
50	mjames	3409	#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /!< 0x00000800 /
30	mjames	3410	#define I2C_CR1_POS I2C_CR1_POS_Msk /!< Acknowledge/PEC Position (for data reception) /
		3411	#define I2C_CR1_PEC_Pos (12U)
50	mjames	3412	#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /!< 0x00001000 /
30	mjames	3413	#define I2C_CR1_PEC I2C_CR1_PEC_Msk /!< Packet Error Checking /
		3414	#define I2C_CR1_ALERT_Pos (13U)
50	mjames	3415	#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /!< 0x00002000 /
30	mjames	3416	#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /!< SMBus Alert /
		3417	#define I2C_CR1_SWRST_Pos (15U)
50	mjames	3418	#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /!< 0x00008000 /
30	mjames	3419	#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /!< Software Reset /
		3420
		3421	/***************** Bit definition for I2C_CR2 register ******************/
		3422	#define I2C_CR2_FREQ_Pos (0U)
50	mjames	3423	#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /!< 0x0000003F /
30	mjames	3424	#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
50	mjames	3425	#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /!< 0x00000001 /
		3426	#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /!< 0x00000002 /
		3427	#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /!< 0x00000004 /
		3428	#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /!< 0x00000008 /
		3429	#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /!< 0x00000010 /
		3430	#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /!< 0x00000020 /
30	mjames	3431
		3432	#define I2C_CR2_ITERREN_Pos (8U)
50	mjames	3433	#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /!< 0x00000100 /
30	mjames	3434	#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /!< Error Interrupt Enable /
		3435	#define I2C_CR2_ITEVTEN_Pos (9U)
50	mjames	3436	#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /!< 0x00000200 /
30	mjames	3437	#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /!< Event Interrupt Enable /
		3438	#define I2C_CR2_ITBUFEN_Pos (10U)
50	mjames	3439	#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /!< 0x00000400 /
30	mjames	3440	#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /!< Buffer Interrupt Enable /
		3441	#define I2C_CR2_DMAEN_Pos (11U)
50	mjames	3442	#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /!< 0x00000800 /
30	mjames	3443	#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /!< DMA Requests Enable /
		3444	#define I2C_CR2_LAST_Pos (12U)
50	mjames	3445	#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /!< 0x00001000 /
30	mjames	3446	#define I2C_CR2_LAST I2C_CR2_LAST_Msk /!< DMA Last Transfer /
		3447
		3448	/***************** Bit definition for I2C_OAR1 register *****************/
		3449	#define I2C_OAR1_ADD1_7 (0x000000FEU) /!< Interface Address /
		3450	#define I2C_OAR1_ADD8_9 (0x00000300U) /!< Interface Address /
		3451
		3452	#define I2C_OAR1_ADD0_Pos (0U)
50	mjames	3453	#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /!< 0x00000001 /
30	mjames	3454	#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /!< Bit 0 /
		3455	#define I2C_OAR1_ADD1_Pos (1U)
50	mjames	3456	#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /!< 0x00000002 /
30	mjames	3457	#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /!< Bit 1 /
		3458	#define I2C_OAR1_ADD2_Pos (2U)
50	mjames	3459	#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /!< 0x00000004 /
30	mjames	3460	#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /!< Bit 2 /
		3461	#define I2C_OAR1_ADD3_Pos (3U)
50	mjames	3462	#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /!< 0x00000008 /
30	mjames	3463	#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /!< Bit 3 /
		3464	#define I2C_OAR1_ADD4_Pos (4U)
50	mjames	3465	#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /!< 0x00000010 /
30	mjames	3466	#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /!< Bit 4 /
		3467	#define I2C_OAR1_ADD5_Pos (5U)
50	mjames	3468	#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /!< 0x00000020 /
30	mjames	3469	#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /!< Bit 5 /
		3470	#define I2C_OAR1_ADD6_Pos (6U)
50	mjames	3471	#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /!< 0x00000040 /
30	mjames	3472	#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /!< Bit 6 /
		3473	#define I2C_OAR1_ADD7_Pos (7U)
50	mjames	3474	#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /!< 0x00000080 /
30	mjames	3475	#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /!< Bit 7 /
		3476	#define I2C_OAR1_ADD8_Pos (8U)
50	mjames	3477	#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /!< 0x00000100 /
30	mjames	3478	#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /!< Bit 8 /
		3479	#define I2C_OAR1_ADD9_Pos (9U)
50	mjames	3480	#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /!< 0x00000200 /
30	mjames	3481	#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /!< Bit 9 /
		3482
		3483	#define I2C_OAR1_ADDMODE_Pos (15U)
50	mjames	3484	#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /!< 0x00008000 /
30	mjames	3485	#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /!< Addressing Mode (Slave mode) /
		3486
		3487	/***************** Bit definition for I2C_OAR2 register *****************/
		3488	#define I2C_OAR2_ENDUAL_Pos (0U)
50	mjames	3489	#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /!< 0x00000001 /
30	mjames	3490	#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /!< Dual addressing mode enable /
		3491	#define I2C_OAR2_ADD2_Pos (1U)
50	mjames	3492	#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /!< 0x000000FE /
30	mjames	3493	#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /!< Interface address /
		3494
		3495	/****************** Bit definition for I2C_DR register ******************/
		3496	#define I2C_DR_DR_Pos (0U)
50	mjames	3497	#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /!< 0x000000FF /
30	mjames	3498	#define I2C_DR_DR I2C_DR_DR_Msk /!< 8-bit Data Register /
		3499
		3500	/***************** Bit definition for I2C_SR1 register ******************/
		3501	#define I2C_SR1_SB_Pos (0U)
50	mjames	3502	#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /!< 0x00000001 /
30	mjames	3503	#define I2C_SR1_SB I2C_SR1_SB_Msk /!< Start Bit (Master mode) /
		3504	#define I2C_SR1_ADDR_Pos (1U)
50	mjames	3505	#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /!< 0x00000002 /
30	mjames	3506	#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /!< Address sent (master mode)/matched (slave mode) /
		3507	#define I2C_SR1_BTF_Pos (2U)
50	mjames	3508	#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /!< 0x00000004 /
30	mjames	3509	#define I2C_SR1_BTF I2C_SR1_BTF_Msk /!< Byte Transfer Finished /
		3510	#define I2C_SR1_ADD10_Pos (3U)
50	mjames	3511	#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /!< 0x00000008 /
30	mjames	3512	#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /!< 10-bit header sent (Master mode) /
		3513	#define I2C_SR1_STOPF_Pos (4U)
50	mjames	3514	#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /!< 0x00000010 /
30	mjames	3515	#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /!< Stop detection (Slave mode) /
		3516	#define I2C_SR1_RXNE_Pos (6U)
50	mjames	3517	#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /!< 0x00000040 /
30	mjames	3518	#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /!< Data Register not Empty (receivers) /
		3519	#define I2C_SR1_TXE_Pos (7U)
50	mjames	3520	#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /!< 0x00000080 /
30	mjames	3521	#define I2C_SR1_TXE I2C_SR1_TXE_Msk /!< Data Register Empty (transmitters) /
		3522	#define I2C_SR1_BERR_Pos (8U)
50	mjames	3523	#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /!< 0x00000100 /
30	mjames	3524	#define I2C_SR1_BERR I2C_SR1_BERR_Msk /!< Bus Error /
		3525	#define I2C_SR1_ARLO_Pos (9U)
50	mjames	3526	#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /!< 0x00000200 /
30	mjames	3527	#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /!< Arbitration Lost (master mode) /
		3528	#define I2C_SR1_AF_Pos (10U)
50	mjames	3529	#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /!< 0x00000400 /
30	mjames	3530	#define I2C_SR1_AF I2C_SR1_AF_Msk /!< Acknowledge Failure /
		3531	#define I2C_SR1_OVR_Pos (11U)
50	mjames	3532	#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /!< 0x00000800 /
30	mjames	3533	#define I2C_SR1_OVR I2C_SR1_OVR_Msk /!< Overrun/Underrun /
		3534	#define I2C_SR1_PECERR_Pos (12U)
50	mjames	3535	#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /!< 0x00001000 /
30	mjames	3536	#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /!< PEC Error in reception /
		3537	#define I2C_SR1_TIMEOUT_Pos (14U)
50	mjames	3538	#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /!< 0x00004000 /
30	mjames	3539	#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /!< Timeout or Tlow Error /
		3540	#define I2C_SR1_SMBALERT_Pos (15U)
50	mjames	3541	#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /!< 0x00008000 /
30	mjames	3542	#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /!< SMBus Alert /
		3543
		3544	/***************** Bit definition for I2C_SR2 register ******************/
		3545	#define I2C_SR2_MSL_Pos (0U)
50	mjames	3546	#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /!< 0x00000001 /
30	mjames	3547	#define I2C_SR2_MSL I2C_SR2_MSL_Msk /!< Master/Slave /
		3548	#define I2C_SR2_BUSY_Pos (1U)
50	mjames	3549	#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /!< 0x00000002 /
30	mjames	3550	#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /!< Bus Busy /
		3551	#define I2C_SR2_TRA_Pos (2U)
50	mjames	3552	#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /!< 0x00000004 /
30	mjames	3553	#define I2C_SR2_TRA I2C_SR2_TRA_Msk /!< Transmitter/Receiver /
		3554	#define I2C_SR2_GENCALL_Pos (4U)
50	mjames	3555	#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /!< 0x00000010 /
30	mjames	3556	#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /!< General Call Address (Slave mode) /
		3557	#define I2C_SR2_SMBDEFAULT_Pos (5U)
50	mjames	3558	#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /!< 0x00000020 /
30	mjames	3559	#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /!< SMBus Device Default Address (Slave mode) /
		3560	#define I2C_SR2_SMBHOST_Pos (6U)
50	mjames	3561	#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /!< 0x00000040 /
30	mjames	3562	#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /!< SMBus Host Header (Slave mode) /
		3563	#define I2C_SR2_DUALF_Pos (7U)
50	mjames	3564	#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /!< 0x00000080 /
30	mjames	3565	#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /!< Dual Flag (Slave mode) /
		3566	#define I2C_SR2_PEC_Pos (8U)
50	mjames	3567	#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /!< 0x0000FF00 /
30	mjames	3568	#define I2C_SR2_PEC I2C_SR2_PEC_Msk /!< Packet Error Checking Register /
		3569
		3570	/***************** Bit definition for I2C_CCR register ******************/
		3571	#define I2C_CCR_CCR_Pos (0U)
50	mjames	3572	#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /!< 0x00000FFF /
30	mjames	3573	#define I2C_CCR_CCR I2C_CCR_CCR_Msk /!< Clock Control Register in Fast/Standard mode (Master mode) /
		3574	#define I2C_CCR_DUTY_Pos (14U)
50	mjames	3575	#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /!< 0x00004000 /
30	mjames	3576	#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /!< Fast Mode Duty Cycle /
		3577	#define I2C_CCR_FS_Pos (15U)
50	mjames	3578	#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /!< 0x00008000 /
30	mjames	3579	#define I2C_CCR_FS I2C_CCR_FS_Msk /!< I2C Master Mode Selection /
		3580
		3581	/**************** Bit definition for I2C_TRISE register *****************/
		3582	#define I2C_TRISE_TRISE_Pos (0U)
50	mjames	3583	#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /!< 0x0000003F /
30	mjames	3584	#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
		3585
		3586	/******************************************************************************/
		3587	/* */
		3588	/* Independent WATCHDOG (IWDG) */
		3589	/* */
		3590	/******************************************************************************/
		3591
		3592	/***************** Bit definition for IWDG_KR register ******************/
		3593	#define IWDG_KR_KEY_Pos (0U)
50	mjames	3594	#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /!< 0x0000FFFF /
30	mjames	3595	#define IWDG_KR_KEY IWDG_KR_KEY_Msk /!< Key value (write only, read 0000h) /
		3596
		3597	/***************** Bit definition for IWDG_PR register ******************/
		3598	#define IWDG_PR_PR_Pos (0U)
50	mjames	3599	#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /!< 0x00000007 /
30	mjames	3600	#define IWDG_PR_PR IWDG_PR_PR_Msk /!< PR[2:0] (Prescaler divider) /
50	mjames	3601	#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /!< 0x00000001 /
		3602	#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /!< 0x00000002 /
		3603	#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /!< 0x00000004 /
30	mjames	3604
		3605	/***************** Bit definition for IWDG_RLR register *****************/
		3606	#define IWDG_RLR_RL_Pos (0U)
50	mjames	3607	#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /!< 0x00000FFF /
30	mjames	3608	#define IWDG_RLR_RL IWDG_RLR_RL_Msk /!< Watchdog counter reload value /
		3609
		3610	/***************** Bit definition for IWDG_SR register ******************/
		3611	#define IWDG_SR_PVU_Pos (0U)
50	mjames	3612	#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /!< 0x00000001 /
30	mjames	3613	#define IWDG_SR_PVU IWDG_SR_PVU_Msk /!< Watchdog prescaler value update /
		3614	#define IWDG_SR_RVU_Pos (1U)
50	mjames	3615	#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /!< 0x00000002 /
30	mjames	3616	#define IWDG_SR_RVU IWDG_SR_RVU_Msk /!< Watchdog counter reload value update /
		3617
		3618	/******************************************************************************/
		3619	/* */
		3620	/* Power Control (PWR) */
		3621	/* */
		3622	/******************************************************************************/
		3623
		3624	#define PWR_PVD_SUPPORT /!< PWR feature available only on specific devices: Power Voltage Detection feature /
		3625
		3626	/****************** Bit definition for PWR_CR register ******************/
		3627	#define PWR_CR_LPSDSR_Pos (0U)
50	mjames	3628	#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /!< 0x00000001 /
30	mjames	3629	#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /!< Low-power deepsleep/sleep/low power run /
		3630	#define PWR_CR_PDDS_Pos (1U)
50	mjames	3631	#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /!< 0x00000002 /
30	mjames	3632	#define PWR_CR_PDDS PWR_CR_PDDS_Msk /!< Power Down Deepsleep /
		3633	#define PWR_CR_CWUF_Pos (2U)
50	mjames	3634	#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /!< 0x00000004 /
30	mjames	3635	#define PWR_CR_CWUF PWR_CR_CWUF_Msk /!< Clear Wakeup Flag /
		3636	#define PWR_CR_CSBF_Pos (3U)
50	mjames	3637	#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /!< 0x00000008 /
30	mjames	3638	#define PWR_CR_CSBF PWR_CR_CSBF_Msk /!< Clear Standby Flag /
		3639	#define PWR_CR_PVDE_Pos (4U)
50	mjames	3640	#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /!< 0x00000010 /
30	mjames	3641	#define PWR_CR_PVDE PWR_CR_PVDE_Msk /!< Power Voltage Detector Enable /
		3642
		3643	#define PWR_CR_PLS_Pos (5U)
50	mjames	3644	#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /!< 0x000000E0 /
30	mjames	3645	#define PWR_CR_PLS PWR_CR_PLS_Msk /!< PLS[2:0] bits (PVD Level Selection) /
50	mjames	3646	#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /!< 0x00000020 /
		3647	#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /!< 0x00000040 /
		3648	#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /!< 0x00000080 /
30	mjames	3649
		3650	/!< PVD level configuration /
		3651	#define PWR_CR_PLS_LEV0 (0x00000000U) /!< PVD level 0 /
		3652	#define PWR_CR_PLS_LEV1 (0x00000020U) /!< PVD level 1 /
		3653	#define PWR_CR_PLS_LEV2 (0x00000040U) /!< PVD level 2 /
		3654	#define PWR_CR_PLS_LEV3 (0x00000060U) /!< PVD level 3 /
		3655	#define PWR_CR_PLS_LEV4 (0x00000080U) /!< PVD level 4 /
		3656	#define PWR_CR_PLS_LEV5 (0x000000A0U) /!< PVD level 5 /
		3657	#define PWR_CR_PLS_LEV6 (0x000000C0U) /!< PVD level 6 /
		3658	#define PWR_CR_PLS_LEV7 (0x000000E0U) /!< PVD level 7 /
		3659
		3660	#define PWR_CR_DBP_Pos (8U)
50	mjames	3661	#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /!< 0x00000100 /
30	mjames	3662	#define PWR_CR_DBP PWR_CR_DBP_Msk /!< Disable Backup Domain write protection /
		3663	#define PWR_CR_ULP_Pos (9U)
50	mjames	3664	#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /!< 0x00000200 /
30	mjames	3665	#define PWR_CR_ULP PWR_CR_ULP_Msk /!< Ultra Low Power mode /
		3666	#define PWR_CR_FWU_Pos (10U)
50	mjames	3667	#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /!< 0x00000400 /
30	mjames	3668	#define PWR_CR_FWU PWR_CR_FWU_Msk /!< Fast wakeup /
		3669
		3670	#define PWR_CR_VOS_Pos (11U)
50	mjames	3671	#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /!< 0x00001800 /
30	mjames	3672	#define PWR_CR_VOS PWR_CR_VOS_Msk /!< VOS[1:0] bits (Voltage scaling range selection) /
50	mjames	3673	#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /!< 0x00000800 /
		3674	#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /!< 0x00001000 /
30	mjames	3675	#define PWR_CR_LPRUN_Pos (14U)
50	mjames	3676	#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /!< 0x00004000 /
30	mjames	3677	#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /!< Low power run mode /
		3678
		3679	/***************** Bit definition for PWR_CSR register ******************/
		3680	#define PWR_CSR_WUF_Pos (0U)
50	mjames	3681	#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /!< 0x00000001 /
30	mjames	3682	#define PWR_CSR_WUF PWR_CSR_WUF_Msk /!< Wakeup Flag /
		3683	#define PWR_CSR_SBF_Pos (1U)
50	mjames	3684	#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /!< 0x00000002 /
30	mjames	3685	#define PWR_CSR_SBF PWR_CSR_SBF_Msk /!< Standby Flag /
		3686	#define PWR_CSR_PVDO_Pos (2U)
50	mjames	3687	#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /!< 0x00000004 /
30	mjames	3688	#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /!< PVD Output /
		3689	#define PWR_CSR_VREFINTRDYF_Pos (3U)
50	mjames	3690	#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /!< 0x00000008 /
30	mjames	3691	#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /!< Internal voltage reference (VREFINT) ready flag /
		3692	#define PWR_CSR_VOSF_Pos (4U)
50	mjames	3693	#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /!< 0x00000010 /
30	mjames	3694	#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /!< Voltage Scaling select flag /
		3695	#define PWR_CSR_REGLPF_Pos (5U)
50	mjames	3696	#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /!< 0x00000020 /
30	mjames	3697	#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /!< Regulator LP flag /
		3698
		3699	#define PWR_CSR_EWUP1_Pos (8U)
50	mjames	3700	#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /!< 0x00000100 /
30	mjames	3701	#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /!< Enable WKUP pin 1 /
		3702	#define PWR_CSR_EWUP2_Pos (9U)
50	mjames	3703	#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /!< 0x00000200 /
30	mjames	3704	#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /!< Enable WKUP pin 2 /
		3705	#define PWR_CSR_EWUP3_Pos (10U)
50	mjames	3706	#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /!< 0x00000400 /
30	mjames	3707	#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /!< Enable WKUP pin 3 /
		3708
		3709	/******************************************************************************/
		3710	/* */
		3711	/* Reset and Clock Control (RCC) */
		3712	/* */
		3713	/******************************************************************************/
		3714	/****************** Bit definition for RCC_CR register ******************/
		3715	#define RCC_CR_HSION_Pos (0U)
50	mjames	3716	#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /!< 0x00000001 /
30	mjames	3717	#define RCC_CR_HSION RCC_CR_HSION_Msk /!< Internal High Speed clock enable /
		3718	#define RCC_CR_HSIRDY_Pos (1U)
50	mjames	3719	#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /!< 0x00000002 /
30	mjames	3720	#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /!< Internal High Speed clock ready flag /
		3721
		3722	#define RCC_CR_MSION_Pos (8U)
50	mjames	3723	#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /!< 0x00000100 /
30	mjames	3724	#define RCC_CR_MSION RCC_CR_MSION_Msk /!< Internal Multi Speed clock enable /
		3725	#define RCC_CR_MSIRDY_Pos (9U)
50	mjames	3726	#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /!< 0x00000200 /
30	mjames	3727	#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /!< Internal Multi Speed clock ready flag /
		3728
		3729	#define RCC_CR_HSEON_Pos (16U)
50	mjames	3730	#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /!< 0x00010000 /
30	mjames	3731	#define RCC_CR_HSEON RCC_CR_HSEON_Msk /!< External High Speed clock enable /
		3732	#define RCC_CR_HSERDY_Pos (17U)
50	mjames	3733	#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /!< 0x00020000 /
30	mjames	3734	#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /!< External High Speed clock ready flag /
		3735	#define RCC_CR_HSEBYP_Pos (18U)
50	mjames	3736	#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /!< 0x00040000 /
30	mjames	3737	#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /!< External High Speed clock Bypass /
		3738
		3739	#define RCC_CR_PLLON_Pos (24U)
50	mjames	3740	#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /!< 0x01000000 /
30	mjames	3741	#define RCC_CR_PLLON RCC_CR_PLLON_Msk /!< PLL enable /
		3742	#define RCC_CR_PLLRDY_Pos (25U)
50	mjames	3743	#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /!< 0x02000000 /
30	mjames	3744	#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /!< PLL clock ready flag /
		3745	#define RCC_CR_CSSON_Pos (28U)
50	mjames	3746	#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /!< 0x10000000 /
30	mjames	3747	#define RCC_CR_CSSON RCC_CR_CSSON_Msk /!< Clock Security System enable /
		3748
		3749	#define RCC_CR_RTCPRE_Pos (29U)
50	mjames	3750	#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /!< 0x60000000 /
30	mjames	3751	#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /!< RTC Prescaler /
		3752	#define RCC_CR_RTCPRE_0 (0x20000000U) /!< Bit0 /
		3753	#define RCC_CR_RTCPRE_1 (0x40000000U) /!< Bit1 /
		3754
		3755	/****************** Bit definition for RCC_ICSCR register ***************/
		3756	#define RCC_ICSCR_HSICAL_Pos (0U)
50	mjames	3757	#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /!< 0x000000FF /
30	mjames	3758	#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /!< Internal High Speed clock Calibration /
		3759	#define RCC_ICSCR_HSITRIM_Pos (8U)
50	mjames	3760	#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /!< 0x00001F00 /
30	mjames	3761	#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /!< Internal High Speed clock trimming /
		3762
		3763	#define RCC_ICSCR_MSIRANGE_Pos (13U)
50	mjames	3764	#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /!< 0x0000E000 /
30	mjames	3765	#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /!< Internal Multi Speed clock Range /
50	mjames	3766	#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /!< 0x00000000 /
		3767	#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /!< 0x00002000 /
		3768	#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /!< 0x00004000 /
		3769	#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /!< 0x00006000 /
		3770	#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /!< 0x00008000 /
		3771	#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /!< 0x0000A000 /
		3772	#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /!< 0x0000C000 /
30	mjames	3773	#define RCC_ICSCR_MSICAL_Pos (16U)
50	mjames	3774	#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /!< 0x00FF0000 /
30	mjames	3775	#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /!< Internal Multi Speed clock Calibration /
		3776	#define RCC_ICSCR_MSITRIM_Pos (24U)
50	mjames	3777	#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /!< 0xFF000000 /
30	mjames	3778	#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /!< Internal Multi Speed clock trimming /
		3779
		3780	/****************** Bit definition for RCC_CFGR register ****************/
		3781	#define RCC_CFGR_SW_Pos (0U)
50	mjames	3782	#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /!< 0x00000003 /
30	mjames	3783	#define RCC_CFGR_SW RCC_CFGR_SW_Msk /!< SW[1:0] bits (System clock Switch) /
50	mjames	3784	#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /!< 0x00000001 /
		3785	#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /!< 0x00000002 /
30	mjames	3786
		3787	/!< SW configuration /
		3788	#define RCC_CFGR_SW_MSI (0x00000000U) /!< MSI selected as system clock /
		3789	#define RCC_CFGR_SW_HSI (0x00000001U) /!< HSI selected as system clock /
		3790	#define RCC_CFGR_SW_HSE (0x00000002U) /!< HSE selected as system clock /
		3791	#define RCC_CFGR_SW_PLL (0x00000003U) /!< PLL selected as system clock /
		3792
		3793	#define RCC_CFGR_SWS_Pos (2U)
50	mjames	3794	#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /!< 0x0000000C /
30	mjames	3795	#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /!< SWS[1:0] bits (System Clock Switch Status) /
50	mjames	3796	#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /!< 0x00000004 /
		3797	#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /!< 0x00000008 /
30	mjames	3798
		3799	/!< SWS configuration /
		3800	#define RCC_CFGR_SWS_MSI (0x00000000U) /!< MSI oscillator used as system clock /
		3801	#define RCC_CFGR_SWS_HSI (0x00000004U) /!< HSI oscillator used as system clock /
		3802	#define RCC_CFGR_SWS_HSE (0x00000008U) /!< HSE oscillator used as system clock /
		3803	#define RCC_CFGR_SWS_PLL (0x0000000CU) /!< PLL used as system clock /
		3804
		3805	#define RCC_CFGR_HPRE_Pos (4U)
50	mjames	3806	#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /!< 0x000000F0 /
30	mjames	3807	#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /!< HPRE[3:0] bits (AHB prescaler) /
50	mjames	3808	#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /!< 0x00000010 /
		3809	#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /!< 0x00000020 /
		3810	#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /!< 0x00000040 /
		3811	#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /!< 0x00000080 /
30	mjames	3812
		3813	/!< HPRE configuration /
		3814	#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /!< SYSCLK not divided /
		3815	#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /!< SYSCLK divided by 2 /
		3816	#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /!< SYSCLK divided by 4 /
		3817	#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /!< SYSCLK divided by 8 /
		3818	#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /!< SYSCLK divided by 16 /
		3819	#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /!< SYSCLK divided by 64 /
		3820	#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /!< SYSCLK divided by 128 /
		3821	#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /!< SYSCLK divided by 256 /
		3822	#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /!< SYSCLK divided by 512 /
		3823
		3824	#define RCC_CFGR_PPRE1_Pos (8U)
50	mjames	3825	#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000700 /
30	mjames	3826	#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /!< PRE1[2:0] bits (APB1 prescaler) /
50	mjames	3827	#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000100 /
		3828	#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000200 /
		3829	#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /!< 0x00000400 /
30	mjames	3830
		3831	/!< PPRE1 configuration /
		3832	#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /!< HCLK not divided /
		3833	#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /!< HCLK divided by 2 /
		3834	#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /!< HCLK divided by 4 /
		3835	#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /!< HCLK divided by 8 /
		3836	#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /!< HCLK divided by 16 /
		3837
		3838	#define RCC_CFGR_PPRE2_Pos (11U)
50	mjames	3839	#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /!< 0x00003800 /
30	mjames	3840	#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /!< PRE2[2:0] bits (APB2 prescaler) /
50	mjames	3841	#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /!< 0x00000800 /
		3842	#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /!< 0x00001000 /
		3843	#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /!< 0x00002000 /
30	mjames	3844
		3845	/!< PPRE2 configuration /
		3846	#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /!< HCLK not divided /
		3847	#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /!< HCLK divided by 2 /
		3848	#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /!< HCLK divided by 4 /
		3849	#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /!< HCLK divided by 8 /
		3850	#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /!< HCLK divided by 16 /
		3851
		3852	/!< PLL entry clock source/
		3853	#define RCC_CFGR_PLLSRC_Pos (16U)
50	mjames	3854	#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /!< 0x00010000 /
30	mjames	3855	#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /!< PLL entry clock source /
		3856
		3857	#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /!< HSI as PLL entry clock source /
		3858	#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /!< HSE as PLL entry clock source /
		3859
		3860
		3861	/!< PLLMUL configuration /
		3862	#define RCC_CFGR_PLLMUL_Pos (18U)
50	mjames	3863	#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /!< 0x003C0000 /
30	mjames	3864	#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /!< PLLMUL[3:0] bits (PLL multiplication factor) /
50	mjames	3865	#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /!< 0x00040000 /
		3866	#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /!< 0x00080000 /
		3867	#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /!< 0x00100000 /
		3868	#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /!< 0x00200000 /
30	mjames	3869
		3870	/!< PLLMUL configuration /
		3871	#define RCC_CFGR_PLLMUL3 (0x00000000U) /!< PLL input clock 3 */
		3872	#define RCC_CFGR_PLLMUL4 (0x00040000U) /!< PLL input clock 4 */
		3873	#define RCC_CFGR_PLLMUL6 (0x00080000U) /!< PLL input clock 6 */
		3874	#define RCC_CFGR_PLLMUL8 (0x000C0000U) /!< PLL input clock 8 */
		3875	#define RCC_CFGR_PLLMUL12 (0x00100000U) /!< PLL input clock 12 */
		3876	#define RCC_CFGR_PLLMUL16 (0x00140000U) /!< PLL input clock 16 */
		3877	#define RCC_CFGR_PLLMUL24 (0x00180000U) /!< PLL input clock 24 */
		3878	#define RCC_CFGR_PLLMUL32 (0x001C0000U) /!< PLL input clock 32 */
		3879	#define RCC_CFGR_PLLMUL48 (0x00200000U) /!< PLL input clock 48 */
		3880
		3881	/!< PLLDIV configuration /
		3882	#define RCC_CFGR_PLLDIV_Pos (22U)
50	mjames	3883	#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /!< 0x00C00000 /
30	mjames	3884	#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /!< PLLDIV[1:0] bits (PLL Output Division) /
50	mjames	3885	#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /!< 0x00400000 /
		3886	#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /!< 0x00800000 /
30	mjames	3887
		3888
		3889	/!< PLLDIV configuration /
		3890	#define RCC_CFGR_PLLDIV1 (0x00000000U) /!< PLL clock output = CKVCO / 1 /
		3891	#define RCC_CFGR_PLLDIV2_Pos (22U)
50	mjames	3892	#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /!< 0x00400000 /
30	mjames	3893	#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /!< PLL clock output = CKVCO / 2 /
		3894	#define RCC_CFGR_PLLDIV3_Pos (23U)
50	mjames	3895	#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /!< 0x00800000 /
30	mjames	3896	#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /!< PLL clock output = CKVCO / 3 /
		3897	#define RCC_CFGR_PLLDIV4_Pos (22U)
50	mjames	3898	#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /!< 0x00C00000 /
30	mjames	3899	#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /!< PLL clock output = CKVCO / 4 /
		3900
		3901
		3902	#define RCC_CFGR_MCOSEL_Pos (24U)
50	mjames	3903	#define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /!< 0x07000000 /
30	mjames	3904	#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /!< MCO[2:0] bits (Microcontroller Clock Output) /
50	mjames	3905	#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /!< 0x01000000 /
		3906	#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /!< 0x02000000 /
		3907	#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /!< 0x04000000 /
30	mjames	3908
		3909	/!< MCO configuration /
		3910	#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /!< No clock /
		3911	#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
50	mjames	3912	#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /!< 0x01000000 /
30	mjames	3913	#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /!< System clock selected /
		3914	#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
50	mjames	3915	#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /!< 0x02000000 /
30	mjames	3916	#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /!< Internal 16 MHz RC oscillator clock selected /
		3917	#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
50	mjames	3918	#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /!< 0x03000000 /
30	mjames	3919	#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /!< Internal Medium Speed RC oscillator clock selected /
		3920	#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
50	mjames	3921	#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /!< 0x04000000 /
30	mjames	3922	#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /!< External 1-25 MHz oscillator clock selected /
		3923	#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
50	mjames	3924	#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /!< 0x05000000 /
30	mjames	3925	#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /!< PLL clock divided /
		3926	#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
50	mjames	3927	#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /!< 0x06000000 /
30	mjames	3928	#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /!< LSI selected /
		3929	#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
50	mjames	3930	#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /!< 0x07000000 /
30	mjames	3931	#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /!< LSE selected /
		3932
		3933	#define RCC_CFGR_MCOPRE_Pos (28U)
50	mjames	3934	#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /!< 0x70000000 /
30	mjames	3935	#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) /
50	mjames	3936	#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /!< 0x10000000 /
		3937	#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /!< 0x20000000 /
		3938	#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /!< 0x40000000 /
30	mjames	3939
		3940	/!< MCO Prescaler configuration /
		3941	#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /!< MCO is divided by 1 /
		3942	#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /!< MCO is divided by 2 /
		3943	#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /!< MCO is divided by 4 /
		3944	#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /!< MCO is divided by 8 /
		3945	#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /!< MCO is divided by 16 /
		3946
		3947	/* Legacy aliases */
		3948	#define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1
		3949	#define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
		3950	#define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4
		3951	#define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8
		3952	#define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16
		3953	#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
		3954	#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
		3955	#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
		3956	#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
		3957	#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
		3958	#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
		3959	#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
		3960	#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
		3961
		3962	/!<*************** Bit definition for RCC_CIR register ******************/
		3963	#define RCC_CIR_LSIRDYF_Pos (0U)
50	mjames	3964	#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /!< 0x00000001 /
30	mjames	3965	#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /!< LSI Ready Interrupt flag /
		3966	#define RCC_CIR_LSERDYF_Pos (1U)
50	mjames	3967	#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /!< 0x00000002 /
30	mjames	3968	#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /!< LSE Ready Interrupt flag /
		3969	#define RCC_CIR_HSIRDYF_Pos (2U)
50	mjames	3970	#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /!< 0x00000004 /
30	mjames	3971	#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /!< HSI Ready Interrupt flag /
		3972	#define RCC_CIR_HSERDYF_Pos (3U)
50	mjames	3973	#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /!< 0x00000008 /
30	mjames	3974	#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /!< HSE Ready Interrupt flag /
		3975	#define RCC_CIR_PLLRDYF_Pos (4U)
50	mjames	3976	#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /!< 0x00000010 /
30	mjames	3977	#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /!< PLL Ready Interrupt flag /
		3978	#define RCC_CIR_MSIRDYF_Pos (5U)
50	mjames	3979	#define RCC_CIR_MSIRDYF_Msk (0x1UL << RCC_CIR_MSIRDYF_Pos) /!< 0x00000020 /
30	mjames	3980	#define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /!< MSI Ready Interrupt flag /
		3981	#define RCC_CIR_CSSF_Pos (7U)
50	mjames	3982	#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /!< 0x00000080 /
30	mjames	3983	#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /!< Clock Security System Interrupt flag /
		3984
		3985	#define RCC_CIR_LSIRDYIE_Pos (8U)
50	mjames	3986	#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /!< 0x00000100 /
30	mjames	3987	#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /!< LSI Ready Interrupt Enable /
		3988	#define RCC_CIR_LSERDYIE_Pos (9U)
50	mjames	3989	#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /!< 0x00000200 /
30	mjames	3990	#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /!< LSE Ready Interrupt Enable /
		3991	#define RCC_CIR_HSIRDYIE_Pos (10U)
50	mjames	3992	#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /!< 0x00000400 /
30	mjames	3993	#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /!< HSI Ready Interrupt Enable /
		3994	#define RCC_CIR_HSERDYIE_Pos (11U)
50	mjames	3995	#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /!< 0x00000800 /
30	mjames	3996	#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /!< HSE Ready Interrupt Enable /
		3997	#define RCC_CIR_PLLRDYIE_Pos (12U)
50	mjames	3998	#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /!< 0x00001000 /
30	mjames	3999	#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /!< PLL Ready Interrupt Enable /
		4000	#define RCC_CIR_MSIRDYIE_Pos (13U)
50	mjames	4001	#define RCC_CIR_MSIRDYIE_Msk (0x1UL << RCC_CIR_MSIRDYIE_Pos) /!< 0x00002000 /
30	mjames	4002	#define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /!< MSI Ready Interrupt Enable /
		4003
		4004	#define RCC_CIR_LSIRDYC_Pos (16U)
50	mjames	4005	#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /!< 0x00010000 /
30	mjames	4006	#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /!< LSI Ready Interrupt Clear /
		4007	#define RCC_CIR_LSERDYC_Pos (17U)
50	mjames	4008	#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /!< 0x00020000 /
30	mjames	4009	#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /!< LSE Ready Interrupt Clear /
		4010	#define RCC_CIR_HSIRDYC_Pos (18U)
50	mjames	4011	#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /!< 0x00040000 /
30	mjames	4012	#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /!< HSI Ready Interrupt Clear /
		4013	#define RCC_CIR_HSERDYC_Pos (19U)
50	mjames	4014	#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /!< 0x00080000 /
30	mjames	4015	#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /!< HSE Ready Interrupt Clear /
		4016	#define RCC_CIR_PLLRDYC_Pos (20U)
50	mjames	4017	#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /!< 0x00100000 /
30	mjames	4018	#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /!< PLL Ready Interrupt Clear /
		4019	#define RCC_CIR_MSIRDYC_Pos (21U)
50	mjames	4020	#define RCC_CIR_MSIRDYC_Msk (0x1UL << RCC_CIR_MSIRDYC_Pos) /!< 0x00200000 /
30	mjames	4021	#define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /!< MSI Ready Interrupt Clear /
		4022	#define RCC_CIR_CSSC_Pos (23U)
50	mjames	4023	#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /!< 0x00800000 /
30	mjames	4024	#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /!< Clock Security System Interrupt Clear /
		4025
		4026	/*************** Bit definition for RCC_AHBRSTR register ****************/
		4027	#define RCC_AHBRSTR_GPIOARST_Pos (0U)
50	mjames	4028	#define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /!< 0x00000001 /
30	mjames	4029	#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /!< GPIO port A reset /
		4030	#define RCC_AHBRSTR_GPIOBRST_Pos (1U)
50	mjames	4031	#define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /!< 0x00000002 /
30	mjames	4032	#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /!< GPIO port B reset /
		4033	#define RCC_AHBRSTR_GPIOCRST_Pos (2U)
50	mjames	4034	#define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /!< 0x00000004 /
30	mjames	4035	#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /!< GPIO port C reset /
		4036	#define RCC_AHBRSTR_GPIODRST_Pos (3U)
50	mjames	4037	#define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /!< 0x00000008 /
30	mjames	4038	#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /!< GPIO port D reset /
		4039	#define RCC_AHBRSTR_GPIOERST_Pos (4U)
50	mjames	4040	#define RCC_AHBRSTR_GPIOERST_Msk (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /!< 0x00000010 /
30	mjames	4041	#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /!< GPIO port E reset /
		4042	#define RCC_AHBRSTR_GPIOHRST_Pos (5U)
50	mjames	4043	#define RCC_AHBRSTR_GPIOHRST_Msk (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /!< 0x00000020 /
30	mjames	4044	#define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /!< GPIO port H reset /
		4045	#define RCC_AHBRSTR_CRCRST_Pos (12U)
50	mjames	4046	#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /!< 0x00001000 /
30	mjames	4047	#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /!< CRC reset /
		4048	#define RCC_AHBRSTR_FLITFRST_Pos (15U)
50	mjames	4049	#define RCC_AHBRSTR_FLITFRST_Msk (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /!< 0x00008000 /
30	mjames	4050	#define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /!< FLITF reset /
		4051	#define RCC_AHBRSTR_DMA1RST_Pos (24U)
50	mjames	4052	#define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /!< 0x01000000 /
30	mjames	4053	#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /!< DMA1 reset /
		4054
		4055	/*************** Bit definition for RCC_APB2RSTR register ***************/
		4056	#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
50	mjames	4057	#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /!< 0x00000001 /
30	mjames	4058	#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /!< System Configuration SYSCFG reset /
		4059	#define RCC_APB2RSTR_TIM9RST_Pos (2U)
50	mjames	4060	#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /!< 0x00000004 /
30	mjames	4061	#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /!< TIM9 reset /
		4062	#define RCC_APB2RSTR_TIM10RST_Pos (3U)
50	mjames	4063	#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /!< 0x00000008 /
30	mjames	4064	#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /!< TIM10 reset /
		4065	#define RCC_APB2RSTR_TIM11RST_Pos (4U)
50	mjames	4066	#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /!< 0x00000010 /
30	mjames	4067	#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /!< TIM11 reset /
		4068	#define RCC_APB2RSTR_ADC1RST_Pos (9U)
50	mjames	4069	#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /!< 0x00000200 /
30	mjames	4070	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /!< ADC1 reset /
		4071	#define RCC_APB2RSTR_SPI1RST_Pos (12U)
50	mjames	4072	#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /!< 0x00001000 /
30	mjames	4073	#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /!< SPI1 reset /
		4074	#define RCC_APB2RSTR_USART1RST_Pos (14U)
50	mjames	4075	#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /!< 0x00004000 /
30	mjames	4076	#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /!< USART1 reset /
		4077
		4078	/*************** Bit definition for RCC_APB1RSTR register ***************/
		4079	#define RCC_APB1RSTR_TIM2RST_Pos (0U)
50	mjames	4080	#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /!< 0x00000001 /
30	mjames	4081	#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /!< Timer 2 reset /
		4082	#define RCC_APB1RSTR_TIM3RST_Pos (1U)
50	mjames	4083	#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /!< 0x00000002 /
30	mjames	4084	#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /!< Timer 3 reset /
		4085	#define RCC_APB1RSTR_TIM4RST_Pos (2U)
50	mjames	4086	#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /!< 0x00000004 /
30	mjames	4087	#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /!< Timer 4 reset /
		4088	#define RCC_APB1RSTR_TIM6RST_Pos (4U)
50	mjames	4089	#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /!< 0x00000010 /
30	mjames	4090	#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /!< Timer 6 reset /
		4091	#define RCC_APB1RSTR_TIM7RST_Pos (5U)
50	mjames	4092	#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /!< 0x00000020 /
30	mjames	4093	#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /!< Timer 7 reset /
		4094	#define RCC_APB1RSTR_WWDGRST_Pos (11U)
50	mjames	4095	#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /!< 0x00000800 /
30	mjames	4096	#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /!< Window Watchdog reset /
		4097	#define RCC_APB1RSTR_SPI2RST_Pos (14U)
50	mjames	4098	#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /!< 0x00004000 /
30	mjames	4099	#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /!< SPI 2 reset /
		4100	#define RCC_APB1RSTR_USART2RST_Pos (17U)
50	mjames	4101	#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /!< 0x00020000 /
30	mjames	4102	#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /!< USART 2 reset /
		4103	#define RCC_APB1RSTR_USART3RST_Pos (18U)
50	mjames	4104	#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /!< 0x00040000 /
30	mjames	4105	#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /!< USART 3 reset /
		4106	#define RCC_APB1RSTR_I2C1RST_Pos (21U)
50	mjames	4107	#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /!< 0x00200000 /
30	mjames	4108	#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /!< I2C 1 reset /
		4109	#define RCC_APB1RSTR_I2C2RST_Pos (22U)
50	mjames	4110	#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /!< 0x00400000 /
30	mjames	4111	#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /!< I2C 2 reset /
		4112	#define RCC_APB1RSTR_USBRST_Pos (23U)
50	mjames	4113	#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /!< 0x00800000 /
30	mjames	4114	#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /!< USB reset /
		4115	#define RCC_APB1RSTR_PWRRST_Pos (28U)
50	mjames	4116	#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /!< 0x10000000 /
30	mjames	4117	#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /!< Power interface reset /
		4118	#define RCC_APB1RSTR_DACRST_Pos (29U)
50	mjames	4119	#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /!< 0x20000000 /
30	mjames	4120	#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /!< DAC interface reset /
		4121	#define RCC_APB1RSTR_COMPRST_Pos (31U)
50	mjames	4122	#define RCC_APB1RSTR_COMPRST_Msk (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /!< 0x80000000 /
30	mjames	4123	#define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /!< Comparator interface reset /
		4124
		4125	/**************** Bit definition for RCC_AHBENR register ****************/
		4126	#define RCC_AHBENR_GPIOAEN_Pos (0U)
50	mjames	4127	#define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /!< 0x00000001 /
30	mjames	4128	#define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /!< GPIO port A clock enable /
		4129	#define RCC_AHBENR_GPIOBEN_Pos (1U)
50	mjames	4130	#define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /!< 0x00000002 /
30	mjames	4131	#define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /!< GPIO port B clock enable /
		4132	#define RCC_AHBENR_GPIOCEN_Pos (2U)
50	mjames	4133	#define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /!< 0x00000004 /
30	mjames	4134	#define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /!< GPIO port C clock enable /
		4135	#define RCC_AHBENR_GPIODEN_Pos (3U)
50	mjames	4136	#define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos) /!< 0x00000008 /
30	mjames	4137	#define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /!< GPIO port D clock enable /
		4138	#define RCC_AHBENR_GPIOEEN_Pos (4U)
50	mjames	4139	#define RCC_AHBENR_GPIOEEN_Msk (0x1UL << RCC_AHBENR_GPIOEEN_Pos) /!< 0x00000010 /
30	mjames	4140	#define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /!< GPIO port E clock enable /
		4141	#define RCC_AHBENR_GPIOHEN_Pos (5U)
50	mjames	4142	#define RCC_AHBENR_GPIOHEN_Msk (0x1UL << RCC_AHBENR_GPIOHEN_Pos) /!< 0x00000020 /
30	mjames	4143	#define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /!< GPIO port H clock enable /
		4144	#define RCC_AHBENR_CRCEN_Pos (12U)
50	mjames	4145	#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /!< 0x00001000 /
30	mjames	4146	#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /!< CRC clock enable /
		4147	#define RCC_AHBENR_FLITFEN_Pos (15U)
50	mjames	4148	#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /!< 0x00008000 /
30	mjames	4149	#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when
		4150	the Flash memory is in power down mode) */
		4151	#define RCC_AHBENR_DMA1EN_Pos (24U)
50	mjames	4152	#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /!< 0x01000000 /
30	mjames	4153	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /!< DMA1 clock enable /
		4154
		4155	/**************** Bit definition for RCC_APB2ENR register ***************/
		4156	#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
50	mjames	4157	#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /!< 0x00000001 /
30	mjames	4158	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /!< System Configuration SYSCFG clock enable /
		4159	#define RCC_APB2ENR_TIM9EN_Pos (2U)
50	mjames	4160	#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /!< 0x00000004 /
30	mjames	4161	#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /!< TIM9 interface clock enable /
		4162	#define RCC_APB2ENR_TIM10EN_Pos (3U)
50	mjames	4163	#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /!< 0x00000008 /
30	mjames	4164	#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /!< TIM10 interface clock enable /
		4165	#define RCC_APB2ENR_TIM11EN_Pos (4U)
50	mjames	4166	#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /!< 0x00000010 /
30	mjames	4167	#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /!< TIM11 Timer clock enable /
		4168	#define RCC_APB2ENR_ADC1EN_Pos (9U)
50	mjames	4169	#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /!< 0x00000200 /
30	mjames	4170	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /!< ADC1 clock enable /
		4171	#define RCC_APB2ENR_SPI1EN_Pos (12U)
50	mjames	4172	#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /!< 0x00001000 /
30	mjames	4173	#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /!< SPI1 clock enable /
		4174	#define RCC_APB2ENR_USART1EN_Pos (14U)
50	mjames	4175	#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /!< 0x00004000 /
30	mjames	4176	#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /!< USART1 clock enable /
		4177
		4178	/*************** Bit definition for RCC_APB1ENR register ****************/
		4179	#define RCC_APB1ENR_TIM2EN_Pos (0U)
50	mjames	4180	#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /!< 0x00000001 /
30	mjames	4181	#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /!< Timer 2 clock enabled/
		4182	#define RCC_APB1ENR_TIM3EN_Pos (1U)
50	mjames	4183	#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /!< 0x00000002 /
30	mjames	4184	#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /!< Timer 3 clock enable /
		4185	#define RCC_APB1ENR_TIM4EN_Pos (2U)
50	mjames	4186	#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /!< 0x00000004 /
30	mjames	4187	#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /!< Timer 4 clock enable /
		4188	#define RCC_APB1ENR_TIM6EN_Pos (4U)
50	mjames	4189	#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /!< 0x00000010 /
30	mjames	4190	#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /!< Timer 6 clock enable /
		4191	#define RCC_APB1ENR_TIM7EN_Pos (5U)
50	mjames	4192	#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /!< 0x00000020 /
30	mjames	4193	#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /!< Timer 7 clock enable /
		4194	#define RCC_APB1ENR_WWDGEN_Pos (11U)
50	mjames	4195	#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /!< 0x00000800 /
30	mjames	4196	#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /!< Window Watchdog clock enable /
		4197	#define RCC_APB1ENR_SPI2EN_Pos (14U)
50	mjames	4198	#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /!< 0x00004000 /
30	mjames	4199	#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /!< SPI 2 clock enable /
		4200	#define RCC_APB1ENR_USART2EN_Pos (17U)
50	mjames	4201	#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /!< 0x00020000 /
30	mjames	4202	#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /!< USART 2 clock enable /
		4203	#define RCC_APB1ENR_USART3EN_Pos (18U)
50	mjames	4204	#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /!< 0x00040000 /
30	mjames	4205	#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /!< USART 3 clock enable /
		4206	#define RCC_APB1ENR_I2C1EN_Pos (21U)
50	mjames	4207	#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /!< 0x00200000 /
30	mjames	4208	#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /!< I2C 1 clock enable /
		4209	#define RCC_APB1ENR_I2C2EN_Pos (22U)
50	mjames	4210	#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /!< 0x00400000 /
30	mjames	4211	#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /!< I2C 2 clock enable /
		4212	#define RCC_APB1ENR_USBEN_Pos (23U)
50	mjames	4213	#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /!< 0x00800000 /
30	mjames	4214	#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /!< USB clock enable /
		4215	#define RCC_APB1ENR_PWREN_Pos (28U)
50	mjames	4216	#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /!< 0x10000000 /
30	mjames	4217	#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /!< Power interface clock enable /
		4218	#define RCC_APB1ENR_DACEN_Pos (29U)
50	mjames	4219	#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /!< 0x20000000 /
30	mjames	4220	#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /!< DAC interface clock enable /
		4221	#define RCC_APB1ENR_COMPEN_Pos (31U)
50	mjames	4222	#define RCC_APB1ENR_COMPEN_Msk (0x1UL << RCC_APB1ENR_COMPEN_Pos) /!< 0x80000000 /
30	mjames	4223	#define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /!< Comparator interface clock enable /
		4224
		4225	/**************** Bit definition for RCC_AHBLPENR register **************/
		4226	#define RCC_AHBLPENR_GPIOALPEN_Pos (0U)
50	mjames	4227	#define RCC_AHBLPENR_GPIOALPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /!< 0x00000001 /
30	mjames	4228	#define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /!< GPIO port A clock enabled in sleep mode /
		4229	#define RCC_AHBLPENR_GPIOBLPEN_Pos (1U)
50	mjames	4230	#define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /!< 0x00000002 /
30	mjames	4231	#define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /!< GPIO port B clock enabled in sleep mode /
		4232	#define RCC_AHBLPENR_GPIOCLPEN_Pos (2U)
50	mjames	4233	#define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /!< 0x00000004 /
30	mjames	4234	#define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /!< GPIO port C clock enabled in sleep mode /
		4235	#define RCC_AHBLPENR_GPIODLPEN_Pos (3U)
50	mjames	4236	#define RCC_AHBLPENR_GPIODLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /!< 0x00000008 /
30	mjames	4237	#define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /!< GPIO port D clock enabled in sleep mode /
		4238	#define RCC_AHBLPENR_GPIOELPEN_Pos (4U)
50	mjames	4239	#define RCC_AHBLPENR_GPIOELPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /!< 0x00000010 /
30	mjames	4240	#define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /!< GPIO port E clock enabled in sleep mode /
		4241	#define RCC_AHBLPENR_GPIOHLPEN_Pos (5U)
50	mjames	4242	#define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /!< 0x00000020 /
30	mjames	4243	#define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /!< GPIO port H clock enabled in sleep mode /
		4244	#define RCC_AHBLPENR_CRCLPEN_Pos (12U)
50	mjames	4245	#define RCC_AHBLPENR_CRCLPEN_Msk (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /!< 0x00001000 /
30	mjames	4246	#define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /!< CRC clock enabled in sleep mode /
		4247	#define RCC_AHBLPENR_FLITFLPEN_Pos (15U)
50	mjames	4248	#define RCC_AHBLPENR_FLITFLPEN_Msk (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /!< 0x00008000 /
30	mjames	4249	#define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode
		4250	(has effect only when the Flash memory is
		4251	in power down mode) */
		4252	#define RCC_AHBLPENR_SRAMLPEN_Pos (16U)
50	mjames	4253	#define RCC_AHBLPENR_SRAMLPEN_Msk (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /!< 0x00010000 /
30	mjames	4254	#define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /!< SRAM clock enabled in sleep mode /
		4255	#define RCC_AHBLPENR_DMA1LPEN_Pos (24U)
50	mjames	4256	#define RCC_AHBLPENR_DMA1LPEN_Msk (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /!< 0x01000000 /
30	mjames	4257	#define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /!< DMA1 clock enabled in sleep mode /
		4258
		4259	/**************** Bit definition for RCC_APB2LPENR register *************/
		4260	#define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U)
50	mjames	4261	#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /!< 0x00000001 /
30	mjames	4262	#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /!< System Configuration SYSCFG clock enabled in sleep mode /
		4263	#define RCC_APB2LPENR_TIM9LPEN_Pos (2U)
50	mjames	4264	#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /!< 0x00000004 /
30	mjames	4265	#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /!< TIM9 interface clock enabled in sleep mode /
		4266	#define RCC_APB2LPENR_TIM10LPEN_Pos (3U)
50	mjames	4267	#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /!< 0x00000008 /
30	mjames	4268	#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /!< TIM10 interface clock enabled in sleep mode /
		4269	#define RCC_APB2LPENR_TIM11LPEN_Pos (4U)
50	mjames	4270	#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /!< 0x00000010 /
30	mjames	4271	#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /!< TIM11 Timer clock enabled in sleep mode /
		4272	#define RCC_APB2LPENR_ADC1LPEN_Pos (9U)
50	mjames	4273	#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /!< 0x00000200 /
30	mjames	4274	#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /!< ADC1 clock enabled in sleep mode /
		4275	#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
50	mjames	4276	#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /!< 0x00001000 /
30	mjames	4277	#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /!< SPI1 clock enabled in sleep mode /
		4278	#define RCC_APB2LPENR_USART1LPEN_Pos (14U)
50	mjames	4279	#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /!< 0x00004000 /
30	mjames	4280	#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /!< USART1 clock enabled in sleep mode /
		4281
		4282	/*************** Bit definition for RCC_APB1LPENR register **************/
		4283	#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
50	mjames	4284	#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /!< 0x00000001 /
30	mjames	4285	#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /!< Timer 2 clock enabled in sleep mode /
		4286	#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
50	mjames	4287	#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /!< 0x00000002 /
30	mjames	4288	#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /!< Timer 3 clock enabled in sleep mode /
		4289	#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
50	mjames	4290	#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /!< 0x00000004 /
30	mjames	4291	#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /!< Timer 4 clock enabled in sleep mode /
		4292	#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
50	mjames	4293	#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /!< 0x00000010 /
30	mjames	4294	#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /!< Timer 6 clock enabled in sleep mode /
		4295	#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
50	mjames	4296	#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /!< 0x00000020 /
30	mjames	4297	#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /!< Timer 7 clock enabled in sleep mode /
		4298	#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
50	mjames	4299	#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /!< 0x00000800 /
30	mjames	4300	#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /!< Window Watchdog clock enabled in sleep mode /
		4301	#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
50	mjames	4302	#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /!< 0x00004000 /
30	mjames	4303	#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /!< SPI 2 clock enabled in sleep mode /
		4304	#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
50	mjames	4305	#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /!< 0x00020000 /
30	mjames	4306	#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /!< USART 2 clock enabled in sleep mode /
		4307	#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
50	mjames	4308	#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /!< 0x00040000 /
30	mjames	4309	#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /!< USART 3 clock enabled in sleep mode /
		4310	#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
50	mjames	4311	#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /!< 0x00200000 /
30	mjames	4312	#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /!< I2C 1 clock enabled in sleep mode /
		4313	#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
50	mjames	4314	#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /!< 0x00400000 /
30	mjames	4315	#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /!< I2C 2 clock enabled in sleep mode /
		4316	#define RCC_APB1LPENR_USBLPEN_Pos (23U)
50	mjames	4317	#define RCC_APB1LPENR_USBLPEN_Msk (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /!< 0x00800000 /
30	mjames	4318	#define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /!< USB clock enabled in sleep mode /
		4319	#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
50	mjames	4320	#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /!< 0x10000000 /
30	mjames	4321	#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /!< Power interface clock enabled in sleep mode /
		4322	#define RCC_APB1LPENR_DACLPEN_Pos (29U)
50	mjames	4323	#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /!< 0x20000000 /
30	mjames	4324	#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /!< DAC interface clock enabled in sleep mode /
		4325	#define RCC_APB1LPENR_COMPLPEN_Pos (31U)
50	mjames	4326	#define RCC_APB1LPENR_COMPLPEN_Msk (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /!< 0x80000000 /
30	mjames	4327	#define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /!< Comparator interface clock enabled in sleep mode/
		4328
		4329	/***************** Bit definition for RCC_CSR register ******************/
		4330	#define RCC_CSR_LSION_Pos (0U)
50	mjames	4331	#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /!< 0x00000001 /
30	mjames	4332	#define RCC_CSR_LSION RCC_CSR_LSION_Msk /!< Internal Low Speed oscillator enable /
		4333	#define RCC_CSR_LSIRDY_Pos (1U)
50	mjames	4334	#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /!< 0x00000002 /
30	mjames	4335	#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /!< Internal Low Speed oscillator Ready /
		4336
		4337	#define RCC_CSR_LSEON_Pos (8U)
50	mjames	4338	#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /!< 0x00000100 /
30	mjames	4339	#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /!< External Low Speed oscillator enable /
		4340	#define RCC_CSR_LSERDY_Pos (9U)
50	mjames	4341	#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /!< 0x00000200 /
30	mjames	4342	#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /!< External Low Speed oscillator Ready /
		4343	#define RCC_CSR_LSEBYP_Pos (10U)
50	mjames	4344	#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /!< 0x00000400 /
30	mjames	4345	#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /!< External Low Speed oscillator Bypass /
		4346
		4347	#define RCC_CSR_RTCSEL_Pos (16U)
50	mjames	4348	#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /!< 0x00030000 /
30	mjames	4349	#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /!< RTCSEL[1:0] bits (RTC clock source selection) /
50	mjames	4350	#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /!< 0x00010000 /
		4351	#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /!< 0x00020000 /
30	mjames	4352
		4353	/!< RTC congiguration /
		4354	#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /!< No clock /
		4355	#define RCC_CSR_RTCSEL_LSE_Pos (16U)
50	mjames	4356	#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /!< 0x00010000 /
30	mjames	4357	#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /!< LSE oscillator clock used as RTC clock /
		4358	#define RCC_CSR_RTCSEL_LSI_Pos (17U)
50	mjames	4359	#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /!< 0x00020000 /
30	mjames	4360	#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /!< LSI oscillator clock used as RTC clock /
		4361	#define RCC_CSR_RTCSEL_HSE_Pos (16U)
50	mjames	4362	#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /!< 0x00030000 /
30	mjames	4363	#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock /
		4364
		4365	#define RCC_CSR_RTCEN_Pos (22U)
50	mjames	4366	#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /!< 0x00400000 /
30	mjames	4367	#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /!< RTC clock enable /
		4368	#define RCC_CSR_RTCRST_Pos (23U)
50	mjames	4369	#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /!< 0x00800000 /
30	mjames	4370	#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /!< RTC reset /
		4371
		4372	#define RCC_CSR_RMVF_Pos (24U)
50	mjames	4373	#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /!< 0x01000000 /
30	mjames	4374	#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /!< Remove reset flag /
		4375	#define RCC_CSR_OBLRSTF_Pos (25U)
50	mjames	4376	#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /!< 0x02000000 /
30	mjames	4377	#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /!< Option Bytes Loader reset flag /
		4378	#define RCC_CSR_PINRSTF_Pos (26U)
50	mjames	4379	#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /!< 0x04000000 /
30	mjames	4380	#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /!< PIN reset flag /
		4381	#define RCC_CSR_PORRSTF_Pos (27U)
50	mjames	4382	#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /!< 0x08000000 /
30	mjames	4383	#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /!< POR/PDR reset flag /
		4384	#define RCC_CSR_SFTRSTF_Pos (28U)
50	mjames	4385	#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /!< 0x10000000 /
30	mjames	4386	#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /!< Software Reset flag /
		4387	#define RCC_CSR_IWDGRSTF_Pos (29U)
50	mjames	4388	#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /!< 0x20000000 /
30	mjames	4389	#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /!< Independent Watchdog reset flag /
		4390	#define RCC_CSR_WWDGRSTF_Pos (30U)
50	mjames	4391	#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /!< 0x40000000 /
30	mjames	4392	#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /!< Window watchdog reset flag /
		4393	#define RCC_CSR_LPWRRSTF_Pos (31U)
50	mjames	4394	#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /!< 0x80000000 /
30	mjames	4395	#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /!< Low-Power reset flag /
		4396
		4397	/******************************************************************************/
		4398	/* */
		4399	/* Real-Time Clock (RTC) */
		4400	/* */
		4401	/******************************************************************************/
		4402	/*
		4403	* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
		4404	*/
		4405	#define RTC_TAMPER1_SUPPORT /!< TAMPER 1 feature support /
		4406	#define RTC_BACKUP_SUPPORT /!< BACKUP register feature support /
		4407	#define RTC_WAKEUP_SUPPORT /!< WAKEUP feature support /
		4408
		4409	/****************** Bits definition for RTC_TR register *****************/
		4410	#define RTC_TR_PM_Pos (22U)
50	mjames	4411	#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /!< 0x00400000 /
30	mjames	4412	#define RTC_TR_PM RTC_TR_PM_Msk
		4413	#define RTC_TR_HT_Pos (20U)
50	mjames	4414	#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /!< 0x00300000 /
30	mjames	4415	#define RTC_TR_HT RTC_TR_HT_Msk
50	mjames	4416	#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /!< 0x00100000 /
		4417	#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /!< 0x00200000 /
30	mjames	4418	#define RTC_TR_HU_Pos (16U)
50	mjames	4419	#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /!< 0x000F0000 /
30	mjames	4420	#define RTC_TR_HU RTC_TR_HU_Msk
50	mjames	4421	#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /!< 0x00010000 /
		4422	#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /!< 0x00020000 /
		4423	#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /!< 0x00040000 /
		4424	#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /!< 0x00080000 /
30	mjames	4425	#define RTC_TR_MNT_Pos (12U)
50	mjames	4426	#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /!< 0x00007000 /
30	mjames	4427	#define RTC_TR_MNT RTC_TR_MNT_Msk
50	mjames	4428	#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /!< 0x00001000 /
		4429	#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /!< 0x00002000 /
		4430	#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /!< 0x00004000 /
30	mjames	4431	#define RTC_TR_MNU_Pos (8U)
50	mjames	4432	#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /!< 0x00000F00 /
30	mjames	4433	#define RTC_TR_MNU RTC_TR_MNU_Msk
50	mjames	4434	#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /!< 0x00000100 /
		4435	#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /!< 0x00000200 /
		4436	#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /!< 0x00000400 /
		4437	#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /!< 0x00000800 /
30	mjames	4438	#define RTC_TR_ST_Pos (4U)
50	mjames	4439	#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /!< 0x00000070 /
30	mjames	4440	#define RTC_TR_ST RTC_TR_ST_Msk
50	mjames	4441	#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /!< 0x00000010 /
		4442	#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /!< 0x00000020 /
		4443	#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /!< 0x00000040 /
30	mjames	4444	#define RTC_TR_SU_Pos (0U)
50	mjames	4445	#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /!< 0x0000000F /
30	mjames	4446	#define RTC_TR_SU RTC_TR_SU_Msk
50	mjames	4447	#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /!< 0x00000001 /
		4448	#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /!< 0x00000002 /
		4449	#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /!< 0x00000004 /
		4450	#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /!< 0x00000008 /
30	mjames	4451
		4452	/****************** Bits definition for RTC_DR register *****************/
		4453	#define RTC_DR_YT_Pos (20U)
50	mjames	4454	#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /!< 0x00F00000 /
30	mjames	4455	#define RTC_DR_YT RTC_DR_YT_Msk
50	mjames	4456	#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /!< 0x00100000 /
		4457	#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /!< 0x00200000 /
		4458	#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /!< 0x00400000 /
		4459	#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /!< 0x00800000 /
30	mjames	4460	#define RTC_DR_YU_Pos (16U)
50	mjames	4461	#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /!< 0x000F0000 /
30	mjames	4462	#define RTC_DR_YU RTC_DR_YU_Msk
50	mjames	4463	#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /!< 0x00010000 /
		4464	#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /!< 0x00020000 /
		4465	#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /!< 0x00040000 /
		4466	#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /!< 0x00080000 /
30	mjames	4467	#define RTC_DR_WDU_Pos (13U)
50	mjames	4468	#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /!< 0x0000E000 /
30	mjames	4469	#define RTC_DR_WDU RTC_DR_WDU_Msk
50	mjames	4470	#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /!< 0x00002000 /
		4471	#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /!< 0x00004000 /
		4472	#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /!< 0x00008000 /
30	mjames	4473	#define RTC_DR_MT_Pos (12U)
50	mjames	4474	#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /!< 0x00001000 /
30	mjames	4475	#define RTC_DR_MT RTC_DR_MT_Msk
		4476	#define RTC_DR_MU_Pos (8U)
50	mjames	4477	#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /!< 0x00000F00 /
30	mjames	4478	#define RTC_DR_MU RTC_DR_MU_Msk
50	mjames	4479	#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /!< 0x00000100 /
		4480	#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /!< 0x00000200 /
		4481	#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /!< 0x00000400 /
		4482	#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /!< 0x00000800 /
30	mjames	4483	#define RTC_DR_DT_Pos (4U)
50	mjames	4484	#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /!< 0x00000030 /
30	mjames	4485	#define RTC_DR_DT RTC_DR_DT_Msk
50	mjames	4486	#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /!< 0x00000010 /
		4487	#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /!< 0x00000020 /
30	mjames	4488	#define RTC_DR_DU_Pos (0U)
50	mjames	4489	#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /!< 0x0000000F /
30	mjames	4490	#define RTC_DR_DU RTC_DR_DU_Msk
50	mjames	4491	#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /!< 0x00000001 /
		4492	#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /!< 0x00000002 /
		4493	#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /!< 0x00000004 /
		4494	#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /!< 0x00000008 /
30	mjames	4495
		4496	/****************** Bits definition for RTC_CR register *****************/
		4497	#define RTC_CR_COE_Pos (23U)
50	mjames	4498	#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /!< 0x00800000 /
30	mjames	4499	#define RTC_CR_COE RTC_CR_COE_Msk
		4500	#define RTC_CR_OSEL_Pos (21U)
50	mjames	4501	#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /!< 0x00600000 /
30	mjames	4502	#define RTC_CR_OSEL RTC_CR_OSEL_Msk
50	mjames	4503	#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /!< 0x00200000 /
		4504	#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /!< 0x00400000 /
30	mjames	4505	#define RTC_CR_POL_Pos (20U)
50	mjames	4506	#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /!< 0x00100000 /
30	mjames	4507	#define RTC_CR_POL RTC_CR_POL_Msk
50	mjames	4508	#define RTC_CR_BKP_Pos (18U)
		4509	#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /!< 0x00040000 /
		4510	#define RTC_CR_BKP RTC_CR_BKP_Msk
30	mjames	4511	#define RTC_CR_SUB1H_Pos (17U)
50	mjames	4512	#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /!< 0x00020000 /
30	mjames	4513	#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
		4514	#define RTC_CR_ADD1H_Pos (16U)
50	mjames	4515	#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /!< 0x00010000 /
30	mjames	4516	#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
		4517	#define RTC_CR_TSIE_Pos (15U)
50	mjames	4518	#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /!< 0x00008000 /
30	mjames	4519	#define RTC_CR_TSIE RTC_CR_TSIE_Msk
		4520	#define RTC_CR_WUTIE_Pos (14U)
50	mjames	4521	#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /!< 0x00004000 /
30	mjames	4522	#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
		4523	#define RTC_CR_ALRBIE_Pos (13U)
50	mjames	4524	#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /!< 0x00002000 /
30	mjames	4525	#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
		4526	#define RTC_CR_ALRAIE_Pos (12U)
50	mjames	4527	#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /!< 0x00001000 /
30	mjames	4528	#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
		4529	#define RTC_CR_TSE_Pos (11U)
50	mjames	4530	#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /!< 0x00000800 /
30	mjames	4531	#define RTC_CR_TSE RTC_CR_TSE_Msk
		4532	#define RTC_CR_WUTE_Pos (10U)
50	mjames	4533	#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /!< 0x00000400 /
30	mjames	4534	#define RTC_CR_WUTE RTC_CR_WUTE_Msk
		4535	#define RTC_CR_ALRBE_Pos (9U)
50	mjames	4536	#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /!< 0x00000200 /
30	mjames	4537	#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
		4538	#define RTC_CR_ALRAE_Pos (8U)
50	mjames	4539	#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /!< 0x00000100 /
30	mjames	4540	#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
		4541	#define RTC_CR_DCE_Pos (7U)
50	mjames	4542	#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /!< 0x00000080 /
30	mjames	4543	#define RTC_CR_DCE RTC_CR_DCE_Msk
		4544	#define RTC_CR_FMT_Pos (6U)
50	mjames	4545	#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /!< 0x00000040 /
30	mjames	4546	#define RTC_CR_FMT RTC_CR_FMT_Msk
		4547	#define RTC_CR_REFCKON_Pos (4U)
50	mjames	4548	#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /!< 0x00000010 /
30	mjames	4549	#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
		4550	#define RTC_CR_TSEDGE_Pos (3U)
50	mjames	4551	#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /!< 0x00000008 /
30	mjames	4552	#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
		4553	#define RTC_CR_WUCKSEL_Pos (0U)
50	mjames	4554	#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /!< 0x00000007 /
30	mjames	4555	#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
50	mjames	4556	#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /!< 0x00000001 /
		4557	#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /!< 0x00000002 /
		4558	#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /!< 0x00000004 /
30	mjames	4559
50	mjames	4560	/* Legacy defines */
		4561	#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
		4562	#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
		4563	#define RTC_CR_BCK RTC_CR_BKP
		4564
30	mjames	4565	/****************** Bits definition for RTC_ISR register ****************/
		4566	#define RTC_ISR_TAMP1F_Pos (13U)
50	mjames	4567	#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /!< 0x00002000 /
30	mjames	4568	#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
		4569	#define RTC_ISR_TSOVF_Pos (12U)
50	mjames	4570	#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /!< 0x00001000 /
30	mjames	4571	#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
		4572	#define RTC_ISR_TSF_Pos (11U)
50	mjames	4573	#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /!< 0x00000800 /
30	mjames	4574	#define RTC_ISR_TSF RTC_ISR_TSF_Msk
		4575	#define RTC_ISR_WUTF_Pos (10U)
50	mjames	4576	#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /!< 0x00000400 /
30	mjames	4577	#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
		4578	#define RTC_ISR_ALRBF_Pos (9U)
50	mjames	4579	#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /!< 0x00000200 /
30	mjames	4580	#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
		4581	#define RTC_ISR_ALRAF_Pos (8U)
50	mjames	4582	#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /!< 0x00000100 /
30	mjames	4583	#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
		4584	#define RTC_ISR_INIT_Pos (7U)
50	mjames	4585	#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /!< 0x00000080 /
30	mjames	4586	#define RTC_ISR_INIT RTC_ISR_INIT_Msk
		4587	#define RTC_ISR_INITF_Pos (6U)
50	mjames	4588	#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /!< 0x00000040 /
30	mjames	4589	#define RTC_ISR_INITF RTC_ISR_INITF_Msk
		4590	#define RTC_ISR_RSF_Pos (5U)
50	mjames	4591	#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /!< 0x00000020 /
30	mjames	4592	#define RTC_ISR_RSF RTC_ISR_RSF_Msk
		4593	#define RTC_ISR_INITS_Pos (4U)
50	mjames	4594	#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /!< 0x00000010 /
30	mjames	4595	#define RTC_ISR_INITS RTC_ISR_INITS_Msk
		4596	#define RTC_ISR_WUTWF_Pos (2U)
50	mjames	4597	#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /!< 0x00000004 /
30	mjames	4598	#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
		4599	#define RTC_ISR_ALRBWF_Pos (1U)
50	mjames	4600	#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /!< 0x00000002 /
30	mjames	4601	#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
		4602	#define RTC_ISR_ALRAWF_Pos (0U)
50	mjames	4603	#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /!< 0x00000001 /
30	mjames	4604	#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
		4605
		4606	/****************** Bits definition for RTC_PRER register ***************/
		4607	#define RTC_PRER_PREDIV_A_Pos (16U)
50	mjames	4608	#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /!< 0x007F0000 /
30	mjames	4609	#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
		4610	#define RTC_PRER_PREDIV_S_Pos (0U)
50	mjames	4611	#define RTC_PRER_PREDIV_S_Msk (0x1FFFUL << RTC_PRER_PREDIV_S_Pos) /!< 0x00001FFF /
30	mjames	4612	#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
		4613
		4614	/****************** Bits definition for RTC_WUTR register ***************/
		4615	#define RTC_WUTR_WUT_Pos (0U)
50	mjames	4616	#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /!< 0x0000FFFF /
30	mjames	4617	#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
		4618
		4619	/****************** Bits definition for RTC_CALIBR register *************/
		4620	#define RTC_CALIBR_DCS_Pos (7U)
50	mjames	4621	#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /!< 0x00000080 /
30	mjames	4622	#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
		4623	#define RTC_CALIBR_DC_Pos (0U)
50	mjames	4624	#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /!< 0x0000001F /
30	mjames	4625	#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
		4626
		4627	/****************** Bits definition for RTC_ALRMAR register *************/
		4628	#define RTC_ALRMAR_MSK4_Pos (31U)
50	mjames	4629	#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /!< 0x80000000 /
30	mjames	4630	#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
		4631	#define RTC_ALRMAR_WDSEL_Pos (30U)
50	mjames	4632	#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /!< 0x40000000 /
30	mjames	4633	#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
		4634	#define RTC_ALRMAR_DT_Pos (28U)
50	mjames	4635	#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /!< 0x30000000 /
30	mjames	4636	#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
50	mjames	4637	#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /!< 0x10000000 /
		4638	#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /!< 0x20000000 /
30	mjames	4639	#define RTC_ALRMAR_DU_Pos (24U)
50	mjames	4640	#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /!< 0x0F000000 /
30	mjames	4641	#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
50	mjames	4642	#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /!< 0x01000000 /
		4643	#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /!< 0x02000000 /
		4644	#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /!< 0x04000000 /
		4645	#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /!< 0x08000000 /
30	mjames	4646	#define RTC_ALRMAR_MSK3_Pos (23U)
50	mjames	4647	#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /!< 0x00800000 /
30	mjames	4648	#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
		4649	#define RTC_ALRMAR_PM_Pos (22U)
50	mjames	4650	#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /!< 0x00400000 /
30	mjames	4651	#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
		4652	#define RTC_ALRMAR_HT_Pos (20U)
50	mjames	4653	#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /!< 0x00300000 /
30	mjames	4654	#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
50	mjames	4655	#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /!< 0x00100000 /
		4656	#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /!< 0x00200000 /
30	mjames	4657	#define RTC_ALRMAR_HU_Pos (16U)
50	mjames	4658	#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /!< 0x000F0000 /
30	mjames	4659	#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
50	mjames	4660	#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /!< 0x00010000 /
		4661	#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /!< 0x00020000 /
		4662	#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /!< 0x00040000 /
		4663	#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /!< 0x00080000 /
30	mjames	4664	#define RTC_ALRMAR_MSK2_Pos (15U)
50	mjames	4665	#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /!< 0x00008000 /
30	mjames	4666	#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
		4667	#define RTC_ALRMAR_MNT_Pos (12U)
50	mjames	4668	#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /!< 0x00007000 /
30	mjames	4669	#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
50	mjames	4670	#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /!< 0x00001000 /
		4671	#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /!< 0x00002000 /
		4672	#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /!< 0x00004000 /
30	mjames	4673	#define RTC_ALRMAR_MNU_Pos (8U)
50	mjames	4674	#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /!< 0x00000F00 /
30	mjames	4675	#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
50	mjames	4676	#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /!< 0x00000100 /
		4677	#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /!< 0x00000200 /
		4678	#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /!< 0x00000400 /
		4679	#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /!< 0x00000800 /
30	mjames	4680	#define RTC_ALRMAR_MSK1_Pos (7U)
50	mjames	4681	#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /!< 0x00000080 /
30	mjames	4682	#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
		4683	#define RTC_ALRMAR_ST_Pos (4U)
50	mjames	4684	#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /!< 0x00000070 /
30	mjames	4685	#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
50	mjames	4686	#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /!< 0x00000010 /
		4687	#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /!< 0x00000020 /
		4688	#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /!< 0x00000040 /
30	mjames	4689	#define RTC_ALRMAR_SU_Pos (0U)
50	mjames	4690	#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /!< 0x0000000F /
30	mjames	4691	#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
50	mjames	4692	#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /!< 0x00000001 /
		4693	#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /!< 0x00000002 /
		4694	#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /!< 0x00000004 /
		4695	#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /!< 0x00000008 /
30	mjames	4696
		4697	/****************** Bits definition for RTC_ALRMBR register *************/
		4698	#define RTC_ALRMBR_MSK4_Pos (31U)
50	mjames	4699	#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /!< 0x80000000 /
30	mjames	4700	#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
		4701	#define RTC_ALRMBR_WDSEL_Pos (30U)
50	mjames	4702	#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /!< 0x40000000 /
30	mjames	4703	#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
		4704	#define RTC_ALRMBR_DT_Pos (28U)
50	mjames	4705	#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /!< 0x30000000 /
30	mjames	4706	#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
50	mjames	4707	#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /!< 0x10000000 /
		4708	#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /!< 0x20000000 /
30	mjames	4709	#define RTC_ALRMBR_DU_Pos (24U)
50	mjames	4710	#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /!< 0x0F000000 /
30	mjames	4711	#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
50	mjames	4712	#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /!< 0x01000000 /
		4713	#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /!< 0x02000000 /
		4714	#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /!< 0x04000000 /
		4715	#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /!< 0x08000000 /
30	mjames	4716	#define RTC_ALRMBR_MSK3_Pos (23U)
50	mjames	4717	#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /!< 0x00800000 /
30	mjames	4718	#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
		4719	#define RTC_ALRMBR_PM_Pos (22U)
50	mjames	4720	#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /!< 0x00400000 /
30	mjames	4721	#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
		4722	#define RTC_ALRMBR_HT_Pos (20U)
50	mjames	4723	#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /!< 0x00300000 /
30	mjames	4724	#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
50	mjames	4725	#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /!< 0x00100000 /
		4726	#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /!< 0x00200000 /
30	mjames	4727	#define RTC_ALRMBR_HU_Pos (16U)
50	mjames	4728	#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /!< 0x000F0000 /
30	mjames	4729	#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
50	mjames	4730	#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /!< 0x00010000 /
		4731	#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /!< 0x00020000 /
		4732	#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /!< 0x00040000 /
		4733	#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /!< 0x00080000 /
30	mjames	4734	#define RTC_ALRMBR_MSK2_Pos (15U)
50	mjames	4735	#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /!< 0x00008000 /
30	mjames	4736	#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
		4737	#define RTC_ALRMBR_MNT_Pos (12U)
50	mjames	4738	#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /!< 0x00007000 /
30	mjames	4739	#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
50	mjames	4740	#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /!< 0x00001000 /
		4741	#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /!< 0x00002000 /
		4742	#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /!< 0x00004000 /
30	mjames	4743	#define RTC_ALRMBR_MNU_Pos (8U)
50	mjames	4744	#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /!< 0x00000F00 /
30	mjames	4745	#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
50	mjames	4746	#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /!< 0x00000100 /
		4747	#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /!< 0x00000200 /
		4748	#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /!< 0x00000400 /
		4749	#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /!< 0x00000800 /
30	mjames	4750	#define RTC_ALRMBR_MSK1_Pos (7U)
50	mjames	4751	#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /!< 0x00000080 /
30	mjames	4752	#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
		4753	#define RTC_ALRMBR_ST_Pos (4U)
50	mjames	4754	#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /!< 0x00000070 /
30	mjames	4755	#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
50	mjames	4756	#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /!< 0x00000010 /
		4757	#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /!< 0x00000020 /
		4758	#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /!< 0x00000040 /
30	mjames	4759	#define RTC_ALRMBR_SU_Pos (0U)
50	mjames	4760	#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /!< 0x0000000F /
30	mjames	4761	#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
50	mjames	4762	#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /!< 0x00000001 /
		4763	#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /!< 0x00000002 /
		4764	#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /!< 0x00000004 /
		4765	#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /!< 0x00000008 /
30	mjames	4766
		4767	/****************** Bits definition for RTC_WPR register ****************/
		4768	#define RTC_WPR_KEY_Pos (0U)
50	mjames	4769	#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /!< 0x000000FF /
30	mjames	4770	#define RTC_WPR_KEY RTC_WPR_KEY_Msk
		4771
		4772	/****************** Bits definition for RTC_TSTR register ***************/
		4773	#define RTC_TSTR_PM_Pos (22U)
50	mjames	4774	#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /!< 0x00400000 /
30	mjames	4775	#define RTC_TSTR_PM RTC_TSTR_PM_Msk
		4776	#define RTC_TSTR_HT_Pos (20U)
50	mjames	4777	#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /!< 0x00300000 /
30	mjames	4778	#define RTC_TSTR_HT RTC_TSTR_HT_Msk
50	mjames	4779	#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /!< 0x00100000 /
		4780	#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /!< 0x00200000 /
30	mjames	4781	#define RTC_TSTR_HU_Pos (16U)
50	mjames	4782	#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /!< 0x000F0000 /
30	mjames	4783	#define RTC_TSTR_HU RTC_TSTR_HU_Msk
50	mjames	4784	#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /!< 0x00010000 /
		4785	#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /!< 0x00020000 /
		4786	#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /!< 0x00040000 /
		4787	#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /!< 0x00080000 /
30	mjames	4788	#define RTC_TSTR_MNT_Pos (12U)
50	mjames	4789	#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /!< 0x00007000 /
30	mjames	4790	#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
50	mjames	4791	#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /!< 0x00001000 /
		4792	#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /!< 0x00002000 /
		4793	#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /!< 0x00004000 /
30	mjames	4794	#define RTC_TSTR_MNU_Pos (8U)
50	mjames	4795	#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /!< 0x00000F00 /
30	mjames	4796	#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
50	mjames	4797	#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /!< 0x00000100 /
		4798	#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /!< 0x00000200 /
		4799	#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /!< 0x00000400 /
		4800	#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /!< 0x00000800 /
30	mjames	4801	#define RTC_TSTR_ST_Pos (4U)
50	mjames	4802	#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /!< 0x00000070 /
30	mjames	4803	#define RTC_TSTR_ST RTC_TSTR_ST_Msk
50	mjames	4804	#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /!< 0x00000010 /
		4805	#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /!< 0x00000020 /
		4806	#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /!< 0x00000040 /
30	mjames	4807	#define RTC_TSTR_SU_Pos (0U)
50	mjames	4808	#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /!< 0x0000000F /
30	mjames	4809	#define RTC_TSTR_SU RTC_TSTR_SU_Msk
50	mjames	4810	#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /!< 0x00000001 /
		4811	#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /!< 0x00000002 /
		4812	#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /!< 0x00000004 /
		4813	#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /!< 0x00000008 /
30	mjames	4814
		4815	/****************** Bits definition for RTC_TSDR register ***************/
		4816	#define RTC_TSDR_WDU_Pos (13U)
50	mjames	4817	#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /!< 0x0000E000 /
30	mjames	4818	#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
50	mjames	4819	#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /!< 0x00002000 /
		4820	#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /!< 0x00004000 /
		4821	#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /!< 0x00008000 /
30	mjames	4822	#define RTC_TSDR_MT_Pos (12U)
50	mjames	4823	#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /!< 0x00001000 /
30	mjames	4824	#define RTC_TSDR_MT RTC_TSDR_MT_Msk
		4825	#define RTC_TSDR_MU_Pos (8U)
50	mjames	4826	#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /!< 0x00000F00 /
30	mjames	4827	#define RTC_TSDR_MU RTC_TSDR_MU_Msk
50	mjames	4828	#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /!< 0x00000100 /
		4829	#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /!< 0x00000200 /
		4830	#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /!< 0x00000400 /
		4831	#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /!< 0x00000800 /
30	mjames	4832	#define RTC_TSDR_DT_Pos (4U)
50	mjames	4833	#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /!< 0x00000030 /
30	mjames	4834	#define RTC_TSDR_DT RTC_TSDR_DT_Msk
50	mjames	4835	#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /!< 0x00000010 /
		4836	#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /!< 0x00000020 /
30	mjames	4837	#define RTC_TSDR_DU_Pos (0U)
50	mjames	4838	#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /!< 0x0000000F /
30	mjames	4839	#define RTC_TSDR_DU RTC_TSDR_DU_Msk
50	mjames	4840	#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /!< 0x00000001 /
		4841	#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /!< 0x00000002 /
		4842	#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /!< 0x00000004 /
		4843	#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /!< 0x00000008 /
30	mjames	4844
		4845	/****************** Bits definition for RTC_TAFCR register **************/
		4846	#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
50	mjames	4847	#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /!< 0x00040000 /
30	mjames	4848	#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
		4849	#define RTC_TAFCR_TAMPIE_Pos (2U)
50	mjames	4850	#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /!< 0x00000004 /
30	mjames	4851	#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
		4852	#define RTC_TAFCR_TAMP1TRG_Pos (1U)
50	mjames	4853	#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /!< 0x00000002 /
30	mjames	4854	#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
		4855	#define RTC_TAFCR_TAMP1E_Pos (0U)
50	mjames	4856	#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /!< 0x00000001 /
30	mjames	4857	#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
		4858
		4859	/****************** Bits definition for RTC_BKP0R register **************/
		4860	#define RTC_BKP0R_Pos (0U)
50	mjames	4861	#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /!< 0xFFFFFFFF /
30	mjames	4862	#define RTC_BKP0R RTC_BKP0R_Msk
		4863
		4864	/****************** Bits definition for RTC_BKP1R register **************/
		4865	#define RTC_BKP1R_Pos (0U)
50	mjames	4866	#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /!< 0xFFFFFFFF /
30	mjames	4867	#define RTC_BKP1R RTC_BKP1R_Msk
		4868
		4869	/****************** Bits definition for RTC_BKP2R register **************/
		4870	#define RTC_BKP2R_Pos (0U)
50	mjames	4871	#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /!< 0xFFFFFFFF /
30	mjames	4872	#define RTC_BKP2R RTC_BKP2R_Msk
		4873
		4874	/****************** Bits definition for RTC_BKP3R register **************/
		4875	#define RTC_BKP3R_Pos (0U)
50	mjames	4876	#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /!< 0xFFFFFFFF /
30	mjames	4877	#define RTC_BKP3R RTC_BKP3R_Msk
		4878
		4879	/****************** Bits definition for RTC_BKP4R register **************/
		4880	#define RTC_BKP4R_Pos (0U)
50	mjames	4881	#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /!< 0xFFFFFFFF /
30	mjames	4882	#define RTC_BKP4R RTC_BKP4R_Msk
		4883
		4884	/****************** Bits definition for RTC_BKP5R register **************/
		4885	#define RTC_BKP5R_Pos (0U)
50	mjames	4886	#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /!< 0xFFFFFFFF /
30	mjames	4887	#define RTC_BKP5R RTC_BKP5R_Msk
		4888
		4889	/****************** Bits definition for RTC_BKP6R register **************/
		4890	#define RTC_BKP6R_Pos (0U)
50	mjames	4891	#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /!< 0xFFFFFFFF /
30	mjames	4892	#define RTC_BKP6R RTC_BKP6R_Msk
		4893
		4894	/****************** Bits definition for RTC_BKP7R register **************/
		4895	#define RTC_BKP7R_Pos (0U)
50	mjames	4896	#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /!< 0xFFFFFFFF /
30	mjames	4897	#define RTC_BKP7R RTC_BKP7R_Msk
		4898
		4899	/****************** Bits definition for RTC_BKP8R register **************/
		4900	#define RTC_BKP8R_Pos (0U)
50	mjames	4901	#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /!< 0xFFFFFFFF /
30	mjames	4902	#define RTC_BKP8R RTC_BKP8R_Msk
		4903
		4904	/****************** Bits definition for RTC_BKP9R register **************/
		4905	#define RTC_BKP9R_Pos (0U)
50	mjames	4906	#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /!< 0xFFFFFFFF /
30	mjames	4907	#define RTC_BKP9R RTC_BKP9R_Msk
		4908
		4909	/****************** Bits definition for RTC_BKP10R register *************/
		4910	#define RTC_BKP10R_Pos (0U)
50	mjames	4911	#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /!< 0xFFFFFFFF /
30	mjames	4912	#define RTC_BKP10R RTC_BKP10R_Msk
		4913
		4914	/****************** Bits definition for RTC_BKP11R register *************/
		4915	#define RTC_BKP11R_Pos (0U)
50	mjames	4916	#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /!< 0xFFFFFFFF /
30	mjames	4917	#define RTC_BKP11R RTC_BKP11R_Msk
		4918
		4919	/****************** Bits definition for RTC_BKP12R register *************/
		4920	#define RTC_BKP12R_Pos (0U)
50	mjames	4921	#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /!< 0xFFFFFFFF /
30	mjames	4922	#define RTC_BKP12R RTC_BKP12R_Msk
		4923
		4924	/****************** Bits definition for RTC_BKP13R register *************/
		4925	#define RTC_BKP13R_Pos (0U)
50	mjames	4926	#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /!< 0xFFFFFFFF /
30	mjames	4927	#define RTC_BKP13R RTC_BKP13R_Msk
		4928
		4929	/****************** Bits definition for RTC_BKP14R register *************/
		4930	#define RTC_BKP14R_Pos (0U)
50	mjames	4931	#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /!< 0xFFFFFFFF /
30	mjames	4932	#define RTC_BKP14R RTC_BKP14R_Msk
		4933
		4934	/****************** Bits definition for RTC_BKP15R register *************/
		4935	#define RTC_BKP15R_Pos (0U)
50	mjames	4936	#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /!< 0xFFFFFFFF /
30	mjames	4937	#define RTC_BKP15R RTC_BKP15R_Msk
		4938
		4939	/****************** Bits definition for RTC_BKP16R register *************/
		4940	#define RTC_BKP16R_Pos (0U)
50	mjames	4941	#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /!< 0xFFFFFFFF /
30	mjames	4942	#define RTC_BKP16R RTC_BKP16R_Msk
		4943
		4944	/****************** Bits definition for RTC_BKP17R register *************/
		4945	#define RTC_BKP17R_Pos (0U)
50	mjames	4946	#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /!< 0xFFFFFFFF /
30	mjames	4947	#define RTC_BKP17R RTC_BKP17R_Msk
		4948
		4949	/****************** Bits definition for RTC_BKP18R register *************/
		4950	#define RTC_BKP18R_Pos (0U)
50	mjames	4951	#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /!< 0xFFFFFFFF /
30	mjames	4952	#define RTC_BKP18R RTC_BKP18R_Msk
		4953
		4954	/****************** Bits definition for RTC_BKP19R register *************/
		4955	#define RTC_BKP19R_Pos (0U)
50	mjames	4956	#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /!< 0xFFFFFFFF /
30	mjames	4957	#define RTC_BKP19R RTC_BKP19R_Msk
		4958
		4959	/****************** Number of backup registers ****************************/
		4960	#define RTC_BKP_NUMBER 20
		4961
		4962	/******************************************************************************/
		4963	/* */
		4964	/* Serial Peripheral Interface (SPI) */
		4965	/* */
		4966	/******************************************************************************/
		4967
		4968	/*
		4969	* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
		4970	*/
		4971
		4972	/***************** Bit definition for SPI_CR1 register ******************/
		4973	#define SPI_CR1_CPHA_Pos (0U)
50	mjames	4974	#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /!< 0x00000001 /
30	mjames	4975	#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /!< Clock Phase /
		4976	#define SPI_CR1_CPOL_Pos (1U)
50	mjames	4977	#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /!< 0x00000002 /
30	mjames	4978	#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /!< Clock Polarity /
		4979	#define SPI_CR1_MSTR_Pos (2U)
50	mjames	4980	#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /!< 0x00000004 /
30	mjames	4981	#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /!< Master Selection /
		4982
		4983	#define SPI_CR1_BR_Pos (3U)
50	mjames	4984	#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /!< 0x00000038 /
30	mjames	4985	#define SPI_CR1_BR SPI_CR1_BR_Msk /!< BR[2:0] bits (Baud Rate Control) /
50	mjames	4986	#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /!< 0x00000008 /
		4987	#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /!< 0x00000010 /
		4988	#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /!< 0x00000020 /
30	mjames	4989
		4990	#define SPI_CR1_SPE_Pos (6U)
50	mjames	4991	#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /!< 0x00000040 /
30	mjames	4992	#define SPI_CR1_SPE SPI_CR1_SPE_Msk /!< SPI Enable /
		4993	#define SPI_CR1_LSBFIRST_Pos (7U)
50	mjames	4994	#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /!< 0x00000080 /
30	mjames	4995	#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /!< Frame Format /
		4996	#define SPI_CR1_SSI_Pos (8U)
50	mjames	4997	#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /!< 0x00000100 /
30	mjames	4998	#define SPI_CR1_SSI SPI_CR1_SSI_Msk /!< Internal slave select /
		4999	#define SPI_CR1_SSM_Pos (9U)
50	mjames	5000	#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /!< 0x00000200 /
30	mjames	5001	#define SPI_CR1_SSM SPI_CR1_SSM_Msk /!< Software slave management /
		5002	#define SPI_CR1_RXONLY_Pos (10U)
50	mjames	5003	#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /!< 0x00000400 /
30	mjames	5004	#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /!< Receive only /
		5005	#define SPI_CR1_DFF_Pos (11U)
50	mjames	5006	#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /!< 0x00000800 /
30	mjames	5007	#define SPI_CR1_DFF SPI_CR1_DFF_Msk /!< Data Frame Format /
		5008	#define SPI_CR1_CRCNEXT_Pos (12U)
50	mjames	5009	#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /!< 0x00001000 /
30	mjames	5010	#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /!< Transmit CRC next /
		5011	#define SPI_CR1_CRCEN_Pos (13U)
50	mjames	5012	#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /!< 0x00002000 /
30	mjames	5013	#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /!< Hardware CRC calculation enable /
		5014	#define SPI_CR1_BIDIOE_Pos (14U)
50	mjames	5015	#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /!< 0x00004000 /
30	mjames	5016	#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /!< Output enable in bidirectional mode /
		5017	#define SPI_CR1_BIDIMODE_Pos (15U)
50	mjames	5018	#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /!< 0x00008000 /
30	mjames	5019	#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /!< Bidirectional data mode enable /
		5020
		5021	/***************** Bit definition for SPI_CR2 register ******************/
		5022	#define SPI_CR2_RXDMAEN_Pos (0U)
50	mjames	5023	#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /!< 0x00000001 /
30	mjames	5024	#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /!< Rx Buffer DMA Enable /
		5025	#define SPI_CR2_TXDMAEN_Pos (1U)
50	mjames	5026	#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /!< 0x00000002 /
30	mjames	5027	#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /!< Tx Buffer DMA Enable /
		5028	#define SPI_CR2_SSOE_Pos (2U)
50	mjames	5029	#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /!< 0x00000004 /
30	mjames	5030	#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /!< SS Output Enable /
		5031	#define SPI_CR2_ERRIE_Pos (5U)
50	mjames	5032	#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /!< 0x00000020 /
30	mjames	5033	#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /!< Error Interrupt Enable /
		5034	#define SPI_CR2_RXNEIE_Pos (6U)
50	mjames	5035	#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /!< 0x00000040 /
30	mjames	5036	#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /!< RX buffer Not Empty Interrupt Enable /
		5037	#define SPI_CR2_TXEIE_Pos (7U)
50	mjames	5038	#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /!< 0x00000080 /
30	mjames	5039	#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /!< Tx buffer Empty Interrupt Enable /
		5040
		5041	/****************** Bit definition for SPI_SR register ******************/
		5042	#define SPI_SR_RXNE_Pos (0U)
50	mjames	5043	#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /!< 0x00000001 /
30	mjames	5044	#define SPI_SR_RXNE SPI_SR_RXNE_Msk /!< Receive buffer Not Empty /
		5045	#define SPI_SR_TXE_Pos (1U)
50	mjames	5046	#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /!< 0x00000002 /
30	mjames	5047	#define SPI_SR_TXE SPI_SR_TXE_Msk /!< Transmit buffer Empty /
		5048	#define SPI_SR_CHSIDE_Pos (2U)
50	mjames	5049	#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /!< 0x00000004 /
30	mjames	5050	#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /!< Channel side /
		5051	#define SPI_SR_UDR_Pos (3U)
50	mjames	5052	#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /!< 0x00000008 /
30	mjames	5053	#define SPI_SR_UDR SPI_SR_UDR_Msk /!< Underrun flag /
		5054	#define SPI_SR_CRCERR_Pos (4U)
50	mjames	5055	#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /!< 0x00000010 /
30	mjames	5056	#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /!< CRC Error flag /
		5057	#define SPI_SR_MODF_Pos (5U)
50	mjames	5058	#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /!< 0x00000020 /
30	mjames	5059	#define SPI_SR_MODF SPI_SR_MODF_Msk /!< Mode fault /
		5060	#define SPI_SR_OVR_Pos (6U)
50	mjames	5061	#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /!< 0x00000040 /
30	mjames	5062	#define SPI_SR_OVR SPI_SR_OVR_Msk /!< Overrun flag /
		5063	#define SPI_SR_BSY_Pos (7U)
50	mjames	5064	#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /!< 0x00000080 /
30	mjames	5065	#define SPI_SR_BSY SPI_SR_BSY_Msk /!< Busy flag /
		5066	#define SPI_SR_FRE_Pos (8U)
50	mjames	5067	#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /!< 0x00000100 /
30	mjames	5068	#define SPI_SR_FRE SPI_SR_FRE_Msk /!<Frame format error flag /
		5069
		5070	/****************** Bit definition for SPI_DR register ******************/
		5071	#define SPI_DR_DR_Pos (0U)
50	mjames	5072	#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /!< 0x0000FFFF /
30	mjames	5073	#define SPI_DR_DR SPI_DR_DR_Msk /!< Data Register /
		5074
		5075	/***************** Bit definition for SPI_CRCPR register ****************/
		5076	#define SPI_CRCPR_CRCPOLY_Pos (0U)
50	mjames	5077	#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /!< 0x0000FFFF /
30	mjames	5078	#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /!< CRC polynomial register /
		5079
		5080	/**************** Bit definition for SPI_RXCRCR register ****************/
		5081	#define SPI_RXCRCR_RXCRC_Pos (0U)
50	mjames	5082	#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /!< 0x0000FFFF /
30	mjames	5083	#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /!< Rx CRC Register /
		5084
		5085	/**************** Bit definition for SPI_TXCRCR register ****************/
		5086	#define SPI_TXCRCR_TXCRC_Pos (0U)
50	mjames	5087	#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /!< 0x0000FFFF /
30	mjames	5088	#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /!< Tx CRC Register /
		5089
		5090	/******************************************************************************/
		5091	/* */
		5092	/* System Configuration (SYSCFG) */
		5093	/* */
		5094	/******************************************************************************/
		5095	/*************** Bit definition for SYSCFG_MEMRMP register **************/
		5096	#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
50	mjames	5097	#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /!< 0x00000003 /
30	mjames	5098	#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /!< SYSCFG_Memory Remap Config /
50	mjames	5099	#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /!< 0x00000001 /
		5100	#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /!< 0x00000002 /
30	mjames	5101	#define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U)
50	mjames	5102	#define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /!< 0x00000300 /
30	mjames	5103	#define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /!< Boot mode Config /
50	mjames	5104	#define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /!< 0x00000100 /
		5105	#define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /!< 0x00000200 /
30	mjames	5106
		5107	/*************** Bit definition for SYSCFG_PMC register *****************/
		5108	#define SYSCFG_PMC_USB_PU_Pos (0U)
50	mjames	5109	#define SYSCFG_PMC_USB_PU_Msk (0x1UL << SYSCFG_PMC_USB_PU_Pos) /!< 0x00000001 /
30	mjames	5110	#define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /!< SYSCFG PMC /
		5111
		5112	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
		5113	#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
50	mjames	5114	#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /!< 0x0000000F /
30	mjames	5115	#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /!< EXTI 0 configuration /
		5116	#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
50	mjames	5117	#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /!< 0x000000F0 /
30	mjames	5118	#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /!< EXTI 1 configuration /
		5119	#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
50	mjames	5120	#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /!< 0x00000F00 /
30	mjames	5121	#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /!< EXTI 2 configuration /
		5122	#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
50	mjames	5123	#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /!< 0x0000F000 /
30	mjames	5124	#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /!< EXTI 3 configuration /
		5125
		5126	/**
		5127	* @brief EXTI0 configuration
		5128	*/
		5129	#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /!< PA[0] pin /
		5130	#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /!< PB[0] pin /
		5131	#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /!< PC[0] pin /
		5132	#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /!< PD[0] pin /
		5133	#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /!< PE[0] pin /
		5134	#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /!< PH[0] pin /
		5135
		5136	/**
		5137	* @brief EXTI1 configuration
		5138	*/
		5139	#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /!< PA[1] pin /
		5140	#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /!< PB[1] pin /
		5141	#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /!< PC[1] pin /
		5142	#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /!< PD[1] pin /
		5143	#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /!< PE[1] pin /
		5144	#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /!< PH[1] pin /
		5145
		5146	/**
		5147	* @brief EXTI2 configuration
		5148	*/
		5149	#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /!< PA[2] pin /
		5150	#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /!< PB[2] pin /
		5151	#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /!< PC[2] pin /
		5152	#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /!< PD[2] pin /
		5153	#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /!< PE[2] pin /
		5154	#define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /!< PH[2] pin /
		5155
		5156	/**
		5157	* @brief EXTI3 configuration
		5158	*/
		5159	#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /!< PA[3] pin /
		5160	#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /!< PB[3] pin /
		5161	#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /!< PC[3] pin /
		5162	#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /!< PD[3] pin /
		5163	#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /!< PE[3] pin /
		5164
		5165	/*************** Bit definition for SYSCFG_EXTICR2 register ***************/
		5166	#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
50	mjames	5167	#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /!< 0x0000000F /
30	mjames	5168	#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /!< EXTI 4 configuration /
		5169	#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
50	mjames	5170	#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /!< 0x000000F0 /
30	mjames	5171	#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /!< EXTI 5 configuration /
		5172	#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
50	mjames	5173	#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /!< 0x00000F00 /
30	mjames	5174	#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /!< EXTI 6 configuration /
		5175	#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
50	mjames	5176	#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /!< 0x0000F000 /
30	mjames	5177	#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /!< EXTI 7 configuration /
		5178
		5179	/**
		5180	* @brief EXTI4 configuration
		5181	*/
		5182	#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /!< PA[4] pin /
		5183	#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /!< PB[4] pin /
		5184	#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /!< PC[4] pin /
		5185	#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /!< PD[4] pin /
		5186	#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /!< PE[4] pin /
		5187
		5188	/**
		5189	* @brief EXTI5 configuration
		5190	*/
		5191	#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /!< PA[5] pin /
		5192	#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /!< PB[5] pin /
		5193	#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /!< PC[5] pin /
		5194	#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /!< PD[5] pin /
		5195	#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /!< PE[5] pin /
		5196
		5197	/**
		5198	* @brief EXTI6 configuration
		5199	*/
		5200	#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /!< PA[6] pin /
		5201	#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /!< PB[6] pin /
		5202	#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /!< PC[6] pin /
		5203	#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /!< PD[6] pin /
		5204	#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /!< PE[6] pin /
		5205
		5206	/**
		5207	* @brief EXTI7 configuration
		5208	*/
		5209	#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /!< PA[7] pin /
		5210	#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /!< PB[7] pin /
		5211	#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /!< PC[7] pin /
		5212	#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /!< PD[7] pin /
		5213	#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /!< PE[7] pin /
		5214
		5215	/*************** Bit definition for SYSCFG_EXTICR3 register ***************/
		5216	#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
50	mjames	5217	#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /!< 0x0000000F /
30	mjames	5218	#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /!< EXTI 8 configuration /
		5219	#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
50	mjames	5220	#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /!< 0x000000F0 /
30	mjames	5221	#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /!< EXTI 9 configuration /
		5222	#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
50	mjames	5223	#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /!< 0x00000F00 /
30	mjames	5224	#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /!< EXTI 10 configuration /
		5225	#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
50	mjames	5226	#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /!< 0x0000F000 /
30	mjames	5227	#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /!< EXTI 11 configuration /
		5228
		5229	/**
		5230	* @brief EXTI8 configuration
		5231	*/
		5232	#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /!< PA[8] pin /
		5233	#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /!< PB[8] pin /
		5234	#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /!< PC[8] pin /
		5235	#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /!< PD[8] pin /
		5236	#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /!< PE[8] pin /
		5237
		5238	/**
		5239	* @brief EXTI9 configuration
		5240	*/
		5241	#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /!< PA[9] pin /
		5242	#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /!< PB[9] pin /
		5243	#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /!< PC[9] pin /
		5244	#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /!< PD[9] pin /
		5245	#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /!< PE[9] pin /
		5246
		5247	/**
		5248	* @brief EXTI10 configuration
		5249	*/
		5250	#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /!< PA[10] pin /
		5251	#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /!< PB[10] pin /
		5252	#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /!< PC[10] pin /
		5253	#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /!< PD[10] pin /
		5254	#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /!< PE[10] pin /
		5255
		5256	/**
		5257	* @brief EXTI11 configuration
		5258	*/
		5259	#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /!< PA[11] pin /
		5260	#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /!< PB[11] pin /
		5261	#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /!< PC[11] pin /
		5262	#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /!< PD[11] pin /
		5263	#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /!< PE[11] pin /
		5264
		5265	/*************** Bit definition for SYSCFG_EXTICR4 register ***************/
		5266	#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
50	mjames	5267	#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /!< 0x0000000F /
30	mjames	5268	#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /!< EXTI 12 configuration /
		5269	#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
50	mjames	5270	#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /!< 0x000000F0 /
30	mjames	5271	#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /!< EXTI 13 configuration /
		5272	#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
50	mjames	5273	#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /!< 0x00000F00 /
30	mjames	5274	#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /!< EXTI 14 configuration /
		5275	#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
50	mjames	5276	#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /!< 0x0000F000 /
30	mjames	5277	#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /!< EXTI 15 configuration /
		5278
		5279	/**
		5280	* @brief EXTI12 configuration
		5281	*/
		5282	#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /!< PA[12] pin /
		5283	#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /!< PB[12] pin /
		5284	#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /!< PC[12] pin /
		5285	#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /!< PD[12] pin /
		5286	#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /!< PE[12] pin /
		5287
		5288	/**
		5289	* @brief EXTI13 configuration
		5290	*/
		5291	#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /!< PA[13] pin /
		5292	#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /!< PB[13] pin /
		5293	#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /!< PC[13] pin /
		5294	#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /!< PD[13] pin /
		5295	#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /!< PE[13] pin /
		5296
		5297	/**
		5298	* @brief EXTI14 configuration
		5299	*/
		5300	#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /!< PA[14] pin /
		5301	#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /!< PB[14] pin /
		5302	#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /!< PC[14] pin /
		5303	#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /!< PD[14] pin /
		5304	#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /!< PE[14] pin /
		5305
		5306	/**
		5307	* @brief EXTI15 configuration
		5308	*/
		5309	#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /!< PA[15] pin /
		5310	#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /!< PB[15] pin /
		5311	#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /!< PC[15] pin /
		5312	#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /!< PD[15] pin /
		5313	#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /!< PE[15] pin /
61	mjames	5314
30	mjames	5315	/******************************************************************************/
		5316	/* */
		5317	/* Routing Interface (RI) */
		5318	/* */
		5319	/******************************************************************************/
		5320
		5321	/****************** Bit definition for RI_ICR register ******************/
		5322	#define RI_ICR_IC1OS_Pos (0U)
50	mjames	5323	#define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /!< 0x0000000F /
30	mjames	5324	#define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /!< IC1OS[3:0] bits (Input Capture 1 select bits) /
50	mjames	5325	#define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /!< 0x00000001 /
		5326	#define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /!< 0x00000002 /
		5327	#define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /!< 0x00000004 /
		5328	#define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /!< 0x00000008 /
30	mjames	5329
		5330	#define RI_ICR_IC2OS_Pos (4U)
50	mjames	5331	#define RI_ICR_IC2OS_Msk (0xFUL << RI_ICR_IC2OS_Pos) /!< 0x000000F0 /
30	mjames	5332	#define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /!< IC2OS[3:0] bits (Input Capture 2 select bits) /
50	mjames	5333	#define RI_ICR_IC2OS_0 (0x1UL << RI_ICR_IC2OS_Pos) /!< 0x00000010 /
		5334	#define RI_ICR_IC2OS_1 (0x2UL << RI_ICR_IC2OS_Pos) /!< 0x00000020 /
		5335	#define RI_ICR_IC2OS_2 (0x4UL << RI_ICR_IC2OS_Pos) /!< 0x00000040 /
		5336	#define RI_ICR_IC2OS_3 (0x8UL << RI_ICR_IC2OS_Pos) /!< 0x00000080 /
30	mjames	5337
		5338	#define RI_ICR_IC3OS_Pos (8U)
50	mjames	5339	#define RI_ICR_IC3OS_Msk (0xFUL << RI_ICR_IC3OS_Pos) /!< 0x00000F00 /
30	mjames	5340	#define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /!< IC3OS[3:0] bits (Input Capture 3 select bits) /
50	mjames	5341	#define RI_ICR_IC3OS_0 (0x1UL << RI_ICR_IC3OS_Pos) /!< 0x00000100 /
		5342	#define RI_ICR_IC3OS_1 (0x2UL << RI_ICR_IC3OS_Pos) /!< 0x00000200 /
		5343	#define RI_ICR_IC3OS_2 (0x4UL << RI_ICR_IC3OS_Pos) /!< 0x00000400 /
		5344	#define RI_ICR_IC3OS_3 (0x8UL << RI_ICR_IC3OS_Pos) /!< 0x00000800 /
30	mjames	5345
		5346	#define RI_ICR_IC4OS_Pos (12U)
50	mjames	5347	#define RI_ICR_IC4OS_Msk (0xFUL << RI_ICR_IC4OS_Pos) /!< 0x0000F000 /
30	mjames	5348	#define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /!< IC4OS[3:0] bits (Input Capture 4 select bits) /
50	mjames	5349	#define RI_ICR_IC4OS_0 (0x1UL << RI_ICR_IC4OS_Pos) /!< 0x00001000 /
		5350	#define RI_ICR_IC4OS_1 (0x2UL << RI_ICR_IC4OS_Pos) /!< 0x00002000 /
		5351	#define RI_ICR_IC4OS_2 (0x4UL << RI_ICR_IC4OS_Pos) /!< 0x00004000 /
		5352	#define RI_ICR_IC4OS_3 (0x8UL << RI_ICR_IC4OS_Pos) /!< 0x00008000 /
30	mjames	5353
		5354	#define RI_ICR_TIM_Pos (16U)
50	mjames	5355	#define RI_ICR_TIM_Msk (0x3UL << RI_ICR_TIM_Pos) /!< 0x00030000 /
30	mjames	5356	#define RI_ICR_TIM RI_ICR_TIM_Msk /!< TIM[3:0] bits (Timers select bits) /
50	mjames	5357	#define RI_ICR_TIM_0 (0x1UL << RI_ICR_TIM_Pos) /!< 0x00010000 /
		5358	#define RI_ICR_TIM_1 (0x2UL << RI_ICR_TIM_Pos) /!< 0x00020000 /
30	mjames	5359
		5360	#define RI_ICR_IC1_Pos (18U)
50	mjames	5361	#define RI_ICR_IC1_Msk (0x1UL << RI_ICR_IC1_Pos) /!< 0x00040000 /
30	mjames	5362	#define RI_ICR_IC1 RI_ICR_IC1_Msk /!< Input capture 1 /
		5363	#define RI_ICR_IC2_Pos (19U)
50	mjames	5364	#define RI_ICR_IC2_Msk (0x1UL << RI_ICR_IC2_Pos) /!< 0x00080000 /
30	mjames	5365	#define RI_ICR_IC2 RI_ICR_IC2_Msk /!< Input capture 2 /
		5366	#define RI_ICR_IC3_Pos (20U)
50	mjames	5367	#define RI_ICR_IC3_Msk (0x1UL << RI_ICR_IC3_Pos) /!< 0x00100000 /
30	mjames	5368	#define RI_ICR_IC3 RI_ICR_IC3_Msk /!< Input capture 3 /
		5369	#define RI_ICR_IC4_Pos (21U)
50	mjames	5370	#define RI_ICR_IC4_Msk (0x1UL << RI_ICR_IC4_Pos) /!< 0x00200000 /
30	mjames	5371	#define RI_ICR_IC4 RI_ICR_IC4_Msk /!< Input capture 4 /
		5372
		5373	/****************** Bit definition for RI_ASCR1 register ******************/
		5374	#define RI_ASCR1_CH_Pos (0U)
50	mjames	5375	#define RI_ASCR1_CH_Msk (0x3FCFFFFUL << RI_ASCR1_CH_Pos) /!< 0x03FCFFFF /
30	mjames	5376	#define RI_ASCR1_CH RI_ASCR1_CH_Msk /!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) /
		5377	#define RI_ASCR1_CH_0 (0x00000001U) /!< Bit 0 /
		5378	#define RI_ASCR1_CH_1 (0x00000002U) /!< Bit 1 /
		5379	#define RI_ASCR1_CH_2 (0x00000004U) /!< Bit 2 /
		5380	#define RI_ASCR1_CH_3 (0x00000008U) /!< Bit 3 /
		5381	#define RI_ASCR1_CH_4 (0x00000010U) /!< Bit 4 /
		5382	#define RI_ASCR1_CH_5 (0x00000020U) /!< Bit 5 /
		5383	#define RI_ASCR1_CH_6 (0x00000040U) /!< Bit 6 /
		5384	#define RI_ASCR1_CH_7 (0x00000080U) /!< Bit 7 /
		5385	#define RI_ASCR1_CH_8 (0x00000100U) /!< Bit 8 /
		5386	#define RI_ASCR1_CH_9 (0x00000200U) /!< Bit 9 /
		5387	#define RI_ASCR1_CH_10 (0x00000400U) /!< Bit 10 /
		5388	#define RI_ASCR1_CH_11 (0x00000800U) /!< Bit 11 /
		5389	#define RI_ASCR1_CH_12 (0x00001000U) /!< Bit 12 /
		5390	#define RI_ASCR1_CH_13 (0x00002000U) /!< Bit 13 /
		5391	#define RI_ASCR1_CH_14 (0x00004000U) /!< Bit 14 /
		5392	#define RI_ASCR1_CH_15 (0x00008000U) /!< Bit 15 /
		5393	#define RI_ASCR1_CH_18 (0x00040000U) /!< Bit 18 /
		5394	#define RI_ASCR1_CH_19 (0x00080000U) /!< Bit 19 /
		5395	#define RI_ASCR1_CH_20 (0x00100000U) /!< Bit 20 /
		5396	#define RI_ASCR1_CH_21 (0x00200000U) /!< Bit 21 /
		5397	#define RI_ASCR1_CH_22 (0x00400000U) /!< Bit 22 /
		5398	#define RI_ASCR1_CH_23 (0x00800000U) /!< Bit 23 /
		5399	#define RI_ASCR1_CH_24 (0x01000000U) /!< Bit 24 /
		5400	#define RI_ASCR1_CH_25 (0x02000000U) /!< Bit 25 /
		5401	#define RI_ASCR1_VCOMP_Pos (26U)
50	mjames	5402	#define RI_ASCR1_VCOMP_Msk (0x1UL << RI_ASCR1_VCOMP_Pos) /!< 0x04000000 /
30	mjames	5403	#define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /!< ADC analog switch selection for internal node to COMP1 /
		5404	#define RI_ASCR1_SCM_Pos (31U)
50	mjames	5405	#define RI_ASCR1_SCM_Msk (0x1UL << RI_ASCR1_SCM_Pos) /!< 0x80000000 /
30	mjames	5406	#define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /!< I/O Switch control mode /
		5407
		5408	/****************** Bit definition for RI_ASCR2 register ******************/
		5409	#define RI_ASCR2_GR10_1 (0x00000001U) /!< GR10-1 selection bit /
		5410	#define RI_ASCR2_GR10_2 (0x00000002U) /!< GR10-2 selection bit /
		5411	#define RI_ASCR2_GR10_3 (0x00000004U) /!< GR10-3 selection bit /
		5412	#define RI_ASCR2_GR10_4 (0x00000008U) /!< GR10-4 selection bit /
		5413	#define RI_ASCR2_GR6_Pos (4U)
50	mjames	5414	#define RI_ASCR2_GR6_Msk (0x3UL << RI_ASCR2_GR6_Pos) /!< 0x00000030 /
30	mjames	5415	#define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /!< GR6 selection bits /
50	mjames	5416	#define RI_ASCR2_GR6_1 (0x1UL << RI_ASCR2_GR6_Pos) /!< 0x00000010 /
		5417	#define RI_ASCR2_GR6_2 (0x2UL << RI_ASCR2_GR6_Pos) /!< 0x00000020 /
30	mjames	5418	#define RI_ASCR2_GR5_1 (0x00000040U) /!< GR5-1 selection bit /
		5419	#define RI_ASCR2_GR5_2 (0x00000080U) /!< GR5-2 selection bit /
		5420	#define RI_ASCR2_GR5_3 (0x00000100U) /!< GR5-3 selection bit /
		5421	#define RI_ASCR2_GR4_1 (0x00000200U) /!< GR4-1 selection bit /
		5422	#define RI_ASCR2_GR4_2 (0x00000400U) /!< GR4-2 selection bit /
		5423	#define RI_ASCR2_GR4_3 (0x00000800U) /!< GR4-3 selection bit /
		5424	#define RI_ASCR2_GR4_4 (0x00008000U) /!< GR4-4 selection bit /
		5425
		5426	/****************** Bit definition for RI_HYSCR1 register ******************/
		5427	#define RI_HYSCR1_PA_Pos (0U)
50	mjames	5428	#define RI_HYSCR1_PA_Msk (0xFFFFUL << RI_HYSCR1_PA_Pos) /!< 0x0000FFFF /
30	mjames	5429	#define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /!< PA[15:0] Port A Hysteresis selection /
50	mjames	5430	#define RI_HYSCR1_PA_0 (0x0001UL << RI_HYSCR1_PA_Pos) /!< 0x00000001 /
		5431	#define RI_HYSCR1_PA_1 (0x0002UL << RI_HYSCR1_PA_Pos) /!< 0x00000002 /
		5432	#define RI_HYSCR1_PA_2 (0x0004UL << RI_HYSCR1_PA_Pos) /!< 0x00000004 /
		5433	#define RI_HYSCR1_PA_3 (0x0008UL << RI_HYSCR1_PA_Pos) /!< 0x00000008 /
		5434	#define RI_HYSCR1_PA_4 (0x0010UL << RI_HYSCR1_PA_Pos) /!< 0x00000010 /
		5435	#define RI_HYSCR1_PA_5 (0x0020UL << RI_HYSCR1_PA_Pos) /!< 0x00000020 /
		5436	#define RI_HYSCR1_PA_6 (0x0040UL << RI_HYSCR1_PA_Pos) /!< 0x00000040 /
		5437	#define RI_HYSCR1_PA_7 (0x0080UL << RI_HYSCR1_PA_Pos) /!< 0x00000080 /
		5438	#define RI_HYSCR1_PA_8 (0x0100UL << RI_HYSCR1_PA_Pos) /!< 0x00000100 /
		5439	#define RI_HYSCR1_PA_9 (0x0200UL << RI_HYSCR1_PA_Pos) /!< 0x00000200 /
		5440	#define RI_HYSCR1_PA_10 (0x0400UL << RI_HYSCR1_PA_Pos) /!< 0x00000400 /
		5441	#define RI_HYSCR1_PA_11 (0x0800UL << RI_HYSCR1_PA_Pos) /!< 0x00000800 /
		5442	#define RI_HYSCR1_PA_12 (0x1000UL << RI_HYSCR1_PA_Pos) /!< 0x00001000 /
		5443	#define RI_HYSCR1_PA_13 (0x2000UL << RI_HYSCR1_PA_Pos) /!< 0x00002000 /
		5444	#define RI_HYSCR1_PA_14 (0x4000UL << RI_HYSCR1_PA_Pos) /!< 0x00004000 /
		5445	#define RI_HYSCR1_PA_15 (0x8000UL << RI_HYSCR1_PA_Pos) /!< 0x00008000 /
30	mjames	5446
		5447	#define RI_HYSCR1_PB_Pos (16U)
50	mjames	5448	#define RI_HYSCR1_PB_Msk (0xFFFFUL << RI_HYSCR1_PB_Pos) /!< 0xFFFF0000 /
30	mjames	5449	#define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /!< PB[15:0] Port B Hysteresis selection /
50	mjames	5450	#define RI_HYSCR1_PB_0 (0x0001UL << RI_HYSCR1_PB_Pos) /!< 0x00010000 /
		5451	#define RI_HYSCR1_PB_1 (0x0002UL << RI_HYSCR1_PB_Pos) /!< 0x00020000 /
		5452	#define RI_HYSCR1_PB_2 (0x0004UL << RI_HYSCR1_PB_Pos) /!< 0x00040000 /
		5453	#define RI_HYSCR1_PB_3 (0x0008UL << RI_HYSCR1_PB_Pos) /!< 0x00080000 /
		5454	#define RI_HYSCR1_PB_4 (0x0010UL << RI_HYSCR1_PB_Pos) /!< 0x00100000 /
		5455	#define RI_HYSCR1_PB_5 (0x0020UL << RI_HYSCR1_PB_Pos) /!< 0x00200000 /
		5456	#define RI_HYSCR1_PB_6 (0x0040UL << RI_HYSCR1_PB_Pos) /!< 0x00400000 /
		5457	#define RI_HYSCR1_PB_7 (0x0080UL << RI_HYSCR1_PB_Pos) /!< 0x00800000 /
		5458	#define RI_HYSCR1_PB_8 (0x0100UL << RI_HYSCR1_PB_Pos) /!< 0x01000000 /
		5459	#define RI_HYSCR1_PB_9 (0x0200UL << RI_HYSCR1_PB_Pos) /!< 0x02000000 /
		5460	#define RI_HYSCR1_PB_10 (0x0400UL << RI_HYSCR1_PB_Pos) /!< 0x04000000 /
		5461	#define RI_HYSCR1_PB_11 (0x0800UL << RI_HYSCR1_PB_Pos) /!< 0x08000000 /
		5462	#define RI_HYSCR1_PB_12 (0x1000UL << RI_HYSCR1_PB_Pos) /!< 0x10000000 /
		5463	#define RI_HYSCR1_PB_13 (0x2000UL << RI_HYSCR1_PB_Pos) /!< 0x20000000 /
		5464	#define RI_HYSCR1_PB_14 (0x4000UL << RI_HYSCR1_PB_Pos) /!< 0x40000000 /
		5465	#define RI_HYSCR1_PB_15 (0x8000UL << RI_HYSCR1_PB_Pos) /!< 0x80000000 /
30	mjames	5466
		5467	/****************** Bit definition for RI_HYSCR2 register ******************/
		5468	#define RI_HYSCR2_PC_Pos (0U)
50	mjames	5469	#define RI_HYSCR2_PC_Msk (0xFFFFUL << RI_HYSCR2_PC_Pos) /!< 0x0000FFFF /
30	mjames	5470	#define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /!< PC[15:0] Port C Hysteresis selection /
50	mjames	5471	#define RI_HYSCR2_PC_0 (0x0001UL << RI_HYSCR2_PC_Pos) /!< 0x00000001 /
		5472	#define RI_HYSCR2_PC_1 (0x0002UL << RI_HYSCR2_PC_Pos) /!< 0x00000002 /
		5473	#define RI_HYSCR2_PC_2 (0x0004UL << RI_HYSCR2_PC_Pos) /!< 0x00000004 /
		5474	#define RI_HYSCR2_PC_3 (0x0008UL << RI_HYSCR2_PC_Pos) /!< 0x00000008 /
		5475	#define RI_HYSCR2_PC_4 (0x0010UL << RI_HYSCR2_PC_Pos) /!< 0x00000010 /
		5476	#define RI_HYSCR2_PC_5 (0x0020UL << RI_HYSCR2_PC_Pos) /!< 0x00000020 /
		5477	#define RI_HYSCR2_PC_6 (0x0040UL << RI_HYSCR2_PC_Pos) /!< 0x00000040 /
		5478	#define RI_HYSCR2_PC_7 (0x0080UL << RI_HYSCR2_PC_Pos) /!< 0x00000080 /
		5479	#define RI_HYSCR2_PC_8 (0x0100UL << RI_HYSCR2_PC_Pos) /!< 0x00000100 /
		5480	#define RI_HYSCR2_PC_9 (0x0200UL << RI_HYSCR2_PC_Pos) /!< 0x00000200 /
		5481	#define RI_HYSCR2_PC_10 (0x0400UL << RI_HYSCR2_PC_Pos) /!< 0x00000400 /
		5482	#define RI_HYSCR2_PC_11 (0x0800UL << RI_HYSCR2_PC_Pos) /!< 0x00000800 /
		5483	#define RI_HYSCR2_PC_12 (0x1000UL << RI_HYSCR2_PC_Pos) /!< 0x00001000 /
		5484	#define RI_HYSCR2_PC_13 (0x2000UL << RI_HYSCR2_PC_Pos) /!< 0x00002000 /
		5485	#define RI_HYSCR2_PC_14 (0x4000UL << RI_HYSCR2_PC_Pos) /!< 0x00004000 /
		5486	#define RI_HYSCR2_PC_15 (0x8000UL << RI_HYSCR2_PC_Pos) /!< 0x00008000 /
30	mjames	5487
		5488	#define RI_HYSCR2_PD_Pos (16U)
50	mjames	5489	#define RI_HYSCR2_PD_Msk (0xFFFFUL << RI_HYSCR2_PD_Pos) /!< 0xFFFF0000 /
30	mjames	5490	#define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /!< PD[15:0] Port D Hysteresis selection /
50	mjames	5491	#define RI_HYSCR2_PD_0 (0x0001UL << RI_HYSCR2_PD_Pos) /!< 0x00010000 /
		5492	#define RI_HYSCR2_PD_1 (0x0002UL << RI_HYSCR2_PD_Pos) /!< 0x00020000 /
		5493	#define RI_HYSCR2_PD_2 (0x0004UL << RI_HYSCR2_PD_Pos) /!< 0x00040000 /
		5494	#define RI_HYSCR2_PD_3 (0x0008UL << RI_HYSCR2_PD_Pos) /!< 0x00080000 /
		5495	#define RI_HYSCR2_PD_4 (0x0010UL << RI_HYSCR2_PD_Pos) /!< 0x00100000 /
		5496	#define RI_HYSCR2_PD_5 (0x0020UL << RI_HYSCR2_PD_Pos) /!< 0x00200000 /
		5497	#define RI_HYSCR2_PD_6 (0x0040UL << RI_HYSCR2_PD_Pos) /!< 0x00400000 /
		5498	#define RI_HYSCR2_PD_7 (0x0080UL << RI_HYSCR2_PD_Pos) /!< 0x00800000 /
		5499	#define RI_HYSCR2_PD_8 (0x0100UL << RI_HYSCR2_PD_Pos) /!< 0x01000000 /
		5500	#define RI_HYSCR2_PD_9 (0x0200UL << RI_HYSCR2_PD_Pos) /!< 0x02000000 /
		5501	#define RI_HYSCR2_PD_10 (0x0400UL << RI_HYSCR2_PD_Pos) /!< 0x04000000 /
		5502	#define RI_HYSCR2_PD_11 (0x0800UL << RI_HYSCR2_PD_Pos) /!< 0x08000000 /
		5503	#define RI_HYSCR2_PD_12 (0x1000UL << RI_HYSCR2_PD_Pos) /!< 0x10000000 /
		5504	#define RI_HYSCR2_PD_13 (0x2000UL << RI_HYSCR2_PD_Pos) /!< 0x20000000 /
		5505	#define RI_HYSCR2_PD_14 (0x4000UL << RI_HYSCR2_PD_Pos) /!< 0x40000000 /
		5506	#define RI_HYSCR2_PD_15 (0x8000UL << RI_HYSCR2_PD_Pos) /!< 0x80000000 /
30	mjames	5507
		5508	/****************** Bit definition for RI_HYSCR3 register ******************/
		5509	#define RI_HYSCR3_PE_Pos (0U)
50	mjames	5510	#define RI_HYSCR3_PE_Msk (0xFFFFUL << RI_HYSCR3_PE_Pos) /!< 0x0000FFFF /
30	mjames	5511	#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /!< PE[15:0] Port E Hysteresis selection /
50	mjames	5512	#define RI_HYSCR3_PE_0 (0x0001UL << RI_HYSCR3_PE_Pos) /!< 0x00000001 /
		5513	#define RI_HYSCR3_PE_1 (0x0002UL << RI_HYSCR3_PE_Pos) /!< 0x00000002 /
		5514	#define RI_HYSCR3_PE_2 (0x0004UL << RI_HYSCR3_PE_Pos) /!< 0x00000004 /
		5515	#define RI_HYSCR3_PE_3 (0x0008UL << RI_HYSCR3_PE_Pos) /!< 0x00000008 /
		5516	#define RI_HYSCR3_PE_4 (0x0010UL << RI_HYSCR3_PE_Pos) /!< 0x00000010 /
		5517	#define RI_HYSCR3_PE_5 (0x0020UL << RI_HYSCR3_PE_Pos) /!< 0x00000020 /
		5518	#define RI_HYSCR3_PE_6 (0x0040UL << RI_HYSCR3_PE_Pos) /!< 0x00000040 /
		5519	#define RI_HYSCR3_PE_7 (0x0080UL << RI_HYSCR3_PE_Pos) /!< 0x00000080 /
		5520	#define RI_HYSCR3_PE_8 (0x0100UL << RI_HYSCR3_PE_Pos) /!< 0x00000100 /
		5521	#define RI_HYSCR3_PE_9 (0x0200UL << RI_HYSCR3_PE_Pos) /!< 0x00000200 /
		5522	#define RI_HYSCR3_PE_10 (0x0400UL << RI_HYSCR3_PE_Pos) /!< 0x00000400 /
		5523	#define RI_HYSCR3_PE_11 (0x0800UL << RI_HYSCR3_PE_Pos) /!< 0x00000800 /
		5524	#define RI_HYSCR3_PE_12 (0x1000UL << RI_HYSCR3_PE_Pos) /!< 0x00001000 /
		5525	#define RI_HYSCR3_PE_13 (0x2000UL << RI_HYSCR3_PE_Pos) /!< 0x00002000 /
		5526	#define RI_HYSCR3_PE_14 (0x4000UL << RI_HYSCR3_PE_Pos) /!< 0x00004000 /
		5527	#define RI_HYSCR3_PE_15 (0x8000UL << RI_HYSCR3_PE_Pos) /!< 0x00008000 /
30	mjames	5528
		5529	/******************************************************************************/
		5530	/* */
		5531	/* Timers (TIM) */
		5532	/* */
		5533	/******************************************************************************/
		5534
		5535	/***************** Bit definition for TIM_CR1 register ******************/
		5536	#define TIM_CR1_CEN_Pos (0U)
50	mjames	5537	#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /!< 0x00000001 /
30	mjames	5538	#define TIM_CR1_CEN TIM_CR1_CEN_Msk /!<Counter enable /
		5539	#define TIM_CR1_UDIS_Pos (1U)
50	mjames	5540	#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /!< 0x00000002 /
30	mjames	5541	#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /!<Update disable /
		5542	#define TIM_CR1_URS_Pos (2U)
50	mjames	5543	#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /!< 0x00000004 /
30	mjames	5544	#define TIM_CR1_URS TIM_CR1_URS_Msk /!<Update request source /
		5545	#define TIM_CR1_OPM_Pos (3U)
50	mjames	5546	#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /!< 0x00000008 /
30	mjames	5547	#define TIM_CR1_OPM TIM_CR1_OPM_Msk /!<One pulse mode /
		5548	#define TIM_CR1_DIR_Pos (4U)
50	mjames	5549	#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /!< 0x00000010 /
30	mjames	5550	#define TIM_CR1_DIR TIM_CR1_DIR_Msk /!<Direction /
		5551
		5552	#define TIM_CR1_CMS_Pos (5U)
50	mjames	5553	#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /!< 0x00000060 /
30	mjames	5554	#define TIM_CR1_CMS TIM_CR1_CMS_Msk /!<CMS[1:0] bits (Center-aligned mode selection) /
50	mjames	5555	#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /!< 0x00000020 /
		5556	#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /!< 0x00000040 /
30	mjames	5557
		5558	#define TIM_CR1_ARPE_Pos (7U)
50	mjames	5559	#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /!< 0x00000080 /
30	mjames	5560	#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /!<Auto-reload preload enable /
		5561
		5562	#define TIM_CR1_CKD_Pos (8U)
50	mjames	5563	#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /!< 0x00000300 /
30	mjames	5564	#define TIM_CR1_CKD TIM_CR1_CKD_Msk /!<CKD[1:0] bits (clock division) /
50	mjames	5565	#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /!< 0x00000100 /
		5566	#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /!< 0x00000200 /
30	mjames	5567
		5568	/***************** Bit definition for TIM_CR2 register ******************/
		5569	#define TIM_CR2_CCDS_Pos (3U)
50	mjames	5570	#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /!< 0x00000008 /
30	mjames	5571	#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /!<Capture/Compare DMA Selection /
		5572
		5573	#define TIM_CR2_MMS_Pos (4U)
50	mjames	5574	#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /!< 0x00000070 /
30	mjames	5575	#define TIM_CR2_MMS TIM_CR2_MMS_Msk /!<MMS[2:0] bits (Master Mode Selection) /
50	mjames	5576	#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /!< 0x00000010 /
		5577	#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /!< 0x00000020 /
		5578	#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /!< 0x00000040 /
30	mjames	5579
		5580	#define TIM_CR2_TI1S_Pos (7U)
50	mjames	5581	#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /!< 0x00000080 /
30	mjames	5582	#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /!<TI1 Selection /
		5583
		5584	/***************** Bit definition for TIM_SMCR register *****************/
		5585	#define TIM_SMCR_SMS_Pos (0U)
50	mjames	5586	#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /!< 0x00000007 /
30	mjames	5587	#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /!<SMS[2:0] bits (Slave mode selection) /
50	mjames	5588	#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /!< 0x00000001 /
		5589	#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /!< 0x00000002 /
		5590	#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /!< 0x00000004 /
30	mjames	5591
		5592	#define TIM_SMCR_OCCS_Pos (3U)
50	mjames	5593	#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /!< 0x00000008 /
30	mjames	5594	#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /!< OCREF clear selection /
		5595
		5596	#define TIM_SMCR_TS_Pos (4U)
50	mjames	5597	#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /!< 0x00000070 /
30	mjames	5598	#define TIM_SMCR_TS TIM_SMCR_TS_Msk /!<TS[2:0] bits (Trigger selection) /
50	mjames	5599	#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /!< 0x00000010 /
		5600	#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /!< 0x00000020 /
		5601	#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /!< 0x00000040 /
30	mjames	5602
		5603	#define TIM_SMCR_MSM_Pos (7U)
50	mjames	5604	#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /!< 0x00000080 /
30	mjames	5605	#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /!<Master/slave mode /
		5606
		5607	#define TIM_SMCR_ETF_Pos (8U)
50	mjames	5608	#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /!< 0x00000F00 /
30	mjames	5609	#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /!<ETF[3:0] bits (External trigger filter) /
50	mjames	5610	#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /!< 0x00000100 /
		5611	#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /!< 0x00000200 /
		5612	#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /!< 0x00000400 /
		5613	#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /!< 0x00000800 /
30	mjames	5614
		5615	#define TIM_SMCR_ETPS_Pos (12U)
50	mjames	5616	#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /!< 0x00003000 /
30	mjames	5617	#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /!<ETPS[1:0] bits (External trigger prescaler) /
50	mjames	5618	#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /!< 0x00001000 /
		5619	#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /!< 0x00002000 /
30	mjames	5620
		5621	#define TIM_SMCR_ECE_Pos (14U)
50	mjames	5622	#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /!< 0x00004000 /
30	mjames	5623	#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /!<External clock enable /
		5624	#define TIM_SMCR_ETP_Pos (15U)
50	mjames	5625	#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /!< 0x00008000 /
30	mjames	5626	#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /!<External trigger polarity /
		5627
		5628	/***************** Bit definition for TIM_DIER register *****************/
		5629	#define TIM_DIER_UIE_Pos (0U)
50	mjames	5630	#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /!< 0x00000001 /
30	mjames	5631	#define TIM_DIER_UIE TIM_DIER_UIE_Msk /!<Update interrupt enable /
		5632	#define TIM_DIER_CC1IE_Pos (1U)
50	mjames	5633	#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /!< 0x00000002 /
30	mjames	5634	#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /!<Capture/Compare 1 interrupt enable /
		5635	#define TIM_DIER_CC2IE_Pos (2U)
50	mjames	5636	#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /!< 0x00000004 /
30	mjames	5637	#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /!<Capture/Compare 2 interrupt enable /
		5638	#define TIM_DIER_CC3IE_Pos (3U)
50	mjames	5639	#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /!< 0x00000008 /
30	mjames	5640	#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /!<Capture/Compare 3 interrupt enable /
		5641	#define TIM_DIER_CC4IE_Pos (4U)
50	mjames	5642	#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /!< 0x00000010 /
30	mjames	5643	#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /!<Capture/Compare 4 interrupt enable /
		5644	#define TIM_DIER_TIE_Pos (6U)
50	mjames	5645	#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /!< 0x00000040 /
30	mjames	5646	#define TIM_DIER_TIE TIM_DIER_TIE_Msk /!<Trigger interrupt enable /
		5647	#define TIM_DIER_UDE_Pos (8U)
50	mjames	5648	#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /!< 0x00000100 /
30	mjames	5649	#define TIM_DIER_UDE TIM_DIER_UDE_Msk /!<Update DMA request enable /
		5650	#define TIM_DIER_CC1DE_Pos (9U)
50	mjames	5651	#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /!< 0x00000200 /
30	mjames	5652	#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /!<Capture/Compare 1 DMA request enable /
		5653	#define TIM_DIER_CC2DE_Pos (10U)
50	mjames	5654	#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /!< 0x00000400 /
30	mjames	5655	#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /!<Capture/Compare 2 DMA request enable /
		5656	#define TIM_DIER_CC3DE_Pos (11U)
50	mjames	5657	#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /!< 0x00000800 /
30	mjames	5658	#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /!<Capture/Compare 3 DMA request enable /
		5659	#define TIM_DIER_CC4DE_Pos (12U)
50	mjames	5660	#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /!< 0x00001000 /
30	mjames	5661	#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /!<Capture/Compare 4 DMA request enable /
		5662	#define TIM_DIER_COMDE ((uint16_t)0x2000U) /!<COM DMA request enable /
		5663	#define TIM_DIER_TDE_Pos (14U)
50	mjames	5664	#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /!< 0x00004000 /
30	mjames	5665	#define TIM_DIER_TDE TIM_DIER_TDE_Msk /!<Trigger DMA request enable /
		5666
		5667	/****************** Bit definition for TIM_SR register ******************/
		5668	#define TIM_SR_UIF_Pos (0U)
50	mjames	5669	#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /!< 0x00000001 /
30	mjames	5670	#define TIM_SR_UIF TIM_SR_UIF_Msk /!<Update interrupt Flag /
		5671	#define TIM_SR_CC1IF_Pos (1U)
50	mjames	5672	#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /!< 0x00000002 /
30	mjames	5673	#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /!<Capture/Compare 1 interrupt Flag /
		5674	#define TIM_SR_CC2IF_Pos (2U)
50	mjames	5675	#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /!< 0x00000004 /
30	mjames	5676	#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /!<Capture/Compare 2 interrupt Flag /
		5677	#define TIM_SR_CC3IF_Pos (3U)
50	mjames	5678	#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /!< 0x00000008 /
30	mjames	5679	#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /!<Capture/Compare 3 interrupt Flag /
		5680	#define TIM_SR_CC4IF_Pos (4U)
50	mjames	5681	#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /!< 0x00000010 /
30	mjames	5682	#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /!<Capture/Compare 4 interrupt Flag /
		5683	#define TIM_SR_TIF_Pos (6U)
50	mjames	5684	#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /!< 0x00000040 /
30	mjames	5685	#define TIM_SR_TIF TIM_SR_TIF_Msk /!<Trigger interrupt Flag /
		5686	#define TIM_SR_CC1OF_Pos (9U)
50	mjames	5687	#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /!< 0x00000200 /
30	mjames	5688	#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /!<Capture/Compare 1 Overcapture Flag /
		5689	#define TIM_SR_CC2OF_Pos (10U)
50	mjames	5690	#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /!< 0x00000400 /
30	mjames	5691	#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /!<Capture/Compare 2 Overcapture Flag /
		5692	#define TIM_SR_CC3OF_Pos (11U)
50	mjames	5693	#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /!< 0x00000800 /
30	mjames	5694	#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /!<Capture/Compare 3 Overcapture Flag /
		5695	#define TIM_SR_CC4OF_Pos (12U)
50	mjames	5696	#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /!< 0x00001000 /
30	mjames	5697	#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /!<Capture/Compare 4 Overcapture Flag /
		5698
		5699	/***************** Bit definition for TIM_EGR register ******************/
		5700	#define TIM_EGR_UG_Pos (0U)
50	mjames	5701	#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /!< 0x00000001 /
30	mjames	5702	#define TIM_EGR_UG TIM_EGR_UG_Msk /!<Update Generation /
		5703	#define TIM_EGR_CC1G_Pos (1U)
50	mjames	5704	#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /!< 0x00000002 /
30	mjames	5705	#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /!<Capture/Compare 1 Generation /
		5706	#define TIM_EGR_CC2G_Pos (2U)
50	mjames	5707	#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /!< 0x00000004 /
30	mjames	5708	#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /!<Capture/Compare 2 Generation /
		5709	#define TIM_EGR_CC3G_Pos (3U)
50	mjames	5710	#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /!< 0x00000008 /
30	mjames	5711	#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /!<Capture/Compare 3 Generation /
		5712	#define TIM_EGR_CC4G_Pos (4U)
50	mjames	5713	#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /!< 0x00000010 /
30	mjames	5714	#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /!<Capture/Compare 4 Generation /
		5715	#define TIM_EGR_TG_Pos (6U)
50	mjames	5716	#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /!< 0x00000040 /
30	mjames	5717	#define TIM_EGR_TG TIM_EGR_TG_Msk /!<Trigger Generation /
		5718
		5719	/**************** Bit definition for TIM_CCMR1 register *****************/
		5720	#define TIM_CCMR1_CC1S_Pos (0U)
50	mjames	5721	#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /!< 0x00000003 /
30	mjames	5722	#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
50	mjames	5723	#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /!< 0x00000001 /
		5724	#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /!< 0x00000002 /
30	mjames	5725
		5726	#define TIM_CCMR1_OC1FE_Pos (2U)
50	mjames	5727	#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /!< 0x00000004 /
30	mjames	5728	#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /!<Output Compare 1 Fast enable /
		5729	#define TIM_CCMR1_OC1PE_Pos (3U)
50	mjames	5730	#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /!< 0x00000008 /
30	mjames	5731	#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /!<Output Compare 1 Preload enable /
		5732
		5733	#define TIM_CCMR1_OC1M_Pos (4U)
50	mjames	5734	#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000070 /
30	mjames	5735	#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /!<OC1M[2:0] bits (Output Compare 1 Mode) /
50	mjames	5736	#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000010 /
		5737	#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000020 /
		5738	#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /!< 0x00000040 /
30	mjames	5739
		5740	#define TIM_CCMR1_OC1CE_Pos (7U)
50	mjames	5741	#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /!< 0x00000080 /
30	mjames	5742	#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /!<Output Compare 1Clear Enable /
		5743
		5744	#define TIM_CCMR1_CC2S_Pos (8U)
50	mjames	5745	#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /!< 0x00000300 /
30	mjames	5746	#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
50	mjames	5747	#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /!< 0x00000100 /
		5748	#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /!< 0x00000200 /
30	mjames	5749
		5750	#define TIM_CCMR1_OC2FE_Pos (10U)
50	mjames	5751	#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /!< 0x00000400 /
30	mjames	5752	#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /!<Output Compare 2 Fast enable /
		5753	#define TIM_CCMR1_OC2PE_Pos (11U)
50	mjames	5754	#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /!< 0x00000800 /
30	mjames	5755	#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /!<Output Compare 2 Preload enable /
		5756
		5757	#define TIM_CCMR1_OC2M_Pos (12U)
50	mjames	5758	#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /!< 0x00007000 /
30	mjames	5759	#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /!<OC2M[2:0] bits (Output Compare 2 Mode) /
50	mjames	5760	#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /!< 0x00001000 /
		5761	#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /!< 0x00002000 /
		5762	#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /!< 0x00004000 /
30	mjames	5763
		5764	#define TIM_CCMR1_OC2CE_Pos (15U)
50	mjames	5765	#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /!< 0x00008000 /
30	mjames	5766	#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /!<Output Compare 2 Clear Enable /
		5767
		5768	/----------------------------------------------------------------------------/
		5769
		5770	#define TIM_CCMR1_IC1PSC_Pos (2U)
50	mjames	5771	#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /!< 0x0000000C /
30	mjames	5772	#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
50	mjames	5773	#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000004 /
		5774	#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000008 /
30	mjames	5775
		5776	#define TIM_CCMR1_IC1F_Pos (4U)
50	mjames	5777	#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /!< 0x000000F0 /
30	mjames	5778	#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /!<IC1F[3:0] bits (Input Capture 1 Filter) /
50	mjames	5779	#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000010 /
		5780	#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000020 /
		5781	#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000040 /
		5782	#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /!< 0x00000080 /
30	mjames	5783
		5784	#define TIM_CCMR1_IC2PSC_Pos (10U)
50	mjames	5785	#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000C00 /
30	mjames	5786	#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
50	mjames	5787	#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000400 /
		5788	#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000800 /
30	mjames	5789
		5790	#define TIM_CCMR1_IC2F_Pos (12U)
50	mjames	5791	#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /!< 0x0000F000 /
30	mjames	5792	#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /!<IC2F[3:0] bits (Input Capture 2 Filter) /
50	mjames	5793	#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /!< 0x00001000 /
		5794	#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /!< 0x00002000 /
		5795	#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /!< 0x00004000 /
		5796	#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /!< 0x00008000 /
30	mjames	5797
		5798	/**************** Bit definition for TIM_CCMR2 register *****************/
		5799	#define TIM_CCMR2_CC3S_Pos (0U)
50	mjames	5800	#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /!< 0x00000003 /
30	mjames	5801	#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
50	mjames	5802	#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /!< 0x00000001 /
		5803	#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /!< 0x00000002 /
30	mjames	5804
		5805	#define TIM_CCMR2_OC3FE_Pos (2U)
50	mjames	5806	#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /!< 0x00000004 /
30	mjames	5807	#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /!<Output Compare 3 Fast enable /
		5808	#define TIM_CCMR2_OC3PE_Pos (3U)
50	mjames	5809	#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /!< 0x00000008 /
30	mjames	5810	#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /!<Output Compare 3 Preload enable /
		5811
		5812	#define TIM_CCMR2_OC3M_Pos (4U)
50	mjames	5813	#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000070 /
30	mjames	5814	#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /!<OC3M[2:0] bits (Output Compare 3 Mode) /
50	mjames	5815	#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000010 /
		5816	#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000020 /
		5817	#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /!< 0x00000040 /
30	mjames	5818
		5819	#define TIM_CCMR2_OC3CE_Pos (7U)
50	mjames	5820	#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /!< 0x00000080 /
30	mjames	5821	#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /!<Output Compare 3 Clear Enable /
		5822
		5823	#define TIM_CCMR2_CC4S_Pos (8U)
50	mjames	5824	#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /!< 0x00000300 /
30	mjames	5825	#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
50	mjames	5826	#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /!< 0x00000100 /
		5827	#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /!< 0x00000200 /
30	mjames	5828
		5829	#define TIM_CCMR2_OC4FE_Pos (10U)
50	mjames	5830	#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /!< 0x00000400 /
30	mjames	5831	#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /!<Output Compare 4 Fast enable /
		5832	#define TIM_CCMR2_OC4PE_Pos (11U)
50	mjames	5833	#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /!< 0x00000800 /
30	mjames	5834	#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /!<Output Compare 4 Preload enable /
		5835
		5836	#define TIM_CCMR2_OC4M_Pos (12U)
50	mjames	5837	#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /!< 0x00007000 /
30	mjames	5838	#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /!<OC4M[2:0] bits (Output Compare 4 Mode) /
50	mjames	5839	#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /!< 0x00001000 /
		5840	#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /!< 0x00002000 /
		5841	#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /!< 0x00004000 /
30	mjames	5842
		5843	#define TIM_CCMR2_OC4CE_Pos (15U)
50	mjames	5844	#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /!< 0x00008000 /
30	mjames	5845	#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /!<Output Compare 4 Clear Enable /
		5846
		5847	/----------------------------------------------------------------------------/
		5848
		5849	#define TIM_CCMR2_IC3PSC_Pos (2U)
50	mjames	5850	#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /!< 0x0000000C /
30	mjames	5851	#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
50	mjames	5852	#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000004 /
		5853	#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000008 /
30	mjames	5854
		5855	#define TIM_CCMR2_IC3F_Pos (4U)
50	mjames	5856	#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /!< 0x000000F0 /
30	mjames	5857	#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /!<IC3F[3:0] bits (Input Capture 3 Filter) /
50	mjames	5858	#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000010 /
		5859	#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000020 /
		5860	#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000040 /
		5861	#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /!< 0x00000080 /
30	mjames	5862
		5863	#define TIM_CCMR2_IC4PSC_Pos (10U)
50	mjames	5864	#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000C00 /
30	mjames	5865	#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
50	mjames	5866	#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000400 /
		5867	#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000800 /
30	mjames	5868
		5869	#define TIM_CCMR2_IC4F_Pos (12U)
50	mjames	5870	#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /!< 0x0000F000 /
30	mjames	5871	#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /!<IC4F[3:0] bits (Input Capture 4 Filter) /
50	mjames	5872	#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /!< 0x00001000 /
		5873	#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /!< 0x00002000 /
		5874	#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /!< 0x00004000 /
		5875	#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /!< 0x00008000 /
30	mjames	5876
		5877	/***************** Bit definition for TIM_CCER register *****************/
		5878	#define TIM_CCER_CC1E_Pos (0U)
50	mjames	5879	#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /!< 0x00000001 /
30	mjames	5880	#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /!<Capture/Compare 1 output enable /
		5881	#define TIM_CCER_CC1P_Pos (1U)
50	mjames	5882	#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /!< 0x00000002 /
30	mjames	5883	#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /!<Capture/Compare 1 output Polarity /
		5884	#define TIM_CCER_CC1NP_Pos (3U)
50	mjames	5885	#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /!< 0x00000008 /
30	mjames	5886	#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /!<Capture/Compare 1 Complementary output Polarity /
		5887	#define TIM_CCER_CC2E_Pos (4U)
50	mjames	5888	#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /!< 0x00000010 /
30	mjames	5889	#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /!<Capture/Compare 2 output enable /
		5890	#define TIM_CCER_CC2P_Pos (5U)
50	mjames	5891	#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /!< 0x00000020 /
30	mjames	5892	#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /!<Capture/Compare 2 output Polarity /
		5893	#define TIM_CCER_CC2NP_Pos (7U)
50	mjames	5894	#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /!< 0x00000080 /
30	mjames	5895	#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /!<Capture/Compare 2 Complementary output Polarity /
		5896	#define TIM_CCER_CC3E_Pos (8U)
50	mjames	5897	#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /!< 0x00000100 /
30	mjames	5898	#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /!<Capture/Compare 3 output enable /
		5899	#define TIM_CCER_CC3P_Pos (9U)
50	mjames	5900	#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /!< 0x00000200 /
30	mjames	5901	#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /!<Capture/Compare 3 output Polarity /
		5902	#define TIM_CCER_CC3NP_Pos (11U)
50	mjames	5903	#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /!< 0x00000800 /
30	mjames	5904	#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /!<Capture/Compare 3 Complementary output Polarity /
		5905	#define TIM_CCER_CC4E_Pos (12U)
50	mjames	5906	#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /!< 0x00001000 /
30	mjames	5907	#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /!<Capture/Compare 4 output enable /
		5908	#define TIM_CCER_CC4P_Pos (13U)
50	mjames	5909	#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /!< 0x00002000 /
30	mjames	5910	#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /!<Capture/Compare 4 output Polarity /
		5911	#define TIM_CCER_CC4NP_Pos (15U)
50	mjames	5912	#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /!< 0x00008000 /
30	mjames	5913	#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /!<Capture/Compare 4 Complementary output Polarity /
		5914
		5915	/***************** Bit definition for TIM_CNT register ******************/
		5916	#define TIM_CNT_CNT_Pos (0U)
50	mjames	5917	#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /!< 0xFFFFFFFF /
30	mjames	5918	#define TIM_CNT_CNT TIM_CNT_CNT_Msk /!<Counter Value /
		5919
		5920	/***************** Bit definition for TIM_PSC register ******************/
		5921	#define TIM_PSC_PSC_Pos (0U)
50	mjames	5922	#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /!< 0x0000FFFF /
30	mjames	5923	#define TIM_PSC_PSC TIM_PSC_PSC_Msk /!<Prescaler Value /
		5924
		5925	/***************** Bit definition for TIM_ARR register ******************/
		5926	#define TIM_ARR_ARR_Pos (0U)
50	mjames	5927	#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /!< 0xFFFFFFFF /
30	mjames	5928	#define TIM_ARR_ARR TIM_ARR_ARR_Msk /!<actual auto-reload Value /
		5929
		5930	/***************** Bit definition for TIM_CCR1 register *****************/
		5931	#define TIM_CCR1_CCR1_Pos (0U)
50	mjames	5932	#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /!< 0x0000FFFF /
30	mjames	5933	#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /!<Capture/Compare 1 Value /
		5934
		5935	/***************** Bit definition for TIM_CCR2 register *****************/
		5936	#define TIM_CCR2_CCR2_Pos (0U)
50	mjames	5937	#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /!< 0x0000FFFF /
30	mjames	5938	#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /!<Capture/Compare 2 Value /
		5939
		5940	/***************** Bit definition for TIM_CCR3 register *****************/
		5941	#define TIM_CCR3_CCR3_Pos (0U)
50	mjames	5942	#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /!< 0x0000FFFF /
30	mjames	5943	#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /!<Capture/Compare 3 Value /
		5944
		5945	/***************** Bit definition for TIM_CCR4 register *****************/
		5946	#define TIM_CCR4_CCR4_Pos (0U)
50	mjames	5947	#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /!< 0x0000FFFF /
30	mjames	5948	#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /!<Capture/Compare 4 Value /
		5949
		5950	/***************** Bit definition for TIM_DCR register ******************/
		5951	#define TIM_DCR_DBA_Pos (0U)
50	mjames	5952	#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /!< 0x0000001F /
30	mjames	5953	#define TIM_DCR_DBA TIM_DCR_DBA_Msk /!<DBA[4:0] bits (DMA Base Address) /
50	mjames	5954	#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /!< 0x00000001 /
		5955	#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /!< 0x00000002 /
		5956	#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /!< 0x00000004 /
		5957	#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /!< 0x00000008 /
		5958	#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /!< 0x00000010 /
30	mjames	5959
		5960	#define TIM_DCR_DBL_Pos (8U)
50	mjames	5961	#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /!< 0x00001F00 /
30	mjames	5962	#define TIM_DCR_DBL TIM_DCR_DBL_Msk /!<DBL[4:0] bits (DMA Burst Length) /
50	mjames	5963	#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /!< 0x00000100 /
		5964	#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /!< 0x00000200 /
		5965	#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /!< 0x00000400 /
		5966	#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /!< 0x00000800 /
		5967	#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /!< 0x00001000 /
30	mjames	5968
		5969	/***************** Bit definition for TIM_DMAR register *****************/
		5970	#define TIM_DMAR_DMAB_Pos (0U)
50	mjames	5971	#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /!< 0x0000FFFF /
30	mjames	5972	#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /!<DMA register for burst accesses /
		5973
		5974	/***************** Bit definition for TIM_OR register *******************/
		5975	#define TIM_OR_TI1RMP_Pos (0U)
50	mjames	5976	#define TIM_OR_TI1RMP_Msk (0x3UL << TIM_OR_TI1RMP_Pos) /!< 0x00000003 /
30	mjames	5977	#define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /!<TI1_RMP[1:0] bits (TIM Input 1 remap) /
50	mjames	5978	#define TIM_OR_TI1RMP_0 (0x1UL << TIM_OR_TI1RMP_Pos) /!< 0x00000001 /
		5979	#define TIM_OR_TI1RMP_1 (0x2UL << TIM_OR_TI1RMP_Pos) /!< 0x00000002 /
30	mjames	5980
		5981	#define TIM_OR_ETR_RMP_Pos (2U)
50	mjames	5982	#define TIM_OR_ETR_RMP_Msk (0x1UL << TIM_OR_ETR_RMP_Pos) /!< 0x00000004 /
30	mjames	5983	#define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /!<ETR_RMP bit (TIM10/11 ETR remap)/
		5984	#define TIM_OR_TI1_RMP_RI_Pos (3U)
50	mjames	5985	#define TIM_OR_TI1_RMP_RI_Msk (0x1UL << TIM_OR_TI1_RMP_RI_Pos) /!< 0x00000008 /
30	mjames	5986	#define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) /
		5987
		5988
		5989	/******************************************************************************/
		5990	/* */
		5991	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
		5992	/* */
		5993	/******************************************************************************/
		5994
		5995	/***************** Bit definition for USART_SR register *****************/
		5996	#define USART_SR_PE_Pos (0U)
50	mjames	5997	#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /!< 0x00000001 /
30	mjames	5998	#define USART_SR_PE USART_SR_PE_Msk /!< Parity Error /
		5999	#define USART_SR_FE_Pos (1U)
50	mjames	6000	#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /!< 0x00000002 /
30	mjames	6001	#define USART_SR_FE USART_SR_FE_Msk /!< Framing Error /
		6002	#define USART_SR_NE_Pos (2U)
50	mjames	6003	#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /!< 0x00000004 /
30	mjames	6004	#define USART_SR_NE USART_SR_NE_Msk /!< Noise Error Flag /
		6005	#define USART_SR_ORE_Pos (3U)
50	mjames	6006	#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /!< 0x00000008 /
30	mjames	6007	#define USART_SR_ORE USART_SR_ORE_Msk /!< OverRun Error /
		6008	#define USART_SR_IDLE_Pos (4U)
50	mjames	6009	#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /!< 0x00000010 /
30	mjames	6010	#define USART_SR_IDLE USART_SR_IDLE_Msk /!< IDLE line detected /
		6011	#define USART_SR_RXNE_Pos (5U)
50	mjames	6012	#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /!< 0x00000020 /
30	mjames	6013	#define USART_SR_RXNE USART_SR_RXNE_Msk /!< Read Data Register Not Empty /
		6014	#define USART_SR_TC_Pos (6U)
50	mjames	6015	#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /!< 0x00000040 /
30	mjames	6016	#define USART_SR_TC USART_SR_TC_Msk /!< Transmission Complete /
		6017	#define USART_SR_TXE_Pos (7U)
50	mjames	6018	#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /!< 0x00000080 /
30	mjames	6019	#define USART_SR_TXE USART_SR_TXE_Msk /!< Transmit Data Register Empty /
		6020	#define USART_SR_LBD_Pos (8U)
50	mjames	6021	#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /!< 0x00000100 /
30	mjames	6022	#define USART_SR_LBD USART_SR_LBD_Msk /!< LIN Break Detection Flag /
		6023	#define USART_SR_CTS_Pos (9U)
50	mjames	6024	#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /!< 0x00000200 /
30	mjames	6025	#define USART_SR_CTS USART_SR_CTS_Msk /!< CTS Flag /
		6026
		6027	/***************** Bit definition for USART_DR register *****************/
		6028	#define USART_DR_DR_Pos (0U)
50	mjames	6029	#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /!< 0x000001FF /
30	mjames	6030	#define USART_DR_DR USART_DR_DR_Msk /!< Data value /
		6031
		6032	/**************** Bit definition for USART_BRR register *****************/
		6033	#define USART_BRR_DIV_FRACTION_Pos (0U)
50	mjames	6034	#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /!< 0x0000000F /
30	mjames	6035	#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /!< Fraction of USARTDIV /
		6036	#define USART_BRR_DIV_MANTISSA_Pos (4U)
50	mjames	6037	#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /!< 0x0000FFF0 /
30	mjames	6038	#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /!< Mantissa of USARTDIV /
		6039
		6040	/**************** Bit definition for USART_CR1 register *****************/
		6041	#define USART_CR1_SBK_Pos (0U)
50	mjames	6042	#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /!< 0x00000001 /
30	mjames	6043	#define USART_CR1_SBK USART_CR1_SBK_Msk /!< Send Break /
		6044	#define USART_CR1_RWU_Pos (1U)
50	mjames	6045	#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /!< 0x00000002 /
30	mjames	6046	#define USART_CR1_RWU USART_CR1_RWU_Msk /!< Receiver wakeup /
		6047	#define USART_CR1_RE_Pos (2U)
50	mjames	6048	#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /!< 0x00000004 /
30	mjames	6049	#define USART_CR1_RE USART_CR1_RE_Msk /!< Receiver Enable /
		6050	#define USART_CR1_TE_Pos (3U)
50	mjames	6051	#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /!< 0x00000008 /
30	mjames	6052	#define USART_CR1_TE USART_CR1_TE_Msk /!< Transmitter Enable /
		6053	#define USART_CR1_IDLEIE_Pos (4U)
50	mjames	6054	#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /!< 0x00000010 /
30	mjames	6055	#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /!< IDLE Interrupt Enable /
		6056	#define USART_CR1_RXNEIE_Pos (5U)
50	mjames	6057	#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /!< 0x00000020 /
30	mjames	6058	#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /!< RXNE Interrupt Enable /
		6059	#define USART_CR1_TCIE_Pos (6U)
50	mjames	6060	#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /!< 0x00000040 /
30	mjames	6061	#define USART_CR1_TCIE USART_CR1_TCIE_Msk /!< Transmission Complete Interrupt Enable /
		6062	#define USART_CR1_TXEIE_Pos (7U)
50	mjames	6063	#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /!< 0x00000080 /
30	mjames	6064	#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /!< PE Interrupt Enable /
		6065	#define USART_CR1_PEIE_Pos (8U)
50	mjames	6066	#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /!< 0x00000100 /
30	mjames	6067	#define USART_CR1_PEIE USART_CR1_PEIE_Msk /!< PE Interrupt Enable /
		6068	#define USART_CR1_PS_Pos (9U)
50	mjames	6069	#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /!< 0x00000200 /
30	mjames	6070	#define USART_CR1_PS USART_CR1_PS_Msk /!< Parity Selection /
		6071	#define USART_CR1_PCE_Pos (10U)
50	mjames	6072	#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /!< 0x00000400 /
30	mjames	6073	#define USART_CR1_PCE USART_CR1_PCE_Msk /!< Parity Control Enable /
		6074	#define USART_CR1_WAKE_Pos (11U)
50	mjames	6075	#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /!< 0x00000800 /
30	mjames	6076	#define USART_CR1_WAKE USART_CR1_WAKE_Msk /!< Wakeup method /
		6077	#define USART_CR1_M_Pos (12U)
50	mjames	6078	#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /!< 0x00001000 /
30	mjames	6079	#define USART_CR1_M USART_CR1_M_Msk /!< Word length /
		6080	#define USART_CR1_UE_Pos (13U)
50	mjames	6081	#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /!< 0x00002000 /
30	mjames	6082	#define USART_CR1_UE USART_CR1_UE_Msk /!< USART Enable /
		6083	#define USART_CR1_OVER8_Pos (15U)
50	mjames	6084	#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /!< 0x00008000 /
30	mjames	6085	#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /!< Oversampling by 8-bit mode /
		6086
		6087	/**************** Bit definition for USART_CR2 register *****************/
		6088	#define USART_CR2_ADD_Pos (0U)
50	mjames	6089	#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /!< 0x0000000F /
30	mjames	6090	#define USART_CR2_ADD USART_CR2_ADD_Msk /!< Address of the USART node /
		6091	#define USART_CR2_LBDL_Pos (5U)
50	mjames	6092	#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /!< 0x00000020 /
30	mjames	6093	#define USART_CR2_LBDL USART_CR2_LBDL_Msk /!< LIN Break Detection Length /
		6094	#define USART_CR2_LBDIE_Pos (6U)
50	mjames	6095	#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /!< 0x00000040 /
30	mjames	6096	#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /!< LIN Break Detection Interrupt Enable /
		6097	#define USART_CR2_LBCL_Pos (8U)
50	mjames	6098	#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /!< 0x00000100 /
30	mjames	6099	#define USART_CR2_LBCL USART_CR2_LBCL_Msk /!< Last Bit Clock pulse /
		6100	#define USART_CR2_CPHA_Pos (9U)
50	mjames	6101	#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /!< 0x00000200 /
30	mjames	6102	#define USART_CR2_CPHA USART_CR2_CPHA_Msk /!< Clock Phase /
		6103	#define USART_CR2_CPOL_Pos (10U)
50	mjames	6104	#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /!< 0x00000400 /
30	mjames	6105	#define USART_CR2_CPOL USART_CR2_CPOL_Msk /!< Clock Polarity /
		6106	#define USART_CR2_CLKEN_Pos (11U)
50	mjames	6107	#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /!< 0x00000800 /
30	mjames	6108	#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /!< Clock Enable /
		6109
		6110	#define USART_CR2_STOP_Pos (12U)
50	mjames	6111	#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /!< 0x00003000 /
30	mjames	6112	#define USART_CR2_STOP USART_CR2_STOP_Msk /!< STOP[1:0] bits (STOP bits) /
50	mjames	6113	#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /!< 0x00001000 /
		6114	#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /!< 0x00002000 /
30	mjames	6115
		6116	#define USART_CR2_LINEN_Pos (14U)
50	mjames	6117	#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /!< 0x00004000 /
30	mjames	6118	#define USART_CR2_LINEN USART_CR2_LINEN_Msk /!< LIN mode enable /
		6119
		6120	/**************** Bit definition for USART_CR3 register *****************/
		6121	#define USART_CR3_EIE_Pos (0U)
50	mjames	6122	#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /!< 0x00000001 /
30	mjames	6123	#define USART_CR3_EIE USART_CR3_EIE_Msk /!< Error Interrupt Enable /
		6124	#define USART_CR3_IREN_Pos (1U)
50	mjames	6125	#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /!< 0x00000002 /
30	mjames	6126	#define USART_CR3_IREN USART_CR3_IREN_Msk /!< IrDA mode Enable /
		6127	#define USART_CR3_IRLP_Pos (2U)
50	mjames	6128	#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /!< 0x00000004 /
30	mjames	6129	#define USART_CR3_IRLP USART_CR3_IRLP_Msk /!< IrDA Low-Power /
		6130	#define USART_CR3_HDSEL_Pos (3U)
50	mjames	6131	#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /!< 0x00000008 /
30	mjames	6132	#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /!< Half-Duplex Selection /
		6133	#define USART_CR3_NACK_Pos (4U)
50	mjames	6134	#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /!< 0x00000010 /
30	mjames	6135	#define USART_CR3_NACK USART_CR3_NACK_Msk /!< Smartcard NACK enable /
		6136	#define USART_CR3_SCEN_Pos (5U)
50	mjames	6137	#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /!< 0x00000020 /
30	mjames	6138	#define USART_CR3_SCEN USART_CR3_SCEN_Msk /!< Smartcard mode enable /
		6139	#define USART_CR3_DMAR_Pos (6U)
50	mjames	6140	#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /!< 0x00000040 /
30	mjames	6141	#define USART_CR3_DMAR USART_CR3_DMAR_Msk /!< DMA Enable Receiver /
		6142	#define USART_CR3_DMAT_Pos (7U)
50	mjames	6143	#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /!< 0x00000080 /
30	mjames	6144	#define USART_CR3_DMAT USART_CR3_DMAT_Msk /!< DMA Enable Transmitter /
		6145	#define USART_CR3_RTSE_Pos (8U)
50	mjames	6146	#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /!< 0x00000100 /
30	mjames	6147	#define USART_CR3_RTSE USART_CR3_RTSE_Msk /!< RTS Enable /
		6148	#define USART_CR3_CTSE_Pos (9U)
50	mjames	6149	#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /!< 0x00000200 /
30	mjames	6150	#define USART_CR3_CTSE USART_CR3_CTSE_Msk /!< CTS Enable /
		6151	#define USART_CR3_CTSIE_Pos (10U)
50	mjames	6152	#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /!< 0x00000400 /
30	mjames	6153	#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /!< CTS Interrupt Enable /
		6154	#define USART_CR3_ONEBIT_Pos (11U)
50	mjames	6155	#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /!< 0x00000800 /
30	mjames	6156	#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /!< One sample bit method enable /
		6157
		6158	/**************** Bit definition for USART_GTPR register ****************/
		6159	#define USART_GTPR_PSC_Pos (0U)
50	mjames	6160	#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /!< 0x000000FF /
30	mjames	6161	#define USART_GTPR_PSC USART_GTPR_PSC_Msk /!< PSC[7:0] bits (Prescaler value) /
50	mjames	6162	#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /!< 0x00000001 /
		6163	#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /!< 0x00000002 /
		6164	#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /!< 0x00000004 /
		6165	#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /!< 0x00000008 /
		6166	#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /!< 0x00000010 /
		6167	#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /!< 0x00000020 /
		6168	#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /!< 0x00000040 /
		6169	#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /!< 0x00000080 /
30	mjames	6170
		6171	#define USART_GTPR_GT_Pos (8U)
50	mjames	6172	#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /!< 0x0000FF00 /
30	mjames	6173	#define USART_GTPR_GT USART_GTPR_GT_Msk /!< Guard time value /
		6174
		6175	/******************************************************************************/
		6176	/* */
		6177	/* Universal Serial Bus (USB) */
		6178	/* */
		6179	/******************************************************************************/
		6180
		6181	/!<Endpoint-specific registers /
		6182
		6183	#define USB_EP0R USB_BASE /!< endpoint 0 register address /
		6184	#define USB_EP1R (USB_BASE + 0x00000004U) /!< endpoint 1 register address /
		6185	#define USB_EP2R (USB_BASE + 0x00000008U) /!< endpoint 2 register address /
		6186	#define USB_EP3R (USB_BASE + 0x0000000CU) /!< endpoint 3 register address /
		6187	#define USB_EP4R (USB_BASE + 0x00000010U) /!< endpoint 4 register address /
		6188	#define USB_EP5R (USB_BASE + 0x00000014U) /!< endpoint 5 register address /
		6189	#define USB_EP6R (USB_BASE + 0x00000018U) /!< endpoint 6 register address /
		6190	#define USB_EP7R (USB_BASE + 0x0000001CU) /!< endpoint 7 register address /
		6191
		6192	/* bit positions */
		6193	#define USB_EP_CTR_RX_Pos (15U)
50	mjames	6194	#define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /!< 0x00008000 /
30	mjames	6195	#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /!< EndPoint Correct TRansfer RX /
		6196	#define USB_EP_DTOG_RX_Pos (14U)
50	mjames	6197	#define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /!< 0x00004000 /
30	mjames	6198	#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /!< EndPoint Data TOGGLE RX /
		6199	#define USB_EPRX_STAT_Pos (12U)
50	mjames	6200	#define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /!< 0x00003000 /
30	mjames	6201	#define USB_EPRX_STAT USB_EPRX_STAT_Msk /!< EndPoint RX STATus bit field /
		6202	#define USB_EP_SETUP_Pos (11U)
50	mjames	6203	#define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /!< 0x00000800 /
30	mjames	6204	#define USB_EP_SETUP USB_EP_SETUP_Msk /!< EndPoint SETUP /
		6205	#define USB_EP_T_FIELD_Pos (9U)
50	mjames	6206	#define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /!< 0x00000600 /
30	mjames	6207	#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /!< EndPoint TYPE /
		6208	#define USB_EP_KIND_Pos (8U)
50	mjames	6209	#define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /!< 0x00000100 /
30	mjames	6210	#define USB_EP_KIND USB_EP_KIND_Msk /!< EndPoint KIND /
		6211	#define USB_EP_CTR_TX_Pos (7U)
50	mjames	6212	#define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /!< 0x00000080 /
30	mjames	6213	#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /!< EndPoint Correct TRansfer TX /
		6214	#define USB_EP_DTOG_TX_Pos (6U)
50	mjames	6215	#define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /!< 0x00000040 /
30	mjames	6216	#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /!< EndPoint Data TOGGLE TX /
		6217	#define USB_EPTX_STAT_Pos (4U)
50	mjames	6218	#define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /!< 0x00000030 /
30	mjames	6219	#define USB_EPTX_STAT USB_EPTX_STAT_Msk /!< EndPoint TX STATus bit field /
		6220	#define USB_EPADDR_FIELD_Pos (0U)
50	mjames	6221	#define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /!< 0x0000000F /
30	mjames	6222	#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /!< EndPoint ADDRess FIELD /
		6223
		6224	/* EndPoint REGister MASK (no toggle fields) */
		6225	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
		6226	/!< EP_TYPE[1:0] EndPoint TYPE /
		6227	#define USB_EP_TYPE_MASK_Pos (9U)
50	mjames	6228	#define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /!< 0x00000600 /
30	mjames	6229	#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /!< EndPoint TYPE Mask /
		6230	#define USB_EP_BULK (0x00000000U) /!< EndPoint BULK /
		6231	#define USB_EP_CONTROL (0x00000200U) /!< EndPoint CONTROL /
		6232	#define USB_EP_ISOCHRONOUS (0x00000400U) /!< EndPoint ISOCHRONOUS /
		6233	#define USB_EP_INTERRUPT (0x00000600U) /!< EndPoint INTERRUPT /
		6234	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
		6235
		6236	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
		6237	/!< STAT_TX[1:0] STATus for TX transfer /
		6238	#define USB_EP_TX_DIS (0x00000000U) /!< EndPoint TX DISabled /
		6239	#define USB_EP_TX_STALL (0x00000010U) /!< EndPoint TX STALLed /
		6240	#define USB_EP_TX_NAK (0x00000020U) /!< EndPoint TX NAKed /
		6241	#define USB_EP_TX_VALID (0x00000030U) /!< EndPoint TX VALID /
		6242	#define USB_EPTX_DTOG1 (0x00000010U) /!< EndPoint TX Data TOGgle bit1 /
		6243	#define USB_EPTX_DTOG2 (0x00000020U) /!< EndPoint TX Data TOGgle bit2 /
		6244	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
		6245	/!< STAT_RX[1:0] STATus for RX transfer /
		6246	#define USB_EP_RX_DIS (0x00000000U) /!< EndPoint RX DISabled /
		6247	#define USB_EP_RX_STALL (0x00001000U) /!< EndPoint RX STALLed /
		6248	#define USB_EP_RX_NAK (0x00002000U) /!< EndPoint RX NAKed /
		6249	#define USB_EP_RX_VALID (0x00003000U) /!< EndPoint RX VALID /
		6250	#define USB_EPRX_DTOG1 (0x00001000U) /!< EndPoint RX Data TOGgle bit1 /
		6251	#define USB_EPRX_DTOG2 (0x00002000U) /!< EndPoint RX Data TOGgle bit1 /
		6252	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
		6253
		6254	/***************** Bit definition for USB_EP0R register *****************/
		6255	#define USB_EP0R_EA_Pos (0U)
50	mjames	6256	#define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /!< 0x0000000F /
30	mjames	6257	#define USB_EP0R_EA USB_EP0R_EA_Msk /!<Endpoint Address /
		6258
		6259	#define USB_EP0R_STAT_TX_Pos (4U)
50	mjames	6260	#define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /!< 0x00000030 /
30	mjames	6261	#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
50	mjames	6262	#define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /!< 0x00000010 /
		6263	#define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /!< 0x00000020 /
30	mjames	6264
		6265	#define USB_EP0R_DTOG_TX_Pos (6U)
50	mjames	6266	#define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /!< 0x00000040 /
30	mjames	6267	#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		6268	#define USB_EP0R_CTR_TX_Pos (7U)
50	mjames	6269	#define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /!< 0x00000080 /
30	mjames	6270	#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /!<Correct Transfer for transmission /
		6271	#define USB_EP0R_EP_KIND_Pos (8U)
50	mjames	6272	#define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /!< 0x00000100 /
30	mjames	6273	#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /!<Endpoint Kind /
		6274
		6275	#define USB_EP0R_EP_TYPE_Pos (9U)
50	mjames	6276	#define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /!< 0x00000600 /
30	mjames	6277	#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
50	mjames	6278	#define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /!< 0x00000200 /
		6279	#define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /!< 0x00000400 /
30	mjames	6280
		6281	#define USB_EP0R_SETUP_Pos (11U)
50	mjames	6282	#define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /!< 0x00000800 /
30	mjames	6283	#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /!<Setup transaction completed /
		6284
		6285	#define USB_EP0R_STAT_RX_Pos (12U)
50	mjames	6286	#define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /!< 0x00003000 /
30	mjames	6287	#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
50	mjames	6288	#define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /!< 0x00001000 /
		6289	#define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /!< 0x00002000 /
30	mjames	6290
		6291	#define USB_EP0R_DTOG_RX_Pos (14U)
50	mjames	6292	#define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /!< 0x00004000 /
30	mjames	6293	#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		6294	#define USB_EP0R_CTR_RX_Pos (15U)
50	mjames	6295	#define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /!< 0x00008000 /
30	mjames	6296	#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /!<Correct Transfer for reception /
		6297
		6298	/***************** Bit definition for USB_EP1R register *****************/
		6299	#define USB_EP1R_EA_Pos (0U)
50	mjames	6300	#define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /!< 0x0000000F /
30	mjames	6301	#define USB_EP1R_EA USB_EP1R_EA_Msk /!<Endpoint Address /
		6302
		6303	#define USB_EP1R_STAT_TX_Pos (4U)
50	mjames	6304	#define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /!< 0x00000030 /
30	mjames	6305	#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
50	mjames	6306	#define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /!< 0x00000010 /
		6307	#define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /!< 0x00000020 /
30	mjames	6308
		6309	#define USB_EP1R_DTOG_TX_Pos (6U)
50	mjames	6310	#define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /!< 0x00000040 /
30	mjames	6311	#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		6312	#define USB_EP1R_CTR_TX_Pos (7U)
50	mjames	6313	#define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /!< 0x00000080 /
30	mjames	6314	#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /!<Correct Transfer for transmission /
		6315	#define USB_EP1R_EP_KIND_Pos (8U)
50	mjames	6316	#define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /!< 0x00000100 /
30	mjames	6317	#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /!<Endpoint Kind /
		6318
		6319	#define USB_EP1R_EP_TYPE_Pos (9U)
50	mjames	6320	#define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /!< 0x00000600 /
30	mjames	6321	#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
50	mjames	6322	#define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /!< 0x00000200 /
		6323	#define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /!< 0x00000400 /
30	mjames	6324
		6325	#define USB_EP1R_SETUP_Pos (11U)
50	mjames	6326	#define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /!< 0x00000800 /
30	mjames	6327	#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /!<Setup transaction completed /
		6328
		6329	#define USB_EP1R_STAT_RX_Pos (12U)
50	mjames	6330	#define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /!< 0x00003000 /
30	mjames	6331	#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
50	mjames	6332	#define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /!< 0x00001000 /
		6333	#define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /!< 0x00002000 /
30	mjames	6334
		6335	#define USB_EP1R_DTOG_RX_Pos (14U)
50	mjames	6336	#define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /!< 0x00004000 /
30	mjames	6337	#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		6338	#define USB_EP1R_CTR_RX_Pos (15U)
50	mjames	6339	#define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /!< 0x00008000 /
30	mjames	6340	#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /!<Correct Transfer for reception /
		6341
		6342	/***************** Bit definition for USB_EP2R register *****************/
		6343	#define USB_EP2R_EA_Pos (0U)
50	mjames	6344	#define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /!< 0x0000000F /
30	mjames	6345	#define USB_EP2R_EA USB_EP2R_EA_Msk /!<Endpoint Address /
		6346
		6347	#define USB_EP2R_STAT_TX_Pos (4U)
50	mjames	6348	#define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /!< 0x00000030 /
30	mjames	6349	#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
50	mjames	6350	#define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /!< 0x00000010 /
		6351	#define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /!< 0x00000020 /
30	mjames	6352
		6353	#define USB_EP2R_DTOG_TX_Pos (6U)
50	mjames	6354	#define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /!< 0x00000040 /
30	mjames	6355	#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		6356	#define USB_EP2R_CTR_TX_Pos (7U)
50	mjames	6357	#define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /!< 0x00000080 /
30	mjames	6358	#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /!<Correct Transfer for transmission /
		6359	#define USB_EP2R_EP_KIND_Pos (8U)
50	mjames	6360	#define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /!< 0x00000100 /
30	mjames	6361	#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /!<Endpoint Kind /
		6362
		6363	#define USB_EP2R_EP_TYPE_Pos (9U)
50	mjames	6364	#define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /!< 0x00000600 /
30	mjames	6365	#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
50	mjames	6366	#define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /!< 0x00000200 /
		6367	#define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /!< 0x00000400 /
30	mjames	6368
		6369	#define USB_EP2R_SETUP_Pos (11U)
50	mjames	6370	#define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /!< 0x00000800 /
30	mjames	6371	#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /!<Setup transaction completed /
		6372
		6373	#define USB_EP2R_STAT_RX_Pos (12U)
50	mjames	6374	#define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /!< 0x00003000 /
30	mjames	6375	#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
50	mjames	6376	#define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /!< 0x00001000 /
		6377	#define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /!< 0x00002000 /
30	mjames	6378
		6379	#define USB_EP2R_DTOG_RX_Pos (14U)
50	mjames	6380	#define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /!< 0x00004000 /
30	mjames	6381	#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		6382	#define USB_EP2R_CTR_RX_Pos (15U)
50	mjames	6383	#define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /!< 0x00008000 /
30	mjames	6384	#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /!<Correct Transfer for reception /
		6385
		6386	/***************** Bit definition for USB_EP3R register *****************/
		6387	#define USB_EP3R_EA_Pos (0U)
50	mjames	6388	#define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /!< 0x0000000F /
30	mjames	6389	#define USB_EP3R_EA USB_EP3R_EA_Msk /!<Endpoint Address /
		6390
		6391	#define USB_EP3R_STAT_TX_Pos (4U)
50	mjames	6392	#define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /!< 0x00000030 /
30	mjames	6393	#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
50	mjames	6394	#define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /!< 0x00000010 /
		6395	#define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /!< 0x00000020 /
30	mjames	6396
		6397	#define USB_EP3R_DTOG_TX_Pos (6U)
50	mjames	6398	#define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /!< 0x00000040 /
30	mjames	6399	#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		6400	#define USB_EP3R_CTR_TX_Pos (7U)
50	mjames	6401	#define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /!< 0x00000080 /
30	mjames	6402	#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /!<Correct Transfer for transmission /
		6403	#define USB_EP3R_EP_KIND_Pos (8U)
50	mjames	6404	#define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /!< 0x00000100 /
30	mjames	6405	#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /!<Endpoint Kind /
		6406
		6407	#define USB_EP3R_EP_TYPE_Pos (9U)
50	mjames	6408	#define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /!< 0x00000600 /
30	mjames	6409	#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
50	mjames	6410	#define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /!< 0x00000200 /
		6411	#define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /!< 0x00000400 /
30	mjames	6412
		6413	#define USB_EP3R_SETUP_Pos (11U)
50	mjames	6414	#define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /!< 0x00000800 /
30	mjames	6415	#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /!<Setup transaction completed /
		6416
		6417	#define USB_EP3R_STAT_RX_Pos (12U)
50	mjames	6418	#define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /!< 0x00003000 /
30	mjames	6419	#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
50	mjames	6420	#define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /!< 0x00001000 /
		6421	#define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /!< 0x00002000 /
30	mjames	6422
		6423	#define USB_EP3R_DTOG_RX_Pos (14U)
50	mjames	6424	#define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /!< 0x00004000 /
30	mjames	6425	#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		6426	#define USB_EP3R_CTR_RX_Pos (15U)
50	mjames	6427	#define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /!< 0x00008000 /
30	mjames	6428	#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /!<Correct Transfer for reception /
		6429
		6430	/***************** Bit definition for USB_EP4R register *****************/
		6431	#define USB_EP4R_EA_Pos (0U)
50	mjames	6432	#define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /!< 0x0000000F /
30	mjames	6433	#define USB_EP4R_EA USB_EP4R_EA_Msk /!<Endpoint Address /
		6434
		6435	#define USB_EP4R_STAT_TX_Pos (4U)
50	mjames	6436	#define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /!< 0x00000030 /
30	mjames	6437	#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
50	mjames	6438	#define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /!< 0x00000010 /
		6439	#define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /!< 0x00000020 /
30	mjames	6440
		6441	#define USB_EP4R_DTOG_TX_Pos (6U)
50	mjames	6442	#define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /!< 0x00000040 /
30	mjames	6443	#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		6444	#define USB_EP4R_CTR_TX_Pos (7U)
50	mjames	6445	#define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /!< 0x00000080 /
30	mjames	6446	#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /!<Correct Transfer for transmission /
		6447	#define USB_EP4R_EP_KIND_Pos (8U)
50	mjames	6448	#define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /!< 0x00000100 /
30	mjames	6449	#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /!<Endpoint Kind /
		6450
		6451	#define USB_EP4R_EP_TYPE_Pos (9U)
50	mjames	6452	#define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /!< 0x00000600 /
30	mjames	6453	#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
50	mjames	6454	#define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /!< 0x00000200 /
		6455	#define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /!< 0x00000400 /
30	mjames	6456
		6457	#define USB_EP4R_SETUP_Pos (11U)
50	mjames	6458	#define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /!< 0x00000800 /
30	mjames	6459	#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /!<Setup transaction completed /
		6460
		6461	#define USB_EP4R_STAT_RX_Pos (12U)
50	mjames	6462	#define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /!< 0x00003000 /
30	mjames	6463	#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
50	mjames	6464	#define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /!< 0x00001000 /
		6465	#define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /!< 0x00002000 /
30	mjames	6466
		6467	#define USB_EP4R_DTOG_RX_Pos (14U)
50	mjames	6468	#define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /!< 0x00004000 /
30	mjames	6469	#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		6470	#define USB_EP4R_CTR_RX_Pos (15U)
50	mjames	6471	#define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /!< 0x00008000 /
30	mjames	6472	#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /!<Correct Transfer for reception /
		6473
		6474	/***************** Bit definition for USB_EP5R register *****************/
		6475	#define USB_EP5R_EA_Pos (0U)
50	mjames	6476	#define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /!< 0x0000000F /
30	mjames	6477	#define USB_EP5R_EA USB_EP5R_EA_Msk /!<Endpoint Address /
		6478
		6479	#define USB_EP5R_STAT_TX_Pos (4U)
50	mjames	6480	#define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /!< 0x00000030 /
30	mjames	6481	#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
50	mjames	6482	#define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /!< 0x00000010 /
		6483	#define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /!< 0x00000020 /
30	mjames	6484
		6485	#define USB_EP5R_DTOG_TX_Pos (6U)
50	mjames	6486	#define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /!< 0x00000040 /
30	mjames	6487	#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		6488	#define USB_EP5R_CTR_TX_Pos (7U)
50	mjames	6489	#define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /!< 0x00000080 /
30	mjames	6490	#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /!<Correct Transfer for transmission /
		6491	#define USB_EP5R_EP_KIND_Pos (8U)
50	mjames	6492	#define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /!< 0x00000100 /
30	mjames	6493	#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /!<Endpoint Kind /
		6494
		6495	#define USB_EP5R_EP_TYPE_Pos (9U)
50	mjames	6496	#define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /!< 0x00000600 /
30	mjames	6497	#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
50	mjames	6498	#define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /!< 0x00000200 /
		6499	#define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /!< 0x00000400 /
30	mjames	6500
		6501	#define USB_EP5R_SETUP_Pos (11U)
50	mjames	6502	#define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /!< 0x00000800 /
30	mjames	6503	#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /!<Setup transaction completed /
		6504
		6505	#define USB_EP5R_STAT_RX_Pos (12U)
50	mjames	6506	#define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /!< 0x00003000 /
30	mjames	6507	#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
50	mjames	6508	#define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /!< 0x00001000 /
		6509	#define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /!< 0x00002000 /
30	mjames	6510
		6511	#define USB_EP5R_DTOG_RX_Pos (14U)
50	mjames	6512	#define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /!< 0x00004000 /
30	mjames	6513	#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		6514	#define USB_EP5R_CTR_RX_Pos (15U)
50	mjames	6515	#define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /!< 0x00008000 /
30	mjames	6516	#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /!<Correct Transfer for reception /
		6517
		6518	/***************** Bit definition for USB_EP6R register *****************/
		6519	#define USB_EP6R_EA_Pos (0U)
50	mjames	6520	#define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /!< 0x0000000F /
30	mjames	6521	#define USB_EP6R_EA USB_EP6R_EA_Msk /!<Endpoint Address /
		6522
		6523	#define USB_EP6R_STAT_TX_Pos (4U)
50	mjames	6524	#define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /!< 0x00000030 /
30	mjames	6525	#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
50	mjames	6526	#define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /!< 0x00000010 /
		6527	#define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /!< 0x00000020 /
30	mjames	6528
		6529	#define USB_EP6R_DTOG_TX_Pos (6U)
50	mjames	6530	#define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /!< 0x00000040 /
30	mjames	6531	#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		6532	#define USB_EP6R_CTR_TX_Pos (7U)
50	mjames	6533	#define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /!< 0x00000080 /
30	mjames	6534	#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /!<Correct Transfer for transmission /
		6535	#define USB_EP6R_EP_KIND_Pos (8U)
50	mjames	6536	#define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /!< 0x00000100 /
30	mjames	6537	#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /!<Endpoint Kind /
		6538
		6539	#define USB_EP6R_EP_TYPE_Pos (9U)
50	mjames	6540	#define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /!< 0x00000600 /
30	mjames	6541	#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
50	mjames	6542	#define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /!< 0x00000200 /
		6543	#define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /!< 0x00000400 /
30	mjames	6544
		6545	#define USB_EP6R_SETUP_Pos (11U)
50	mjames	6546	#define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /!< 0x00000800 /
30	mjames	6547	#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /!<Setup transaction completed /
		6548
		6549	#define USB_EP6R_STAT_RX_Pos (12U)
50	mjames	6550	#define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /!< 0x00003000 /
30	mjames	6551	#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
50	mjames	6552	#define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /!< 0x00001000 /
		6553	#define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /!< 0x00002000 /
30	mjames	6554
		6555	#define USB_EP6R_DTOG_RX_Pos (14U)
50	mjames	6556	#define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /!< 0x00004000 /
30	mjames	6557	#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		6558	#define USB_EP6R_CTR_RX_Pos (15U)
50	mjames	6559	#define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /!< 0x00008000 /
30	mjames	6560	#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /!<Correct Transfer for reception /
		6561
		6562	/***************** Bit definition for USB_EP7R register *****************/
		6563	#define USB_EP7R_EA_Pos (0U)
50	mjames	6564	#define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /!< 0x0000000F /
30	mjames	6565	#define USB_EP7R_EA USB_EP7R_EA_Msk /!<Endpoint Address /
		6566
		6567	#define USB_EP7R_STAT_TX_Pos (4U)
50	mjames	6568	#define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /!< 0x00000030 /
30	mjames	6569	#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
50	mjames	6570	#define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /!< 0x00000010 /
		6571	#define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /!< 0x00000020 /
30	mjames	6572
		6573	#define USB_EP7R_DTOG_TX_Pos (6U)
50	mjames	6574	#define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /!< 0x00000040 /
30	mjames	6575	#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		6576	#define USB_EP7R_CTR_TX_Pos (7U)
50	mjames	6577	#define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /!< 0x00000080 /
30	mjames	6578	#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /!<Correct Transfer for transmission /
		6579	#define USB_EP7R_EP_KIND_Pos (8U)
50	mjames	6580	#define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /!< 0x00000100 /
30	mjames	6581	#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /!<Endpoint Kind /
		6582
		6583	#define USB_EP7R_EP_TYPE_Pos (9U)
50	mjames	6584	#define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /!< 0x00000600 /
30	mjames	6585	#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
50	mjames	6586	#define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /!< 0x00000200 /
		6587	#define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /!< 0x00000400 /
30	mjames	6588
		6589	#define USB_EP7R_SETUP_Pos (11U)
50	mjames	6590	#define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /!< 0x00000800 /
30	mjames	6591	#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /!<Setup transaction completed /
		6592
		6593	#define USB_EP7R_STAT_RX_Pos (12U)
50	mjames	6594	#define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /!< 0x00003000 /
30	mjames	6595	#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
50	mjames	6596	#define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /!< 0x00001000 /
		6597	#define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /!< 0x00002000 /
30	mjames	6598
		6599	#define USB_EP7R_DTOG_RX_Pos (14U)
50	mjames	6600	#define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /!< 0x00004000 /
30	mjames	6601	#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		6602	#define USB_EP7R_CTR_RX_Pos (15U)
50	mjames	6603	#define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /!< 0x00008000 /
30	mjames	6604	#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /!<Correct Transfer for reception /
		6605
		6606	/!<Common registers /
		6607
		6608	#define USB_CNTR (USB_BASE + 0x00000040U) /!< Control register /
		6609	#define USB_ISTR (USB_BASE + 0x00000044U) /!< Interrupt status register /
		6610	#define USB_FNR (USB_BASE + 0x00000048U) /!< Frame number register /
		6611	#define USB_DADDR (USB_BASE + 0x0000004CU) /!< Device address register /
		6612	#define USB_BTABLE (USB_BASE + 0x00000050U) /!< Buffer Table address register /
		6613
		6614
		6615
		6616	/***************** Bit definition for USB_CNTR register *****************/
		6617	#define USB_CNTR_FRES_Pos (0U)
50	mjames	6618	#define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /!< 0x00000001 /
30	mjames	6619	#define USB_CNTR_FRES USB_CNTR_FRES_Msk /!<Force USB Reset /
		6620	#define USB_CNTR_PDWN_Pos (1U)
50	mjames	6621	#define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /!< 0x00000002 /
30	mjames	6622	#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /!<Power down /
		6623	#define USB_CNTR_LPMODE_Pos (2U)
50	mjames	6624	#define USB_CNTR_LPMODE_Msk (0x1UL << USB_CNTR_LPMODE_Pos) /!< 0x00000004 /
30	mjames	6625	#define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /!<Low-power mode /
		6626	#define USB_CNTR_FSUSP_Pos (3U)
50	mjames	6627	#define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /!< 0x00000008 /
30	mjames	6628	#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /!<Force suspend /
		6629	#define USB_CNTR_RESUME_Pos (4U)
50	mjames	6630	#define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /!< 0x00000010 /
30	mjames	6631	#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /!<Resume request /
		6632	#define USB_CNTR_ESOFM_Pos (8U)
50	mjames	6633	#define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /!< 0x00000100 /
30	mjames	6634	#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /!<Expected Start Of Frame Interrupt Mask /
		6635	#define USB_CNTR_SOFM_Pos (9U)
50	mjames	6636	#define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /!< 0x00000200 /
30	mjames	6637	#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /!<Start Of Frame Interrupt Mask /
		6638	#define USB_CNTR_RESETM_Pos (10U)
50	mjames	6639	#define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /!< 0x00000400 /
30	mjames	6640	#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /!<RESET Interrupt Mask /
		6641	#define USB_CNTR_SUSPM_Pos (11U)
50	mjames	6642	#define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /!< 0x00000800 /
30	mjames	6643	#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /!<Suspend mode Interrupt Mask /
		6644	#define USB_CNTR_WKUPM_Pos (12U)
50	mjames	6645	#define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /!< 0x00001000 /
30	mjames	6646	#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /!<Wakeup Interrupt Mask /
		6647	#define USB_CNTR_ERRM_Pos (13U)
50	mjames	6648	#define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /!< 0x00002000 /
30	mjames	6649	#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /!<Error Interrupt Mask /
		6650	#define USB_CNTR_PMAOVRM_Pos (14U)
50	mjames	6651	#define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /!< 0x00004000 /
30	mjames	6652	#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /!<Packet Memory Area Over / Underrun Interrupt Mask /
		6653	#define USB_CNTR_CTRM_Pos (15U)
50	mjames	6654	#define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /!< 0x00008000 /
30	mjames	6655	#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /!<Correct Transfer Interrupt Mask /
		6656
		6657	/***************** Bit definition for USB_ISTR register *****************/
		6658	#define USB_ISTR_EP_ID_Pos (0U)
50	mjames	6659	#define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /!< 0x0000000F /
30	mjames	6660	#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /!<Endpoint Identifier /
		6661	#define USB_ISTR_DIR_Pos (4U)
50	mjames	6662	#define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /!< 0x00000010 /
30	mjames	6663	#define USB_ISTR_DIR USB_ISTR_DIR_Msk /!<Direction of transaction /
		6664	#define USB_ISTR_ESOF_Pos (8U)
50	mjames	6665	#define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /!< 0x00000100 /
30	mjames	6666	#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /!<Expected Start Of Frame /
		6667	#define USB_ISTR_SOF_Pos (9U)
50	mjames	6668	#define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /!< 0x00000200 /
30	mjames	6669	#define USB_ISTR_SOF USB_ISTR_SOF_Msk /!<Start Of Frame /
		6670	#define USB_ISTR_RESET_Pos (10U)
50	mjames	6671	#define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /!< 0x00000400 /
30	mjames	6672	#define USB_ISTR_RESET USB_ISTR_RESET_Msk /!<USB RESET request /
		6673	#define USB_ISTR_SUSP_Pos (11U)
50	mjames	6674	#define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /!< 0x00000800 /
30	mjames	6675	#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /!<Suspend mode request /
		6676	#define USB_ISTR_WKUP_Pos (12U)
50	mjames	6677	#define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /!< 0x00001000 /
30	mjames	6678	#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /!<Wake up /
		6679	#define USB_ISTR_ERR_Pos (13U)
50	mjames	6680	#define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /!< 0x00002000 /
30	mjames	6681	#define USB_ISTR_ERR USB_ISTR_ERR_Msk /!<Error /
		6682	#define USB_ISTR_PMAOVR_Pos (14U)
50	mjames	6683	#define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /!< 0x00004000 /
30	mjames	6684	#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /!<Packet Memory Area Over / Underrun /
		6685	#define USB_ISTR_CTR_Pos (15U)
50	mjames	6686	#define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /!< 0x00008000 /
30	mjames	6687	#define USB_ISTR_CTR USB_ISTR_CTR_Msk /!<Correct Transfer /
		6688
		6689	#define USB_CLR_CTR (~USB_ISTR_CTR) /!< clear Correct TRansfer bit /
		6690	#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /!< clear DMA OVeR/underrun bit/
		6691	#define USB_CLR_ERR (~USB_ISTR_ERR) /!< clear ERRor bit /
		6692	#define USB_CLR_WKUP (~USB_ISTR_WKUP) /!< clear WaKe UP bit /
		6693	#define USB_CLR_SUSP (~USB_ISTR_SUSP) /!< clear SUSPend bit /
		6694	#define USB_CLR_RESET (~USB_ISTR_RESET) /!< clear RESET bit /
		6695	#define USB_CLR_SOF (~USB_ISTR_SOF) /!< clear Start Of Frame bit /
		6696	#define USB_CLR_ESOF (~USB_ISTR_ESOF) /!< clear Expected Start Of Frame bit /
		6697
		6698
		6699	/***************** Bit definition for USB_FNR register ******************/
		6700	#define USB_FNR_FN_Pos (0U)
50	mjames	6701	#define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /!< 0x000007FF /
30	mjames	6702	#define USB_FNR_FN USB_FNR_FN_Msk /!<Frame Number /
		6703	#define USB_FNR_LSOF_Pos (11U)
50	mjames	6704	#define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /!< 0x00001800 /
30	mjames	6705	#define USB_FNR_LSOF USB_FNR_LSOF_Msk /!<Lost SOF /
		6706	#define USB_FNR_LCK_Pos (13U)
50	mjames	6707	#define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /!< 0x00002000 /
30	mjames	6708	#define USB_FNR_LCK USB_FNR_LCK_Msk /!<Locked /
		6709	#define USB_FNR_RXDM_Pos (14U)
50	mjames	6710	#define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /!< 0x00004000 /
30	mjames	6711	#define USB_FNR_RXDM USB_FNR_RXDM_Msk /!<Receive Data - Line Status /
		6712	#define USB_FNR_RXDP_Pos (15U)
50	mjames	6713	#define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /!< 0x00008000 /
30	mjames	6714	#define USB_FNR_RXDP USB_FNR_RXDP_Msk /!<Receive Data + Line Status /
		6715
		6716	/**************** Bit definition for USB_DADDR register *****************/
		6717	#define USB_DADDR_ADD_Pos (0U)
50	mjames	6718	#define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /!< 0x0000007F /
30	mjames	6719	#define USB_DADDR_ADD USB_DADDR_ADD_Msk /!<ADD[6:0] bits (Device Address) /
		6720	#define USB_DADDR_ADD0_Pos (0U)
50	mjames	6721	#define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /!< 0x00000001 /
30	mjames	6722	#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /!<Bit 0 /
		6723	#define USB_DADDR_ADD1_Pos (1U)
50	mjames	6724	#define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /!< 0x00000002 /
30	mjames	6725	#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /!<Bit 1 /
		6726	#define USB_DADDR_ADD2_Pos (2U)
50	mjames	6727	#define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /!< 0x00000004 /
30	mjames	6728	#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /!<Bit 2 /
		6729	#define USB_DADDR_ADD3_Pos (3U)
50	mjames	6730	#define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /!< 0x00000008 /
30	mjames	6731	#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /!<Bit 3 /
		6732	#define USB_DADDR_ADD4_Pos (4U)
50	mjames	6733	#define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /!< 0x00000010 /
30	mjames	6734	#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /!<Bit 4 /
		6735	#define USB_DADDR_ADD5_Pos (5U)
50	mjames	6736	#define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /!< 0x00000020 /
30	mjames	6737	#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /!<Bit 5 /
		6738	#define USB_DADDR_ADD6_Pos (6U)
50	mjames	6739	#define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /!< 0x00000040 /
30	mjames	6740	#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /!<Bit 6 /
		6741
		6742	#define USB_DADDR_EF_Pos (7U)
50	mjames	6743	#define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /!< 0x00000080 /
30	mjames	6744	#define USB_DADDR_EF USB_DADDR_EF_Msk /!<Enable Function /
		6745
		6746	/**************** Bit definition for USB_BTABLE register ****************/
		6747	#define USB_BTABLE_BTABLE_Pos (3U)
50	mjames	6748	#define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /!< 0x0000FFF8 /
30	mjames	6749	#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /!<Buffer Table /
		6750
		6751	/!< Buffer descriptor table /
		6752	/*************** Bit definition for USB_ADDR0_TX register ***************/
		6753	#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
50	mjames	6754	#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /!< 0x0000FFFE /
30	mjames	6755	#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /!< Transmission Buffer Address 0 /
		6756
		6757	/*************** Bit definition for USB_ADDR1_TX register ***************/
		6758	#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
50	mjames	6759	#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /!< 0x0000FFFE /
30	mjames	6760	#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /!< Transmission Buffer Address 1 /
		6761
		6762	/*************** Bit definition for USB_ADDR2_TX register ***************/
		6763	#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
50	mjames	6764	#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /!< 0x0000FFFE /
30	mjames	6765	#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /!< Transmission Buffer Address 2 /
		6766
		6767	/*************** Bit definition for USB_ADDR3_TX register ***************/
		6768	#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
50	mjames	6769	#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /!< 0x0000FFFE /
30	mjames	6770	#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /!< Transmission Buffer Address 3 /
		6771
		6772	/*************** Bit definition for USB_ADDR4_TX register ***************/
		6773	#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
50	mjames	6774	#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /!< 0x0000FFFE /
30	mjames	6775	#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /!< Transmission Buffer Address 4 /
		6776
		6777	/*************** Bit definition for USB_ADDR5_TX register ***************/
		6778	#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
50	mjames	6779	#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /!< 0x0000FFFE /
30	mjames	6780	#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /!< Transmission Buffer Address 5 /
		6781
		6782	/*************** Bit definition for USB_ADDR6_TX register ***************/
		6783	#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
50	mjames	6784	#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /!< 0x0000FFFE /
30	mjames	6785	#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /!< Transmission Buffer Address 6 /
		6786
		6787	/*************** Bit definition for USB_ADDR7_TX register ***************/
		6788	#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
50	mjames	6789	#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /!< 0x0000FFFE /
30	mjames	6790	#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /!< Transmission Buffer Address 7 /
		6791
		6792	/----------------------------------------------------------------------------/
		6793
		6794	/*************** Bit definition for USB_COUNT0_TX register **************/
		6795	#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
50	mjames	6796	#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /!< 0x000003FF /
30	mjames	6797	#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /!< Transmission Byte Count 0 /
		6798
		6799	/*************** Bit definition for USB_COUNT1_TX register **************/
		6800	#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
50	mjames	6801	#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /!< 0x000003FF /
30	mjames	6802	#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /!< Transmission Byte Count 1 /
		6803
		6804	/*************** Bit definition for USB_COUNT2_TX register **************/
		6805	#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
50	mjames	6806	#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /!< 0x000003FF /
30	mjames	6807	#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /!< Transmission Byte Count 2 /
		6808
		6809	/*************** Bit definition for USB_COUNT3_TX register **************/
		6810	#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
50	mjames	6811	#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /!< 0x000003FF /
30	mjames	6812	#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /!< Transmission Byte Count 3 /
		6813
		6814	/*************** Bit definition for USB_COUNT4_TX register **************/
		6815	#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
50	mjames	6816	#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /!< 0x000003FF /
30	mjames	6817	#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /!< Transmission Byte Count 4 /
		6818
		6819	/*************** Bit definition for USB_COUNT5_TX register **************/
		6820	#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
50	mjames	6821	#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /!< 0x000003FF /
30	mjames	6822	#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /!< Transmission Byte Count 5 /
		6823
		6824	/*************** Bit definition for USB_COUNT6_TX register **************/
		6825	#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
50	mjames	6826	#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /!< 0x000003FF /
30	mjames	6827	#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /!< Transmission Byte Count 6 /
		6828
		6829	/*************** Bit definition for USB_COUNT7_TX register **************/
		6830	#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
50	mjames	6831	#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /!< 0x000003FF /
30	mjames	6832	#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /!< Transmission Byte Count 7 /
		6833
		6834	/----------------------------------------------------------------------------/
		6835
		6836	/************** Bit definition for USB_COUNT0_TX_0 register *************/
		6837	#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /!< Transmission Byte Count 0 (low) /
		6838
		6839	/************** Bit definition for USB_COUNT0_TX_1 register *************/
		6840	#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /!< Transmission Byte Count 0 (high) /
		6841
		6842	/************** Bit definition for USB_COUNT1_TX_0 register *************/
		6843	#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /!< Transmission Byte Count 1 (low) /
		6844
		6845	/************** Bit definition for USB_COUNT1_TX_1 register *************/
		6846	#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /!< Transmission Byte Count 1 (high) /
		6847
		6848	/************** Bit definition for USB_COUNT2_TX_0 register *************/
		6849	#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /!< Transmission Byte Count 2 (low) /
		6850
		6851	/************** Bit definition for USB_COUNT2_TX_1 register *************/
		6852	#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /!< Transmission Byte Count 2 (high) /
		6853
		6854	/************** Bit definition for USB_COUNT3_TX_0 register *************/
50	mjames	6855	#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /!< Transmission Byte Count 3 (low) /
30	mjames	6856
		6857	/************** Bit definition for USB_COUNT3_TX_1 register *************/
50	mjames	6858	#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /!< Transmission Byte Count 3 (high) /
30	mjames	6859
		6860	/************** Bit definition for USB_COUNT4_TX_0 register *************/
		6861	#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /!< Transmission Byte Count 4 (low) /
		6862
		6863	/************** Bit definition for USB_COUNT4_TX_1 register *************/
		6864	#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /!< Transmission Byte Count 4 (high) /
		6865
		6866	/************** Bit definition for USB_COUNT5_TX_0 register *************/
		6867	#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /!< Transmission Byte Count 5 (low) /
		6868
		6869	/************** Bit definition for USB_COUNT5_TX_1 register *************/
		6870	#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /!< Transmission Byte Count 5 (high) /
		6871
		6872	/************** Bit definition for USB_COUNT6_TX_0 register *************/
		6873	#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /!< Transmission Byte Count 6 (low) /
		6874
		6875	/************** Bit definition for USB_COUNT6_TX_1 register *************/
		6876	#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /!< Transmission Byte Count 6 (high) /
		6877
		6878	/************** Bit definition for USB_COUNT7_TX_0 register *************/
		6879	#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /!< Transmission Byte Count 7 (low) /
		6880
		6881	/************** Bit definition for USB_COUNT7_TX_1 register *************/
		6882	#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /!< Transmission Byte Count 7 (high) /
		6883
		6884	/----------------------------------------------------------------------------/
		6885
		6886	/*************** Bit definition for USB_ADDR0_RX register ***************/
		6887	#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
50	mjames	6888	#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /!< 0x0000FFFE /
30	mjames	6889	#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /!< Reception Buffer Address 0 /
		6890
		6891	/*************** Bit definition for USB_ADDR1_RX register ***************/
		6892	#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
50	mjames	6893	#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /!< 0x0000FFFE /
30	mjames	6894	#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /!< Reception Buffer Address 1 /
		6895
		6896	/*************** Bit definition for USB_ADDR2_RX register ***************/
		6897	#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
50	mjames	6898	#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /!< 0x0000FFFE /
30	mjames	6899	#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /!< Reception Buffer Address 2 /
		6900
		6901	/*************** Bit definition for USB_ADDR3_RX register ***************/
		6902	#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
50	mjames	6903	#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /!< 0x0000FFFE /
30	mjames	6904	#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /!< Reception Buffer Address 3 /
		6905
		6906	/*************** Bit definition for USB_ADDR4_RX register ***************/
		6907	#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
50	mjames	6908	#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /!< 0x0000FFFE /
30	mjames	6909	#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /!< Reception Buffer Address 4 /
		6910
		6911	/*************** Bit definition for USB_ADDR5_RX register ***************/
		6912	#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
50	mjames	6913	#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /!< 0x0000FFFE /
30	mjames	6914	#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /!< Reception Buffer Address 5 /
		6915
		6916	/*************** Bit definition for USB_ADDR6_RX register ***************/
		6917	#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
50	mjames	6918	#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /!< 0x0000FFFE /
30	mjames	6919	#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /!< Reception Buffer Address 6 /
		6920
		6921	/*************** Bit definition for USB_ADDR7_RX register ***************/
		6922	#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
50	mjames	6923	#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /!< 0x0000FFFE /
30	mjames	6924	#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /!< Reception Buffer Address 7 /
		6925
		6926	/----------------------------------------------------------------------------/
		6927
		6928	/*************** Bit definition for USB_COUNT0_RX register **************/
		6929	#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
50	mjames	6930	#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /!< 0x000003FF /
30	mjames	6931	#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /!< Reception Byte Count /
		6932
		6933	#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
50	mjames	6934	#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
30	mjames	6935	#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
50	mjames	6936	#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		6937	#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		6938	#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		6939	#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		6940	#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
30	mjames	6941
		6942	#define USB_COUNT0_RX_BLSIZE_Pos (15U)
50	mjames	6943	#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /!< 0x00008000 /
30	mjames	6944	#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /!< BLock SIZE /
		6945
		6946	/*************** Bit definition for USB_COUNT1_RX register **************/
		6947	#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
50	mjames	6948	#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /!< 0x000003FF /
30	mjames	6949	#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /!< Reception Byte Count /
		6950
		6951	#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
50	mjames	6952	#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
30	mjames	6953	#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
50	mjames	6954	#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		6955	#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		6956	#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		6957	#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		6958	#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
30	mjames	6959
		6960	#define USB_COUNT1_RX_BLSIZE_Pos (15U)
50	mjames	6961	#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /!< 0x00008000 /
30	mjames	6962	#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /!< BLock SIZE /
		6963
		6964	/*************** Bit definition for USB_COUNT2_RX register **************/
		6965	#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
50	mjames	6966	#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /!< 0x000003FF /
30	mjames	6967	#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /!< Reception Byte Count /
		6968
		6969	#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
50	mjames	6970	#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
30	mjames	6971	#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
50	mjames	6972	#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		6973	#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		6974	#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		6975	#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		6976	#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
30	mjames	6977
		6978	#define USB_COUNT2_RX_BLSIZE_Pos (15U)
50	mjames	6979	#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /!< 0x00008000 /
30	mjames	6980	#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /!< BLock SIZE /
		6981
		6982	/*************** Bit definition for USB_COUNT3_RX register **************/
		6983	#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
50	mjames	6984	#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /!< 0x000003FF /
30	mjames	6985	#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /!< Reception Byte Count /
		6986
		6987	#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
50	mjames	6988	#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
30	mjames	6989	#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
50	mjames	6990	#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		6991	#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		6992	#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		6993	#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		6994	#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
30	mjames	6995
		6996	#define USB_COUNT3_RX_BLSIZE_Pos (15U)
50	mjames	6997	#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /!< 0x00008000 /
30	mjames	6998	#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /!< BLock SIZE /
		6999
		7000	/*************** Bit definition for USB_COUNT4_RX register **************/
		7001	#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
50	mjames	7002	#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /!< 0x000003FF /
30	mjames	7003	#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /!< Reception Byte Count /
		7004
		7005	#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
50	mjames	7006	#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
30	mjames	7007	#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
50	mjames	7008	#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		7009	#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		7010	#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		7011	#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		7012	#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
30	mjames	7013
		7014	#define USB_COUNT4_RX_BLSIZE_Pos (15U)
50	mjames	7015	#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /!< 0x00008000 /
30	mjames	7016	#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /!< BLock SIZE /
		7017
		7018	/*************** Bit definition for USB_COUNT5_RX register **************/
		7019	#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
50	mjames	7020	#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /!< 0x000003FF /
30	mjames	7021	#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /!< Reception Byte Count /
		7022
		7023	#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
50	mjames	7024	#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
30	mjames	7025	#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
50	mjames	7026	#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		7027	#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		7028	#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		7029	#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		7030	#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
30	mjames	7031
		7032	#define USB_COUNT5_RX_BLSIZE_Pos (15U)
50	mjames	7033	#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /!< 0x00008000 /
30	mjames	7034	#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /!< BLock SIZE /
		7035
		7036	/*************** Bit definition for USB_COUNT6_RX register **************/
		7037	#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
50	mjames	7038	#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /!< 0x000003FF /
30	mjames	7039	#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /!< Reception Byte Count /
		7040
		7041	#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
50	mjames	7042	#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
30	mjames	7043	#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
50	mjames	7044	#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		7045	#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		7046	#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		7047	#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		7048	#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
30	mjames	7049
		7050	#define USB_COUNT6_RX_BLSIZE_Pos (15U)
50	mjames	7051	#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /!< 0x00008000 /
30	mjames	7052	#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /!< BLock SIZE /
		7053
		7054	/*************** Bit definition for USB_COUNT7_RX register **************/
		7055	#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
50	mjames	7056	#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /!< 0x000003FF /
30	mjames	7057	#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /!< Reception Byte Count /
		7058
		7059	#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
50	mjames	7060	#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
30	mjames	7061	#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
50	mjames	7062	#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		7063	#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		7064	#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		7065	#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		7066	#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
30	mjames	7067
		7068	#define USB_COUNT7_RX_BLSIZE_Pos (15U)
50	mjames	7069	#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /!< 0x00008000 /
30	mjames	7070	#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /!< BLock SIZE /
		7071
		7072	/----------------------------------------------------------------------------/
		7073
		7074	/************** Bit definition for USB_COUNT0_RX_0 register *************/
		7075	#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		7076
		7077	#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		7078	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		7079	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		7080	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		7081	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		7082	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		7083
		7084	#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		7085
		7086	/************** Bit definition for USB_COUNT0_RX_1 register *************/
		7087	#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		7088
		7089	#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		7090	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 1 /
		7091	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		7092	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		7093	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		7094	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		7095
		7096	#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		7097
		7098	/************** Bit definition for USB_COUNT1_RX_0 register *************/
		7099	#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		7100
		7101	#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		7102	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		7103	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		7104	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		7105	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		7106	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		7107
		7108	#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		7109
		7110	/************** Bit definition for USB_COUNT1_RX_1 register *************/
		7111	#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		7112
		7113	#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		7114	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		7115	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		7116	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		7117	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		7118	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		7119
		7120	#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		7121
		7122	/************** Bit definition for USB_COUNT2_RX_0 register *************/
		7123	#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		7124
		7125	#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		7126	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		7127	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		7128	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		7129	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		7130	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		7131
		7132	#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		7133
		7134	/************** Bit definition for USB_COUNT2_RX_1 register *************/
		7135	#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		7136
		7137	#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		7138	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		7139	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		7140	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		7141	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		7142	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		7143
		7144	#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		7145
		7146	/************** Bit definition for USB_COUNT3_RX_0 register *************/
		7147	#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		7148
		7149	#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		7150	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		7151	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		7152	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		7153	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		7154	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		7155
		7156	#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		7157
		7158	/************** Bit definition for USB_COUNT3_RX_1 register *************/
		7159	#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		7160
		7161	#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		7162	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		7163	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		7164	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		7165	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		7166	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		7167
		7168	#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		7169
		7170	/************** Bit definition for USB_COUNT4_RX_0 register *************/
		7171	#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		7172
		7173	#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		7174	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		7175	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		7176	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		7177	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		7178	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		7179
		7180	#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		7181
		7182	/************** Bit definition for USB_COUNT4_RX_1 register *************/
		7183	#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		7184
		7185	#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		7186	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		7187	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		7188	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		7189	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		7190	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		7191
		7192	#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		7193
		7194	/************** Bit definition for USB_COUNT5_RX_0 register *************/
		7195	#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		7196
		7197	#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		7198	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		7199	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		7200	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		7201	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		7202	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		7203
		7204	#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		7205
		7206	/************** Bit definition for USB_COUNT5_RX_1 register *************/
		7207	#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		7208
		7209	#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		7210	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		7211	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		7212	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		7213	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		7214	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		7215
		7216	#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		7217
		7218	/************* Bit definition for USB_COUNT6_RX_0 register *************/
		7219	#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		7220
		7221	#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		7222	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		7223	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		7224	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		7225	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		7226	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		7227
		7228	#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		7229
		7230	/************** Bit definition for USB_COUNT6_RX_1 register *************/
		7231	#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		7232
		7233	#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		7234	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		7235	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		7236	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		7237	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		7238	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		7239
		7240	#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		7241
		7242	/************* Bit definition for USB_COUNT7_RX_0 register **************/
		7243	#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		7244
		7245	#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		7246	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		7247	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		7248	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		7249	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		7250	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		7251
		7252	#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		7253
		7254	/************* Bit definition for USB_COUNT7_RX_1 register **************/
		7255	#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		7256
		7257	#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		7258	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		7259	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		7260	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		7261	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		7262	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		7263
		7264	#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		7265
		7266	/******************************************************************************/
		7267	/* */
		7268	/* Window WATCHDOG (WWDG) */
		7269	/* */
		7270	/******************************************************************************/
		7271
		7272	/***************** Bit definition for WWDG_CR register ******************/
		7273	#define WWDG_CR_T_Pos (0U)
50	mjames	7274	#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /!< 0x0000007F /
30	mjames	7275	#define WWDG_CR_T WWDG_CR_T_Msk /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
50	mjames	7276	#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /!< 0x00000001 /
		7277	#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /!< 0x00000002 /
		7278	#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /!< 0x00000004 /
		7279	#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /!< 0x00000008 /
		7280	#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /!< 0x00000010 /
		7281	#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /!< 0x00000020 /
		7282	#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /!< 0x00000040 /
30	mjames	7283
		7284	/* Legacy defines */
		7285	#define WWDG_CR_T0 WWDG_CR_T_0
		7286	#define WWDG_CR_T1 WWDG_CR_T_1
		7287	#define WWDG_CR_T2 WWDG_CR_T_2
		7288	#define WWDG_CR_T3 WWDG_CR_T_3
		7289	#define WWDG_CR_T4 WWDG_CR_T_4
		7290	#define WWDG_CR_T5 WWDG_CR_T_5
		7291	#define WWDG_CR_T6 WWDG_CR_T_6
		7292
		7293	#define WWDG_CR_WDGA_Pos (7U)
50	mjames	7294	#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /!< 0x00000080 /
30	mjames	7295	#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /!< Activation bit /
		7296
		7297	/***************** Bit definition for WWDG_CFR register *****************/
		7298	#define WWDG_CFR_W_Pos (0U)
50	mjames	7299	#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /!< 0x0000007F /
30	mjames	7300	#define WWDG_CFR_W WWDG_CFR_W_Msk /!< W[6:0] bits (7-bit window value) /
50	mjames	7301	#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /!< 0x00000001 /
		7302	#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /!< 0x00000002 /
		7303	#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /!< 0x00000004 /
		7304	#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /!< 0x00000008 /
		7305	#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /!< 0x00000010 /
		7306	#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /!< 0x00000020 /
		7307	#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /!< 0x00000040 /
30	mjames	7308
		7309	/* Legacy defines */
		7310	#define WWDG_CFR_W0 WWDG_CFR_W_0
		7311	#define WWDG_CFR_W1 WWDG_CFR_W_1
		7312	#define WWDG_CFR_W2 WWDG_CFR_W_2
		7313	#define WWDG_CFR_W3 WWDG_CFR_W_3
		7314	#define WWDG_CFR_W4 WWDG_CFR_W_4
		7315	#define WWDG_CFR_W5 WWDG_CFR_W_5
		7316	#define WWDG_CFR_W6 WWDG_CFR_W_6
		7317
		7318	#define WWDG_CFR_WDGTB_Pos (7U)
50	mjames	7319	#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /!< 0x00000180 /
30	mjames	7320	#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /!< WDGTB[1:0] bits (Timer Base) /
50	mjames	7321	#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /!< 0x00000080 /
		7322	#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /!< 0x00000100 /
30	mjames	7323
		7324	/* Legacy defines */
		7325	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
		7326	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
		7327
		7328	#define WWDG_CFR_EWI_Pos (9U)
50	mjames	7329	#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /!< 0x00000200 /
30	mjames	7330	#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /!< Early Wakeup Interrupt /
		7331
		7332	/***************** Bit definition for WWDG_SR register ******************/
		7333	#define WWDG_SR_EWIF_Pos (0U)
50	mjames	7334	#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /!< 0x00000001 /
30	mjames	7335	#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /!< Early Wakeup Interrupt Flag /
		7336
		7337	/**
		7338	* @}
		7339	*/
		7340	/** @addtogroup Exported_macro
		7341	* @{
		7342	*/
		7343
		7344	/**************************** ADC Instances *******************************/
		7345	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		7346
		7347	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
		7348
		7349	/****************************** COMP Instances ****************************/
		7350	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
		7351	((INSTANCE) == COMP2))
		7352
		7353	#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
		7354
		7355	/**************************** CRC Instances *******************************/
		7356	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
		7357
		7358	/**************************** DAC Instances *******************************/
		7359	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
		7360
		7361	/**************************** DMA Instances *******************************/
		7362	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
		7363	((INSTANCE) == DMA1_Channel2) \|\| \
		7364	((INSTANCE) == DMA1_Channel3) \|\| \
		7365	((INSTANCE) == DMA1_Channel4) \|\| \
		7366	((INSTANCE) == DMA1_Channel5) \|\| \
		7367	((INSTANCE) == DMA1_Channel6) \|\| \
		7368	((INSTANCE) == DMA1_Channel7))
		7369
		7370	/***************************** GPIO Instances *****************************/
		7371	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
		7372	((INSTANCE) == GPIOB) \|\| \
		7373	((INSTANCE) == GPIOC) \|\| \
		7374	((INSTANCE) == GPIOD) \|\| \
		7375	((INSTANCE) == GPIOE) \|\| \
		7376	((INSTANCE) == GPIOH))
		7377
		7378	/************************** GPIO Alternate Function Instances *************/
		7379	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		7380
		7381	/************************** GPIO Lock Instances ***************************/
		7382	/* On L1, all GPIO Bank support the Lock mechanism */
		7383	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		7384
		7385	/****************************** I2C Instances *****************************/
		7386	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
		7387	((INSTANCE) == I2C2))
		7388
		7389	/**************************** SMBUS Instances *****************************/
		7390	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
		7391
		7392	/**************************** IWDG Instances ******************************/
		7393	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
		7394
		7395	/**************************** RTC Instances *******************************/
		7396	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
		7397
		7398	/****************************** SPI Instances *****************************/
		7399	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
		7400	((INSTANCE) == SPI2))
		7401
		7402	/**************************** TIM Instances *******************************/
		7403
		7404	#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7405	((INSTANCE) == TIM3) \|\| \
		7406	((INSTANCE) == TIM4) \|\| \
		7407	((INSTANCE) == TIM6) \|\| \
		7408	((INSTANCE) == TIM7) \|\| \
		7409	((INSTANCE) == TIM9) \|\| \
		7410	((INSTANCE) == TIM10) \|\| \
		7411	((INSTANCE) == TIM11))
		7412
		7413	#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7414	((INSTANCE) == TIM3) \|\| \
		7415	((INSTANCE) == TIM4) \|\| \
		7416	((INSTANCE) == TIM9) \|\| \
		7417	((INSTANCE) == TIM10) \|\| \
		7418	((INSTANCE) == TIM11))
		7419
		7420	#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7421	((INSTANCE) == TIM3) \|\| \
		7422	((INSTANCE) == TIM4) \|\| \
		7423	((INSTANCE) == TIM9))
		7424
		7425	#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7426	((INSTANCE) == TIM3) \|\| \
		7427	((INSTANCE) == TIM4))
		7428
		7429	#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7430	((INSTANCE) == TIM3) \|\| \
		7431	((INSTANCE) == TIM4))
		7432
		7433	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7434	((INSTANCE) == TIM3) \|\| \
		7435	((INSTANCE) == TIM4) \|\| \
		7436	((INSTANCE) == TIM9))
		7437
		7438	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7439	((INSTANCE) == TIM3) \|\| \
		7440	((INSTANCE) == TIM4) \|\| \
		7441	((INSTANCE) == TIM9) \|\| \
		7442	((INSTANCE) == TIM10) \|\| \
		7443	((INSTANCE) == TIM11))
		7444
		7445	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7446	((INSTANCE) == TIM3) \|\| \
		7447	((INSTANCE) == TIM4) \|\| \
		7448	((INSTANCE) == TIM9))
		7449
		7450	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7451	((INSTANCE) == TIM3) \|\| \
		7452	((INSTANCE) == TIM4) \|\| \
		7453	((INSTANCE) == TIM9))
		7454
		7455	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7456	((INSTANCE) == TIM3) \|\| \
		7457	((INSTANCE) == TIM4))
		7458
		7459	#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7460	((INSTANCE) == TIM3) \|\| \
		7461	((INSTANCE) == TIM4))
		7462
		7463	#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7464	((INSTANCE) == TIM3) \|\| \
		7465	((INSTANCE) == TIM4) \|\| \
		7466	((INSTANCE) == TIM6) \|\| \
		7467	((INSTANCE) == TIM7) \|\| \
		7468	((INSTANCE) == TIM9))
		7469
		7470	#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7471	((INSTANCE) == TIM3) \|\| \
		7472	((INSTANCE) == TIM4) \|\| \
		7473	((INSTANCE) == TIM9))
		7474
50	mjames	7475	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
		7476
30	mjames	7477	#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7478	((INSTANCE) == TIM3) \|\| \
		7479	((INSTANCE) == TIM4))
		7480
		7481	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
		7482	((((INSTANCE) == TIM2) && \
		7483	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7484	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7485	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7486	((CHANNEL) == TIM_CHANNEL_4))) \
		7487	\|\| \
		7488	(((INSTANCE) == TIM3) && \
		7489	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7490	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7491	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7492	((CHANNEL) == TIM_CHANNEL_4))) \
		7493	\|\| \
		7494	(((INSTANCE) == TIM4) && \
		7495	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7496	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		7497	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		7498	((CHANNEL) == TIM_CHANNEL_4))) \
		7499	\|\| \
		7500	(((INSTANCE) == TIM9) && \
		7501	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		7502	((CHANNEL) == TIM_CHANNEL_2))) \
		7503	\|\| \
		7504	(((INSTANCE) == TIM10) && \
		7505	(((CHANNEL) == TIM_CHANNEL_1))) \
		7506	\|\| \
		7507	(((INSTANCE) == TIM11) && \
		7508	(((CHANNEL) == TIM_CHANNEL_1))))
		7509
		7510	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7511	((INSTANCE) == TIM3) \|\| \
		7512	((INSTANCE) == TIM4) \|\| \
		7513	((INSTANCE) == TIM9) \|\| \
		7514	((INSTANCE) == TIM10) \|\| \
		7515	((INSTANCE) == TIM11))
		7516
		7517	#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7518	((INSTANCE) == TIM3) \|\| \
		7519	((INSTANCE) == TIM4) \|\| \
		7520	((INSTANCE) == TIM6) \|\| \
		7521	((INSTANCE) == TIM7))
		7522
		7523	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7524	((INSTANCE) == TIM3) \|\| \
		7525	((INSTANCE) == TIM4))
		7526
		7527	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7528	((INSTANCE) == TIM3) \|\| \
		7529	((INSTANCE) == TIM4))
		7530
		7531	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		7532	((INSTANCE) == TIM3) \|\| \
		7533	((INSTANCE) == TIM4))
		7534
		7535	#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM9) \|\| \
		7536	((INSTANCE) == TIM10) \|\| \
		7537	((INSTANCE) == TIM11))
		7538
		7539	/****************** USART Instances : Synchronous mode ********************/
		7540	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7541	((INSTANCE) == USART2) \|\| \
		7542	((INSTANCE) == USART3))
		7543
		7544	/****************** UART Instances : Asynchronous mode ********************/
		7545	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7546	((INSTANCE) == USART2) \|\| \
		7547	((INSTANCE) == USART3))
		7548
		7549	/****************** UART Instances : Half-Duplex mode ********************/
		7550	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7551	((INSTANCE) == USART2) \|\| \
		7552	((INSTANCE) == USART3))
		7553
		7554	/****************** UART Instances : LIN mode ********************/
		7555	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7556	((INSTANCE) == USART2) \|\| \
		7557	((INSTANCE) == USART3))
		7558
		7559	/**************** UART Instances : Hardware Flow control ******************/
		7560	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7561	((INSTANCE) == USART2) \|\| \
		7562	((INSTANCE) == USART3))
		7563
		7564	/******************* UART Instances : Smard card mode *********************/
		7565	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7566	((INSTANCE) == USART2) \|\| \
		7567	((INSTANCE) == USART3))
		7568
		7569	/********************* UART Instances : IRDA mode *************************/
		7570	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7571	((INSTANCE) == USART2) \|\| \
		7572	((INSTANCE) == USART3))
		7573
		7574	/*************** UART Instances : Multi-Processor mode ********************/
		7575	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		7576	((INSTANCE) == USART2) \|\| \
		7577	((INSTANCE) == USART3))
		7578
		7579	/**************************** WWDG Instances ******************************/
		7580	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
		7581
		7582	/**************************** USB Instances ******************************/
		7583	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
50	mjames	7584	#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
30	mjames	7585
		7586	/**
		7587	* @}
		7588	*/
		7589
		7590	/******************************************************************************/
		7591	/* For a painless codes migration between the STM32L1xx device product */
		7592	/* lines, the aliases defined below are put in place to overcome the */
		7593	/* differences in the interrupt handlers and IRQn definitions. */
		7594	/* No need to update developed interrupt code when moving across */
		7595	/* product lines within the same STM32L1 Family */
		7596	/******************************************************************************/
		7597
		7598	/* Aliases for __IRQn */
		7599
		7600	/* Aliases for __IRQHandler */
		7601
		7602	/**
		7603	* @}
		7604	*/
		7605
		7606	/**
		7607	* @}
		7608	*/
		7609
		7610	#ifdef __cplusplus
		7611	}
		7612	#endif /* __cplusplus */
		7613
		7614	#endif /* __STM32L151xB_H */
		7615
		7616
		7617
		7618	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/branches/Dashboard_L152_v2/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xb.h – Rev 61