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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 56 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_ll_fsmc.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief FSMC Low Layer HAL module driver. |
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| 6 | * |
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| 7 | * This file provides firmware functions to manage the following |
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| 8 | * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: |
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| 9 | * + Initialization/de-initialization functions |
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| 10 | * + Peripheral Control functions |
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| 11 | * + Peripheral State functions |
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| 12 | * |
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| 13 | @verbatim |
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| 14 | ============================================================================= |
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| 15 | ##### FSMC peripheral features ##### |
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| 16 | ============================================================================= |
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| 17 | [..] The Flexible static memory controller (FSMC) includes following memory controllers: |
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| 18 | (+) The NOR/PSRAM memory controller |
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| 19 | |||
| 20 | [..] The FSMC functional block makes the interface with synchronous and asynchronous static |
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| 21 | memories. Its main purposes are: |
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| 22 | (+) to translate AHB transactions into the appropriate external device protocol. |
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| 23 | (+) to meet the access time requirements of the external memory devices. |
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| 24 | |||
| 25 | [..] All external memories share the addresses, data and control signals with the controller. |
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| 26 | Each external device is accessed by means of a unique Chip Select. The FSMC performs |
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| 27 | only one access at a time to an external device. |
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| 28 | The main features of the FSMC controller are the following: |
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| 29 | (+) Interface with static-memory mapped devices including: |
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| 30 | (++) Static random access memory (SRAM). |
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| 31 | (++) NOR Flash memory. |
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| 32 | (++) PSRAM (4 memory banks). |
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| 33 | (+) Independent Chip Select control for each memory bank |
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| 34 | (+) Independent configuration for each memory bank |
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| 35 | |||
| 36 | @endverbatim |
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| 37 | ****************************************************************************** |
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| 38 | * @attention |
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| 39 | * |
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| 40 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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| 41 | * All rights reserved.</center></h2> |
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| 42 | * |
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| 43 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 44 | * the "License"; You may not use this file except in compliance with the |
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| 45 | * License. You may obtain a copy of the License at: |
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| 46 | * opensource.org/licenses/BSD-3-Clause |
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| 47 | * |
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| 48 | ****************************************************************************** |
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| 49 | */ |
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| 50 | |||
| 51 | /* Includes ------------------------------------------------------------------*/ |
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| 52 | #include "stm32l1xx_hal.h" |
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| 53 | |||
| 54 | /** @addtogroup STM32L1xx_HAL_Driver |
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| 55 | * @{ |
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| 56 | */ |
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| 57 | |||
| 58 | #if defined(FSMC_BANK1) |
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| 59 | |||
| 60 | #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) |
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| 61 | |||
| 62 | /** @defgroup FSMC_LL FSMC Low Layer |
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| 63 | * @brief FSMC driver modules |
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| 64 | * @{ |
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| 65 | */ |
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| 66 | |||
| 67 | /* Private typedef -----------------------------------------------------------*/ |
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| 68 | /* Private define ------------------------------------------------------------*/ |
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| 69 | /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants |
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| 70 | * @{ |
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| 71 | */ |
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| 72 | |||
| 73 | /* ----------------------- FSMC registers bit mask --------------------------- */ |
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| 74 | /* --- BCR Register ---*/ |
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| 75 | /* BCR register clear mask */ |
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| 76 | #define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | \ |
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| 77 | FSMC_BCRx_MTYP | FSMC_BCRx_MWID | \ |
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| 78 | FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | \ |
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| 79 | FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \ |
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| 80 | FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | \ |
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| 81 | FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | \ |
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| 82 | FSMC_BCRx_CBURSTRW)) |
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| 83 | /* --- BTR Register ---*/ |
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| 84 | /* BTR register clear mask */ |
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| 85 | #define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\ |
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| 86 | FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\ |
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| 87 | FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\ |
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| 88 | FSMC_BTRx_ACCMOD)) |
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| 89 | |||
| 90 | /* --- BWTR Register ---*/ |
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| 91 | /* BWTR register clear mask */ |
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| 92 | #define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \ |
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| 93 | FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \ |
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| 94 | FSMC_BWTRx_BUSTURN)) |
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| 95 | |||
| 96 | /** |
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| 97 | * @} |
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| 98 | */ |
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| 99 | |||
| 100 | /* Private macro -------------------------------------------------------------*/ |
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| 101 | /** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros |
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| 102 | * @{ |
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| 103 | */ |
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| 104 | |||
| 105 | /** |
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| 106 | * @} |
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| 107 | */ |
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| 108 | |||
| 109 | /* Private variables ---------------------------------------------------------*/ |
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| 110 | /* Private function prototypes -----------------------------------------------*/ |
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| 111 | /* Exported functions --------------------------------------------------------*/ |
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| 112 | |||
| 113 | /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions |
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| 114 | * @{ |
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| 115 | */ |
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| 116 | |||
| 117 | /** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions |
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| 118 | * @brief NORSRAM Controller functions |
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| 119 | * |
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| 120 | @verbatim |
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| 121 | ============================================================================== |
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| 122 | ##### How to use NORSRAM device driver ##### |
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| 123 | ============================================================================== |
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| 124 | |||
| 125 | [..] |
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| 126 | This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order |
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| 127 | to run the NORSRAM external devices. |
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| 128 | |||
| 129 | (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() |
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| 130 | (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() |
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| 131 | (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() |
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| 132 | (+) FSMC NORSRAM bank extended timing configuration using the function |
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| 133 | FSMC_NORSRAM_Extended_Timing_Init() |
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| 134 | (+) FSMC NORSRAM bank enable/disable write operation using the functions |
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| 135 | FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() |
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| 136 | |||
| 137 | |||
| 138 | @endverbatim |
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| 139 | * @{ |
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| 140 | */ |
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| 141 | |||
| 142 | /** @defgroup FSMC_NORSRAM_Group1 Initialization/de-initialization functions |
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| 143 | * @brief Initialization and Configuration functions |
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| 144 | * |
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| 145 | @verbatim |
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| 146 | ============================================================================== |
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| 147 | ##### Initialization and de_initialization functions ##### |
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| 148 | ============================================================================== |
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| 149 | [..] |
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| 150 | This section provides functions allowing to: |
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| 151 | (+) Initialize and configure the FSMC NORSRAM interface |
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| 152 | (+) De-initialize the FSMC NORSRAM interface |
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| 153 | (+) Configure the FSMC clock and associated GPIOs |
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| 154 | |||
| 155 | @endverbatim |
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| 156 | * @{ |
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| 157 | */ |
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| 158 | |||
| 159 | /** |
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| 160 | * @brief Initialize the FSMC_NORSRAM device according to the specified |
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| 161 | * control parameters in the FSMC_NORSRAM_InitTypeDef |
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| 162 | * @param Device Pointer to NORSRAM device instance |
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| 163 | * @param Init Pointer to NORSRAM Initialization structure |
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| 164 | * @retval HAL status |
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| 165 | */ |
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| 166 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init) |
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| 167 | { |
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| 168 | /* Check the parameters */ |
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| 169 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
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| 170 | assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); |
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| 171 | assert_param(IS_FSMC_MUX(Init->DataAddressMux)); |
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| 172 | assert_param(IS_FSMC_MEMORY(Init->MemoryType)); |
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| 173 | assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
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| 174 | assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); |
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| 175 | assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
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| 176 | assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); |
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| 177 | assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
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| 178 | assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); |
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| 179 | assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); |
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| 180 | assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); |
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| 181 | assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); |
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| 182 | assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); |
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| 183 | |||
| 184 | /* Disable NORSRAM Device */ |
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| 185 | __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); |
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| 186 | |||
| 187 | /* Set NORSRAM device control parameters */ |
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| 188 | if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR) |
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| 189 | { |
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| 190 | MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE |
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| 191 | | Init->DataAddressMux |
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| 192 | | Init->MemoryType |
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| 193 | | Init->MemoryDataWidth |
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| 194 | | Init->BurstAccessMode |
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| 195 | | Init->WaitSignalPolarity |
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| 196 | | Init->WrapMode |
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| 197 | | Init->WaitSignalActive |
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| 198 | | Init->WriteOperation |
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| 199 | | Init->WaitSignal |
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| 200 | | Init->ExtendedMode |
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| 201 | | Init->AsynchronousWait |
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| 202 | | Init->WriteBurst |
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| 203 | ) |
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| 204 | ); |
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| 205 | } |
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| 206 | else |
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| 207 | { |
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| 208 | MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE |
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| 209 | | Init->DataAddressMux |
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| 210 | | Init->MemoryType |
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| 211 | | Init->MemoryDataWidth |
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| 212 | | Init->BurstAccessMode |
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| 213 | | Init->WaitSignalPolarity |
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| 214 | | Init->WrapMode |
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| 215 | | Init->WaitSignalActive |
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| 216 | | Init->WriteOperation |
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| 217 | | Init->WaitSignal |
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| 218 | | Init->ExtendedMode |
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| 219 | | Init->AsynchronousWait |
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| 220 | | Init->WriteBurst |
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| 221 | ) |
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| 222 | ); |
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| 223 | } |
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| 224 | |||
| 225 | return HAL_OK; |
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| 226 | } |
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| 227 | |||
| 228 | |||
| 229 | /** |
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| 230 | * @brief DeInitialize the FSMC_NORSRAM peripheral |
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| 231 | * @param Device Pointer to NORSRAM device instance |
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| 232 | * @param ExDevice Pointer to NORSRAM extended mode device instance |
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| 233 | * @param Bank NORSRAM bank number |
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| 234 | * @retval HAL status |
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| 235 | */ |
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| 236 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
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| 237 | { |
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| 238 | /* Check the parameters */ |
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| 239 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
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| 240 | assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
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| 241 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
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| 242 | |||
| 243 | /* Disable the FSMC_NORSRAM device */ |
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| 244 | __FSMC_NORSRAM_DISABLE(Device, Bank); |
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| 245 | |||
| 246 | /* De-initialize the FSMC_NORSRAM device */ |
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| 247 | /* FSMC_NORSRAM_BANK1 */ |
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| 248 | if (Bank == FSMC_NORSRAM_BANK1) |
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| 249 | { |
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| 250 | Device->BTCR[Bank] = 0x000030DB; |
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| 251 | } |
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| 252 | /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ |
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| 253 | else |
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| 254 | { |
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| 255 | Device->BTCR[Bank] = 0x000030D2; |
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| 256 | } |
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| 257 | |||
| 258 | Device->BTCR[Bank + 1] = 0x0FFFFFFF; |
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| 259 | ExDevice->BWTR[Bank] = 0x0FFFFFFF; |
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| 260 | |||
| 261 | return HAL_OK; |
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| 262 | } |
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| 263 | |||
| 264 | |||
| 265 | /** |
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| 266 | * @brief Initialize the FSMC_NORSRAM Timing according to the specified |
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| 267 | * parameters in the FSMC_NORSRAM_TimingTypeDef |
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| 268 | * @param Device Pointer to NORSRAM device instance |
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| 269 | * @param Timing Pointer to NORSRAM Timing structure |
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| 270 | * @param Bank NORSRAM bank number |
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| 271 | * @retval HAL status |
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| 272 | */ |
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| 273 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
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| 274 | { |
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| 275 | /* Check the parameters */ |
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| 276 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
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| 277 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
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| 278 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
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| 279 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); |
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| 280 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
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| 281 | assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); |
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| 282 | assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); |
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| 283 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); |
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| 284 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
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| 285 | |||
| 286 | /* Set FSMC_NORSRAM device timing parameters */ |
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| 287 | MODIFY_REG(Device->BTCR[Bank + 1], \ |
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| 288 | BTR_CLEAR_MASK, \ |
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| 289 | (uint32_t)(Timing->AddressSetupTime | \ |
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| 290 | ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) | \ |
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| 291 | ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) | \ |
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| 292 | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) | \ |
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| 293 | (((Timing->CLKDivision) - 1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \ |
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| 294 | (((Timing->DataLatency) - 2) << POSITION_VAL(FSMC_BTRx_DATLAT)) | \ |
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| 295 | (Timing->AccessMode))); |
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| 296 | |||
| 297 | return HAL_OK; |
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| 298 | } |
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| 299 | |||
| 300 | /** |
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| 301 | * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified |
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| 302 | * parameters in the FSMC_NORSRAM_TimingTypeDef |
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| 303 | * @param Device Pointer to NORSRAM device instance |
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| 304 | * @param Timing Pointer to NORSRAM Timing structure |
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| 305 | * @param Bank NORSRAM bank number |
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| 306 | * @param ExtendedMode FSMC Extended Mode |
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| 307 | * This parameter can be one of the following values: |
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| 308 | * @arg FSMC_EXTENDED_MODE_DISABLE |
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| 309 | * @arg FSMC_EXTENDED_MODE_ENABLE |
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| 310 | * @retval HAL status |
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| 311 | */ |
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| 312 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
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| 313 | { |
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| 314 | /* Check the parameters */ |
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| 315 | assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); |
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| 316 | |||
| 317 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
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| 318 | if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) |
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| 319 | { |
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| 320 | /* Check the parameters */ |
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| 321 | assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); |
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| 322 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
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| 323 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
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| 324 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); |
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| 325 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
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| 326 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); |
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| 327 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
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| 328 | |||
| 329 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
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| 330 | MODIFY_REG(Device->BWTR[Bank], \ |
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| 331 | BWTR_CLEAR_MASK, \ |
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| 332 | (uint32_t)(Timing->AddressSetupTime | \ |
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| 333 | ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \ |
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| 334 | ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \ |
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| 335 | Timing->AccessMode | \ |
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| 336 | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN)))); |
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| 337 | } |
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| 338 | else |
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| 339 | { |
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| 340 | Device->BWTR[Bank] = 0x0FFFFFFF; |
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| 341 | } |
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| 342 | |||
| 343 | return HAL_OK; |
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| 344 | } |
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| 345 | |||
| 346 | |||
| 347 | /** |
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| 348 | * @} |
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| 349 | */ |
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| 350 | |||
| 351 | |||
| 352 | /** @defgroup FSMC_NORSRAM_Group2 Control functions |
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| 353 | * @brief management functions |
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| 354 | * |
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| 355 | @verbatim |
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| 356 | ============================================================================== |
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| 357 | ##### FSMC_NORSRAM Control functions ##### |
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| 358 | ============================================================================== |
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| 359 | [..] |
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| 360 | This subsection provides a set of functions allowing to control dynamically |
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| 361 | the FSMC NORSRAM interface. |
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| 362 | |||
| 363 | @endverbatim |
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| 364 | * @{ |
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| 365 | */ |
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| 366 | |||
| 367 | /** |
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| 368 | * @brief Enables dynamically FSMC_NORSRAM write operation. |
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| 369 | * @param Device Pointer to NORSRAM device instance |
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| 370 | * @param Bank NORSRAM bank number |
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| 371 | * @retval HAL status |
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| 372 | */ |
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| 373 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
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| 374 | { |
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| 375 | /* Check the parameters */ |
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| 376 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
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| 377 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
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| 378 | |||
| 379 | /* Enable write operation */ |
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| 380 | SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); |
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| 381 | |||
| 382 | return HAL_OK; |
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| 383 | } |
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| 384 | |||
| 385 | /** |
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| 386 | * @brief Disables dynamically FSMC_NORSRAM write operation. |
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| 387 | * @param Device Pointer to NORSRAM device instance |
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| 388 | * @param Bank NORSRAM bank number |
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| 389 | * @retval HAL status |
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| 390 | */ |
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| 391 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
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| 392 | { |
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| 393 | /* Check the parameters */ |
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| 394 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
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| 395 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
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| 396 | |||
| 397 | /* Disable write operation */ |
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| 398 | CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); |
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| 399 | |||
| 400 | return HAL_OK; |
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| 401 | } |
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| 402 | |||
| 403 | /** |
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| 404 | * @} |
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| 405 | */ |
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| 406 | |||
| 407 | /** |
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| 408 | * @} |
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| 409 | */ |
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| 410 | /** |
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| 411 | * @} |
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| 412 | */ |
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| 413 | |||
| 414 | /** |
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| 415 | * @} |
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| 416 | */ |
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| 417 | |||
| 418 | #endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) */ |
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| 419 | |||
| 420 | #endif /* FSMC_BANK1 */ |
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| 421 | |||
| 422 | /** |
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| 423 | * @} |
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| 424 | */ |
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| 425 | |||
| 426 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |