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| Rev | Author | Line No. | Line |
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| 56 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_ll_adc.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief ADC LL module driver |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | #if defined(USE_FULL_LL_DRIVER) |
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| 20 | |||
| 21 | /* Includes ------------------------------------------------------------------*/ |
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| 22 | #include "stm32l1xx_ll_adc.h" |
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| 23 | #include "stm32l1xx_ll_bus.h" |
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| 24 | |||
| 25 | #ifdef USE_FULL_ASSERT |
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| 26 | #include "stm32_assert.h" |
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| 27 | #else |
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| 28 | #define assert_param(expr) ((void)0U) |
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| 29 | #endif |
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| 30 | |||
| 31 | /** @addtogroup STM32L1xx_LL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | #if defined (ADC1) |
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| 36 | |||
| 37 | /** @addtogroup ADC_LL ADC |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 41 | /* Private types -------------------------------------------------------------*/ |
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| 42 | /* Private variables ---------------------------------------------------------*/ |
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| 43 | /* Private constants ---------------------------------------------------------*/ |
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| 44 | /* Private macros ------------------------------------------------------------*/ |
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| 45 | |||
| 46 | /** @addtogroup ADC_LL_Private_Macros |
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| 47 | * @{ |
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| 48 | */ |
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| 49 | |||
| 50 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 51 | /* common to several ADC instances. */ |
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| 52 | #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ |
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| 53 | ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ |
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| 54 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ |
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| 55 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ |
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| 56 | ) |
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| 57 | |||
| 58 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 59 | /* ADC instance. */ |
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| 60 | #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ |
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| 61 | ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ |
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| 62 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ |
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| 63 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ |
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| 64 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ |
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| 65 | ) |
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| 66 | |||
| 67 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
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| 68 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
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| 69 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
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| 70 | ) |
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| 71 | |||
| 72 | #define IS_LL_ADC_LOW_POWER_AUTOWAIT(__LOW_POWER__) \ |
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| 73 | ( ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_NONE) \ |
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| 74 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ |
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| 75 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES) \ |
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| 76 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES) \ |
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| 77 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES) \ |
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| 78 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES) \ |
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| 79 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES) \ |
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| 80 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES) \ |
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| 81 | ) |
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| 82 | |||
| 83 | #define IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(__LOW_POWER__) \ |
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| 84 | ( ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_NONE) \ |
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| 85 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE) \ |
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| 86 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE) \ |
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| 87 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES) \ |
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| 88 | ) |
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| 89 | |||
| 90 | #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ |
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| 91 | ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
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| 92 | || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
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| 93 | ) |
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| 94 | |||
| 95 | #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ |
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| 96 | ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
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| 97 | || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
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| 98 | ) |
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| 99 | |||
| 100 | #define IS_LL_ADC_CHANNELS_BANK(__CHANNELS_BANK__) \ |
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| 101 | ( ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_A) \ |
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| 102 | || ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_B) \ |
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| 103 | ) |
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| 104 | |||
| 105 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 106 | /* ADC group regular */ |
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| 107 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
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| 108 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
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| 109 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ |
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| 110 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ |
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| 111 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
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| 112 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
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| 113 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ |
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| 114 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH3) \ |
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| 115 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ |
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| 116 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
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| 117 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ |
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| 118 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_CH2) \ |
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| 119 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_TRGO) \ |
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| 120 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
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| 121 | ) |
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| 122 | |||
| 123 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
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| 124 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
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| 125 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
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| 126 | ) |
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| 127 | |||
| 128 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
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| 129 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
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| 130 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ |
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| 131 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
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| 132 | ) |
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| 133 | |||
| 134 | #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ |
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| 135 | ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ |
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| 136 | || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ |
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| 137 | ) |
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| 138 | |||
| 139 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
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| 140 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
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| 141 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
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| 142 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
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| 143 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
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| 144 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
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| 145 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
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| 146 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
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| 147 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
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| 148 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
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| 149 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
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| 150 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
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| 151 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
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| 152 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
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| 153 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
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| 154 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
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| 155 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
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| 156 | ) |
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| 157 | |||
| 158 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
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| 159 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
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| 160 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
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| 161 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
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| 162 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
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| 163 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
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| 164 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
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| 165 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
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| 166 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
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| 167 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
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| 168 | ) |
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| 169 | |||
| 170 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 171 | /* ADC group injected */ |
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| 172 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
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| 173 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
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| 174 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_CH1) \ |
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| 175 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_TRGO) \ |
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| 176 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
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| 177 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
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| 178 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
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| 179 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
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| 180 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ |
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| 181 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ |
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| 182 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ |
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| 183 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM10_CH1) \ |
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| 184 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ |
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| 185 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
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| 186 | ) |
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| 187 | |||
| 188 | #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ |
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| 189 | ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ |
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| 190 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ |
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| 191 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ |
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| 192 | ) |
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| 193 | |||
| 194 | #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
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| 195 | ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
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| 196 | || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
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| 197 | ) |
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| 198 | |||
| 199 | #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
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| 200 | ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
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| 201 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
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| 202 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
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| 203 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
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| 204 | ) |
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| 205 | |||
| 206 | #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
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| 207 | ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
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| 208 | || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
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| 209 | ) |
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| 210 | |||
| 211 | /** |
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| 212 | * @} |
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| 213 | */ |
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| 214 | |||
| 215 | |||
| 216 | /* Private function prototypes -----------------------------------------------*/ |
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| 217 | |||
| 218 | /* Exported functions --------------------------------------------------------*/ |
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| 219 | /** @addtogroup ADC_LL_Exported_Functions |
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| 220 | * @{ |
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| 221 | */ |
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| 222 | |||
| 223 | /** @addtogroup ADC_LL_EF_Init |
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| 224 | * @{ |
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| 225 | */ |
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| 226 | |||
| 227 | /** |
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| 228 | * @brief De-initialize registers of all ADC instances belonging to |
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| 229 | * the same ADC common instance to their default reset values. |
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| 230 | * @param ADCxy_COMMON ADC common instance |
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| 231 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
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| 232 | * @retval An ErrorStatus enumeration value: |
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| 233 | * - SUCCESS: ADC common registers are de-initialized |
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| 234 | * - ERROR: not applicable |
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| 235 | */ |
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| 236 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
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| 237 | { |
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| 238 | /* Check the parameters */ |
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| 239 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
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| 240 | |||
| 241 | /* Force reset of ADC clock (core clock) */ |
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| 242 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); |
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| 243 | |||
| 244 | /* Release reset of ADC clock (core clock) */ |
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| 245 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); |
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| 246 | |||
| 247 | return SUCCESS; |
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| 248 | } |
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| 249 | |||
| 250 | /** |
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| 251 | * @brief Initialize some features of ADC common parameters |
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| 252 | * (all ADC instances belonging to the same ADC common instance) |
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| 253 | * and multimode (for devices with several ADC instances available). |
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| 254 | * @note The setting of ADC common parameters is conditioned to |
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| 255 | * ADC instances state: |
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| 256 | * All ADC instances belonging to the same ADC common instance |
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| 257 | * must be disabled. |
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| 258 | * @param ADCxy_COMMON ADC common instance |
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| 259 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
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| 260 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
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| 261 | * @retval An ErrorStatus enumeration value: |
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| 262 | * - SUCCESS: ADC common registers are initialized |
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| 263 | * - ERROR: ADC common registers are not initialized |
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| 264 | */ |
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| 265 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
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| 266 | { |
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| 267 | ErrorStatus status = SUCCESS; |
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| 268 | |||
| 269 | /* Check the parameters */ |
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| 270 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
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| 271 | assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); |
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| 272 | |||
| 273 | /* Note: Hardware constraint (refer to description of functions */ |
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| 274 | /* "LL_ADC_SetCommonXXX()": */ |
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| 275 | /* On this STM32 serie, setting of these features is conditioned to */ |
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| 276 | /* ADC state: */ |
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| 277 | /* All ADC instances of the ADC common group must be disabled. */ |
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| 278 | if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) |
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| 279 | { |
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| 280 | /* Configuration of ADC hierarchical scope: */ |
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| 281 | /* - common to several ADC */ |
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| 282 | /* (all ADC instances belonging to the same ADC common instance) */ |
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| 283 | /* - Set ADC clock (conversion clock) */ |
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| 284 | LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); |
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| 285 | } |
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| 286 | else |
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| 287 | { |
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| 288 | /* Initialization error: One or several ADC instances belonging to */ |
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| 289 | /* the same ADC common instance are not disabled. */ |
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| 290 | status = ERROR; |
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| 291 | } |
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| 292 | |||
| 293 | return status; |
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| 294 | } |
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| 295 | |||
| 296 | /** |
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| 297 | * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
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| 298 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
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| 299 | * whose fields will be set to default values. |
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| 300 | * @retval None |
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| 301 | */ |
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| 302 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
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| 303 | { |
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| 304 | /* Set ADC_CommonInitStruct fields to default values */ |
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| 305 | /* Set fields of ADC common */ |
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| 306 | /* (all ADC instances belonging to the same ADC common instance) */ |
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| 307 | ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; |
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| 308 | |||
| 309 | } |
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| 310 | |||
| 311 | /** |
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| 312 | * @brief De-initialize registers of the selected ADC instance |
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| 313 | * to their default reset values. |
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| 314 | * @note To reset all ADC instances quickly (perform a hard reset), |
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| 315 | * use function @ref LL_ADC_CommonDeInit(). |
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| 316 | * @param ADCx ADC instance |
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| 317 | * @retval An ErrorStatus enumeration value: |
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| 318 | * - SUCCESS: ADC registers are de-initialized |
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| 319 | * - ERROR: ADC registers are not de-initialized |
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| 320 | */ |
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| 321 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
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| 322 | { |
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| 323 | ErrorStatus status = SUCCESS; |
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| 324 | |||
| 325 | /* Check the parameters */ |
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| 326 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
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| 327 | |||
| 328 | /* Disable ADC instance if not already disabled. */ |
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| 329 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
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| 330 | { |
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| 331 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
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| 332 | /* have an external trigger event occurring during the conversion stop */ |
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| 333 | /* ADC disable process. */ |
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| 334 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
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| 335 | |||
| 336 | /* Set ADC group injected trigger source to SW start to ensure to not */ |
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| 337 | /* have an external trigger event occurring during the conversion stop */ |
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| 338 | /* ADC disable process. */ |
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| 339 | LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
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| 340 | |||
| 341 | /* Disable the ADC instance */ |
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| 342 | LL_ADC_Disable(ADCx); |
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| 343 | } |
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| 344 | |||
| 345 | /* Check whether ADC state is compliant with expected state */ |
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| 346 | /* (hardware requirements of bits state to reset registers below) */ |
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| 347 | if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) |
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| 348 | { |
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| 349 | /* ========== Reset ADC registers ========== */ |
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| 350 | /* Reset register SR */ |
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| 351 | CLEAR_BIT(ADCx->SR, |
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| 352 | ( LL_ADC_FLAG_STRT |
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| 353 | | LL_ADC_FLAG_JSTRT |
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| 354 | | LL_ADC_FLAG_EOCS |
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| 355 | | LL_ADC_FLAG_OVR |
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| 356 | | LL_ADC_FLAG_JEOS |
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| 357 | | LL_ADC_FLAG_AWD1 ) |
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| 358 | ); |
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| 359 | |||
| 360 | /* Reset register CR1 */ |
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| 361 | CLEAR_BIT(ADCx->CR1, |
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| 362 | ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN |
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| 363 | | ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD |
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| 364 | | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
||
| 365 | | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
||
| 366 | | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
||
| 367 | | ADC_CR1_AWDCH ) |
||
| 368 | ); |
||
| 369 | |||
| 370 | /* Reset register CR2 */ |
||
| 371 | #if defined(ADC_CR2_CFG) |
||
| 372 | CLEAR_BIT(ADCx->CR2, |
||
| 373 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
||
| 374 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
||
| 375 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
||
| 376 | | ADC_CR2_DDS | ADC_CR2_DMA | ADC_CR2_DELS |
||
| 377 | | ADC_CR2_CFG | ADC_CR2_CONT | ADC_CR2_ADON ) |
||
| 378 | ); |
||
| 379 | #else |
||
| 380 | CLEAR_BIT(ADCx->CR2, |
||
| 381 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
||
| 382 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
||
| 383 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
||
| 384 | | ADC_CR2_DDS | ADC_CR2_DMA | ADC_CR2_DELS |
||
| 385 | | ADC_CR2_CONT | ADC_CR2_ADON ) |
||
| 386 | ); |
||
| 387 | #endif /* ADC_CR2_CFG */ |
||
| 388 | |||
| 389 | /* Reset register SMPR1 */ |
||
| 390 | /* Note: On STM32L1, ADC channels 27, 28, 29, 30, 31 are not available */ |
||
| 391 | /* on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
||
| 392 | #if defined(ADC_SMPR0_SMP31) |
||
| 393 | CLEAR_BIT(ADCx->SMPR1, |
||
| 394 | ( ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 |
||
| 395 | | ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |
||
| 396 | | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
||
| 397 | | ADC_SMPR1_SMP20 ) |
||
| 398 | ); |
||
| 399 | #else |
||
| 400 | CLEAR_BIT(ADCx->SMPR1, |
||
| 401 | ( ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |
||
| 402 | | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
||
| 403 | | ADC_SMPR1_SMP20 ) |
||
| 404 | ); |
||
| 405 | #endif /* ADC_SMPR0_SMP31 */ |
||
| 406 | |||
| 407 | /* Reset register SMPR2 */ |
||
| 408 | CLEAR_BIT(ADCx->SMPR2, |
||
| 409 | ( ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 |
||
| 410 | | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 |
||
| 411 | | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 |
||
| 412 | | ADC_SMPR2_SMP10 ) |
||
| 413 | ); |
||
| 414 | |||
| 415 | /* Reset register SMPR3 */ |
||
| 416 | CLEAR_BIT(ADCx->SMPR3, |
||
| 417 | ( ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 |
||
| 418 | | ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 |
||
| 419 | | ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 |
||
| 420 | | ADC_SMPR3_SMP0 ) |
||
| 421 | ); |
||
| 422 | |||
| 423 | #if defined(ADC_SMPR0_SMP31) |
||
| 424 | /* Reset register SMPR0 */ |
||
| 425 | CLEAR_BIT(ADCx->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30)); |
||
| 426 | #endif /* ADC_SMPR0_SMP31 */ |
||
| 427 | |||
| 428 | /* Reset register JOFR1 */ |
||
| 429 | CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); |
||
| 430 | /* Reset register JOFR2 */ |
||
| 431 | CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); |
||
| 432 | /* Reset register JOFR3 */ |
||
| 433 | CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); |
||
| 434 | /* Reset register JOFR4 */ |
||
| 435 | CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); |
||
| 436 | |||
| 437 | /* Reset register HTR */ |
||
| 438 | SET_BIT(ADCx->HTR, ADC_HTR_HT); |
||
| 439 | /* Reset register LTR */ |
||
| 440 | CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); |
||
| 441 | |||
| 442 | /* Reset register SQR1 */ |
||
| 443 | CLEAR_BIT(ADCx->SQR1, |
||
| 444 | ( ADC_SQR1_L |
||
| 445 | #if defined(ADC_SQR1_SQ28) |
||
| 446 | | ADC_SQR1_SQ28 | ADC_SQR1_SQ27 |
||
| 447 | #endif |
||
| 448 | | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) |
||
| 449 | ); |
||
| 450 | |||
| 451 | /* Reset register SQR2 */ |
||
| 452 | CLEAR_BIT(ADCx->SQR2, |
||
| 453 | ( ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 |
||
| 454 | | ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19) |
||
| 455 | ); |
||
| 456 | |||
| 457 | /* Reset register SQR3 */ |
||
| 458 | CLEAR_BIT(ADCx->SQR3, |
||
| 459 | ( ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 |
||
| 460 | | ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13) |
||
| 461 | ); |
||
| 462 | |||
| 463 | /* Reset register SQR4 */ |
||
| 464 | CLEAR_BIT(ADCx->SQR4, |
||
| 465 | ( ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 |
||
| 466 | | ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 ) |
||
| 467 | ); |
||
| 468 | |||
| 469 | /* Reset register SQR5 */ |
||
| 470 | CLEAR_BIT(ADCx->SQR5, |
||
| 471 | ( ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 |
||
| 472 | | ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 ) |
||
| 473 | ); |
||
| 474 | |||
| 475 | |||
| 476 | /* Reset register JSQR */ |
||
| 477 | CLEAR_BIT(ADCx->JSQR, |
||
| 478 | ( ADC_JSQR_JL |
||
| 479 | | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
||
| 480 | | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
||
| 481 | ); |
||
| 482 | |||
| 483 | /* Reset register DR */ |
||
| 484 | /* bits in access mode read only, no direct reset applicable */ |
||
| 485 | |||
| 486 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
||
| 487 | /* bits in access mode read only, no direct reset applicable */ |
||
| 488 | |||
| 489 | /* Reset register CCR */ |
||
| 490 | CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); |
||
| 491 | } |
||
| 492 | |||
| 493 | return status; |
||
| 494 | } |
||
| 495 | |||
| 496 | /** |
||
| 497 | * @brief Initialize some features of ADC instance. |
||
| 498 | * @note These parameters have an impact on ADC scope: ADC instance. |
||
| 499 | * Affects both group regular and group injected (availability |
||
| 500 | * of ADC group injected depends on STM32 families). |
||
| 501 | * Refer to corresponding unitary functions into |
||
| 502 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
||
| 503 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
||
| 504 | * is conditioned to ADC state: |
||
| 505 | * ADC instance must be disabled. |
||
| 506 | * This condition is applied to all ADC features, for efficiency |
||
| 507 | * and compatibility over all STM32 families. However, the different |
||
| 508 | * features can be set under different ADC state conditions |
||
| 509 | * (setting possible with ADC enabled without conversion on going, |
||
| 510 | * ADC enabled with conversion on going, ...) |
||
| 511 | * Each feature can be updated afterwards with a unitary function |
||
| 512 | * and potentially with ADC in a different state than disabled, |
||
| 513 | * refer to description of each function for setting |
||
| 514 | * conditioned to ADC state. |
||
| 515 | * @note After using this function, some other features must be configured |
||
| 516 | * using LL unitary functions. |
||
| 517 | * The minimum configuration remaining to be done is: |
||
| 518 | * - Set ADC group regular or group injected sequencer: |
||
| 519 | * map channel on the selected sequencer rank. |
||
| 520 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
||
| 521 | * - Set ADC channel sampling time |
||
| 522 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
||
| 523 | * @param ADCx ADC instance |
||
| 524 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
||
| 525 | * @retval An ErrorStatus enumeration value: |
||
| 526 | * - SUCCESS: ADC registers are initialized |
||
| 527 | * - ERROR: ADC registers are not initialized |
||
| 528 | */ |
||
| 529 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
||
| 530 | { |
||
| 531 | ErrorStatus status = SUCCESS; |
||
| 532 | |||
| 533 | /* Check the parameters */ |
||
| 534 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
||
| 535 | |||
| 536 | assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); |
||
| 537 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
||
| 538 | /* Note: On STM32L1, low power feature is set by concatenating */ |
||
| 539 | /* values of @ref ADC_LL_EC_LP_MODE_AUTOWAIT */ |
||
| 540 | /* and @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF. */ |
||
| 541 | /* Check of the parameter is done for each of group of values, */ |
||
| 542 | /* by excluding the other group of values. */ |
||
| 543 | assert_param(IS_LL_ADC_LOW_POWER_AUTOWAIT(ADC_InitStruct->LowPowerMode & ~(ADC_CR1_PDI | ADC_CR1_PDD))); |
||
| 544 | assert_param(IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(ADC_InitStruct->LowPowerMode & ~(ADC_CR2_DELS))); |
||
| 545 | assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); |
||
| 546 | |||
| 547 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 548 | /* ADC instance must be disabled. */ |
||
| 549 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
||
| 550 | { |
||
| 551 | /* Configuration of ADC hierarchical scope: */ |
||
| 552 | /* - ADC instance */ |
||
| 553 | /* - Set ADC data resolution */ |
||
| 554 | /* - Set ADC conversion data alignment */ |
||
| 555 | /* - Set ADC low power mode */ |
||
| 556 | MODIFY_REG(ADCx->CR1, |
||
| 557 | ADC_CR1_RES |
||
| 558 | | ADC_CR1_PDI |
||
| 559 | | ADC_CR1_PDD |
||
| 560 | | ADC_CR1_SCAN |
||
| 561 | , |
||
| 562 | ADC_InitStruct->Resolution |
||
| 563 | | (ADC_InitStruct->LowPowerMode & (ADC_CR1_PDI | ADC_CR1_PDD)) |
||
| 564 | | ADC_InitStruct->SequencersScanMode |
||
| 565 | ); |
||
| 566 | |||
| 567 | MODIFY_REG(ADCx->CR2, |
||
| 568 | ADC_CR2_ALIGN |
||
| 569 | | ADC_CR2_DELS |
||
| 570 | , |
||
| 571 | ADC_InitStruct->DataAlignment |
||
| 572 | | (ADC_InitStruct->LowPowerMode & ADC_CR2_DELS) |
||
| 573 | ); |
||
| 574 | |||
| 575 | } |
||
| 576 | else |
||
| 577 | { |
||
| 578 | /* Initialization error: ADC instance is not disabled. */ |
||
| 579 | status = ERROR; |
||
| 580 | } |
||
| 581 | return status; |
||
| 582 | } |
||
| 583 | |||
| 584 | /** |
||
| 585 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
||
| 586 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
||
| 587 | * whose fields will be set to default values. |
||
| 588 | * @retval None |
||
| 589 | */ |
||
| 590 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
||
| 591 | { |
||
| 592 | /* Set ADC_InitStruct fields to default values */ |
||
| 593 | /* Set fields of ADC instance */ |
||
| 594 | ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; |
||
| 595 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
||
| 596 | ADC_InitStruct->LowPowerMode = (LL_ADC_LP_AUTOWAIT_NONE | LL_ADC_LP_AUTOPOWEROFF_NONE); |
||
| 597 | |||
| 598 | /* Enable scan mode to have a generic behavior with ADC of other */ |
||
| 599 | /* STM32 families, without this setting available: */ |
||
| 600 | /* ADC group regular sequencer and ADC group injected sequencer depend */ |
||
| 601 | /* only of their own configuration. */ |
||
| 602 | ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; |
||
| 603 | |||
| 604 | } |
||
| 605 | |||
| 606 | /** |
||
| 607 | * @brief Initialize some features of ADC group regular. |
||
| 608 | * @note These parameters have an impact on ADC scope: ADC group regular. |
||
| 609 | * Refer to corresponding unitary functions into |
||
| 610 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
||
| 611 | * (functions with prefix "REG"). |
||
| 612 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
||
| 613 | * is conditioned to ADC state: |
||
| 614 | * ADC instance must be disabled. |
||
| 615 | * This condition is applied to all ADC features, for efficiency |
||
| 616 | * and compatibility over all STM32 families. However, the different |
||
| 617 | * features can be set under different ADC state conditions |
||
| 618 | * (setting possible with ADC enabled without conversion on going, |
||
| 619 | * ADC enabled with conversion on going, ...) |
||
| 620 | * Each feature can be updated afterwards with a unitary function |
||
| 621 | * and potentially with ADC in a different state than disabled, |
||
| 622 | * refer to description of each function for setting |
||
| 623 | * conditioned to ADC state. |
||
| 624 | * @note After using this function, other features must be configured |
||
| 625 | * using LL unitary functions. |
||
| 626 | * The minimum configuration remaining to be done is: |
||
| 627 | * - Set ADC group regular or group injected sequencer: |
||
| 628 | * map channel on the selected sequencer rank. |
||
| 629 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
||
| 630 | * - Set ADC channel sampling time |
||
| 631 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
||
| 632 | * @param ADCx ADC instance |
||
| 633 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
||
| 634 | * @retval An ErrorStatus enumeration value: |
||
| 635 | * - SUCCESS: ADC registers are initialized |
||
| 636 | * - ERROR: ADC registers are not initialized |
||
| 637 | */ |
||
| 638 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
||
| 639 | { |
||
| 640 | ErrorStatus status = SUCCESS; |
||
| 641 | |||
| 642 | /* Check the parameters */ |
||
| 643 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
||
| 644 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
||
| 645 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
||
| 646 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
||
| 647 | { |
||
| 648 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
||
| 649 | } |
||
| 650 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
||
| 651 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
||
| 652 | |||
| 653 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 654 | /* ADC instance must be disabled. */ |
||
| 655 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
||
| 656 | { |
||
| 657 | /* Configuration of ADC hierarchical scope: */ |
||
| 658 | /* - ADC group regular */ |
||
| 659 | /* - Set ADC group regular trigger source */ |
||
| 660 | /* - Set ADC group regular sequencer length */ |
||
| 661 | /* - Set ADC group regular sequencer discontinuous mode */ |
||
| 662 | /* - Set ADC group regular continuous mode */ |
||
| 663 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
||
| 664 | /* transfer by DMA, and DMA requests mode */ |
||
| 665 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
||
| 666 | /* ADC conversion. */ |
||
| 667 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
||
| 668 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
||
| 669 | { |
||
| 670 | MODIFY_REG(ADCx->CR1, |
||
| 671 | ADC_CR1_DISCEN |
||
| 672 | | ADC_CR1_DISCNUM |
||
| 673 | , |
||
| 674 | ADC_REG_InitStruct->SequencerLength |
||
| 675 | | ADC_REG_InitStruct->SequencerDiscont |
||
| 676 | ); |
||
| 677 | } |
||
| 678 | else |
||
| 679 | { |
||
| 680 | MODIFY_REG(ADCx->CR1, |
||
| 681 | ADC_CR1_DISCEN |
||
| 682 | | ADC_CR1_DISCNUM |
||
| 683 | , |
||
| 684 | ADC_REG_InitStruct->SequencerLength |
||
| 685 | | LL_ADC_REG_SEQ_DISCONT_DISABLE |
||
| 686 | ); |
||
| 687 | } |
||
| 688 | |||
| 689 | MODIFY_REG(ADCx->CR2, |
||
| 690 | ADC_CR2_EXTSEL |
||
| 691 | | ADC_CR2_EXTEN |
||
| 692 | | ADC_CR2_CONT |
||
| 693 | | ADC_CR2_DMA |
||
| 694 | | ADC_CR2_DDS |
||
| 695 | , |
||
| 696 | (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) |
||
| 697 | | ADC_REG_InitStruct->ContinuousMode |
||
| 698 | | ADC_REG_InitStruct->DMATransfer |
||
| 699 | ); |
||
| 700 | |||
| 701 | /* Set ADC group regular sequencer length and scan direction */ |
||
| 702 | /* Note: Hardware constraint (refer to description of this function): */ |
||
| 703 | /* Note: If ADC instance feature scan mode is disabled */ |
||
| 704 | /* (refer to ADC instance initialization structure */ |
||
| 705 | /* parameter @ref SequencersScanMode */ |
||
| 706 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
||
| 707 | /* this parameter is discarded. */ |
||
| 708 | LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
||
| 709 | } |
||
| 710 | else |
||
| 711 | { |
||
| 712 | /* Initialization error: ADC instance is not disabled. */ |
||
| 713 | status = ERROR; |
||
| 714 | } |
||
| 715 | return status; |
||
| 716 | } |
||
| 717 | |||
| 718 | /** |
||
| 719 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
||
| 720 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
||
| 721 | * whose fields will be set to default values. |
||
| 722 | * @retval None |
||
| 723 | */ |
||
| 724 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
||
| 725 | { |
||
| 726 | /* Set ADC_REG_InitStruct fields to default values */ |
||
| 727 | /* Set fields of ADC group regular */ |
||
| 728 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
||
| 729 | /* ADC conversion. */ |
||
| 730 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
||
| 731 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
||
| 732 | ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
||
| 733 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
||
| 734 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
||
| 735 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
||
| 736 | } |
||
| 737 | |||
| 738 | /** |
||
| 739 | * @brief Initialize some features of ADC group injected. |
||
| 740 | * @note These parameters have an impact on ADC scope: ADC group injected. |
||
| 741 | * Refer to corresponding unitary functions into |
||
| 742 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
||
| 743 | * (functions with prefix "INJ"). |
||
| 744 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
||
| 745 | * is conditioned to ADC state: |
||
| 746 | * ADC instance must be disabled. |
||
| 747 | * This condition is applied to all ADC features, for efficiency |
||
| 748 | * and compatibility over all STM32 families. However, the different |
||
| 749 | * features can be set under different ADC state conditions |
||
| 750 | * (setting possible with ADC enabled without conversion on going, |
||
| 751 | * ADC enabled with conversion on going, ...) |
||
| 752 | * Each feature can be updated afterwards with a unitary function |
||
| 753 | * and potentially with ADC in a different state than disabled, |
||
| 754 | * refer to description of each function for setting |
||
| 755 | * conditioned to ADC state. |
||
| 756 | * @note After using this function, other features must be configured |
||
| 757 | * using LL unitary functions. |
||
| 758 | * The minimum configuration remaining to be done is: |
||
| 759 | * - Set ADC group injected sequencer: |
||
| 760 | * map channel on the selected sequencer rank. |
||
| 761 | * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
||
| 762 | * - Set ADC channel sampling time |
||
| 763 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
||
| 764 | * @param ADCx ADC instance |
||
| 765 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
||
| 766 | * @retval An ErrorStatus enumeration value: |
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| 767 | * - SUCCESS: ADC registers are initialized |
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| 768 | * - ERROR: ADC registers are not initialized |
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| 769 | */ |
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| 770 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
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| 771 | { |
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| 772 | ErrorStatus status = SUCCESS; |
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| 773 | |||
| 774 | /* Check the parameters */ |
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| 775 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
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| 776 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
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| 777 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
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| 778 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
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| 779 | { |
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| 780 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
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| 781 | } |
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| 782 | assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
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| 783 | |||
| 784 | /* Note: Hardware constraint (refer to description of this function): */ |
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| 785 | /* ADC instance must be disabled. */ |
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| 786 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
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| 787 | { |
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| 788 | /* Configuration of ADC hierarchical scope: */ |
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| 789 | /* - ADC group injected */ |
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| 790 | /* - Set ADC group injected trigger source */ |
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| 791 | /* - Set ADC group injected sequencer length */ |
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| 792 | /* - Set ADC group injected sequencer discontinuous mode */ |
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| 793 | /* - Set ADC group injected conversion trigger: independent or */ |
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| 794 | /* from ADC group regular */ |
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| 795 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
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| 796 | /* ADC conversion. */ |
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| 797 | /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
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| 798 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
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| 799 | { |
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| 800 | MODIFY_REG(ADCx->CR1, |
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| 801 | ADC_CR1_JDISCEN |
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| 802 | | ADC_CR1_JAUTO |
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| 803 | , |
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| 804 | ADC_INJ_InitStruct->SequencerDiscont |
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| 805 | | ADC_INJ_InitStruct->TrigAuto |
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| 806 | ); |
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| 807 | } |
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| 808 | else |
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| 809 | { |
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| 810 | MODIFY_REG(ADCx->CR1, |
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| 811 | ADC_CR1_JDISCEN |
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| 812 | | ADC_CR1_JAUTO |
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| 813 | , |
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| 814 | LL_ADC_REG_SEQ_DISCONT_DISABLE |
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| 815 | | ADC_INJ_InitStruct->TrigAuto |
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| 816 | ); |
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| 817 | } |
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| 818 | |||
| 819 | MODIFY_REG(ADCx->CR2, |
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| 820 | ADC_CR2_JEXTSEL |
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| 821 | | ADC_CR2_JEXTEN |
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| 822 | , |
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| 823 | (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) |
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| 824 | ); |
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| 825 | |||
| 826 | /* Note: Hardware constraint (refer to description of this function): */ |
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| 827 | /* Note: If ADC instance feature scan mode is disabled */ |
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| 828 | /* (refer to ADC instance initialization structure */ |
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| 829 | /* parameter @ref SequencersScanMode */ |
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| 830 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
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| 831 | /* this parameter is discarded. */ |
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| 832 | LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); |
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| 833 | } |
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| 834 | else |
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| 835 | { |
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| 836 | /* Initialization error: ADC instance is not disabled. */ |
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| 837 | status = ERROR; |
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| 838 | } |
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| 839 | return status; |
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| 840 | } |
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| 841 | |||
| 842 | /** |
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| 843 | * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
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| 844 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
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| 845 | * whose fields will be set to default values. |
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| 846 | * @retval None |
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| 847 | */ |
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| 848 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
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| 849 | { |
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| 850 | /* Set ADC_INJ_InitStruct fields to default values */ |
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| 851 | /* Set fields of ADC group injected */ |
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| 852 | ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
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| 853 | ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
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| 854 | ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
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| 855 | ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
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| 856 | } |
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| 857 | |||
| 858 | /** |
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| 859 | * @} |
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| 860 | */ |
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| 861 | |||
| 862 | /** |
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| 863 | * @} |
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| 864 | */ |
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| 865 | |||
| 866 | /** |
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| 867 | * @} |
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| 868 | */ |
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| 869 | |||
| 870 | #endif /* ADC1 */ |
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| 871 | |||
| 872 | /** |
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| 873 | * @} |
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| 874 | */ |
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| 875 | |||
| 876 | #endif /* USE_FULL_LL_DRIVER */ |
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| 877 | |||
| 878 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |