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Rev	Author	Line No.	Line
56	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32l1xx_hal_sram.c
		4	* @author MCD Application Team
		5	* @brief SRAM HAL module driver.
		6	* This file provides a generic firmware to drive SRAM memories
		7	* mounted as external device.
		8	*
		9	@verbatim
		10	==============================================================================
		11	##### How to use this driver #####
		12	==============================================================================
		13	[..]
		14	This driver is a generic layered driver which contains a set of APIs used to
		15	control SRAM memories. It uses the FSMC layer functions to interface
		16	with SRAM devices.
		17	The following sequence should be followed to configure the FSMC to interface
		18	with SRAM/PSRAM memories:
		19
		20	(#) Declare a SRAM_HandleTypeDef handle structure, for example:
		21	SRAM_HandleTypeDef hsram; and:
		22
		23	(++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
		24	values of the structure member.
		25
		26	(++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
		27	base register instance for NOR or SRAM device
		28
		29	(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
		30	base register instance for NOR or SRAM extended mode
		31
		32	(#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
		33	mode timings; for example:
		34	FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
		35	and fill its fields with the allowed values of the structure member.
		36
		37	(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
		38	performs the following sequence:
		39
		40	(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
		41	(##) Control register configuration using the FSMC NORSRAM interface function
		42	FSMC_NORSRAM_Init()
		43	(##) Timing register configuration using the FSMC NORSRAM interface function
		44	FSMC_NORSRAM_Timing_Init()
		45	(##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
		46	FSMC_NORSRAM_Extended_Timing_Init()
		47	(##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
		48
		49	(#) At this stage you can perform read/write accesses from/to the memory connected
		50	to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
		51	following APIs:
		52	(++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
		53	(++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
		54
		55	(#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
		56	HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
		57
		58	(#) You can continuously monitor the SRAM device HAL state by calling the function
		59	HAL_SRAM_GetState()
		60
		61	@endverbatim
		62	******************************************************************************
		63	* @attention
		64	*
		65	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
		66	* All rights reserved.</center></h2>
		67	*
		68	* This software component is licensed by ST under BSD 3-Clause license,
		69	* the "License"; You may not use this file except in compliance with the
		70	* License. You may obtain a copy of the License at:
		71	* opensource.org/licenses/BSD-3-Clause
		72	*
		73	******************************************************************************
		74	*/
		75
		76	/* Includes ------------------------------------------------------------------*/
		77	#include "stm32l1xx_hal.h"
		78
		79	/** @addtogroup STM32L1xx_HAL_Driver
		80	* @{
		81	*/
		82
		83	#ifdef HAL_SRAM_MODULE_ENABLED
		84
		85	#if defined (STM32L151xD) \|\| defined (STM32L152xD) \|\| defined (STM32L162xD)
		86
		87	/** @defgroup SRAM SRAM
		88	* @brief SRAM driver modules
		89	* @{
		90	*/
		91	/* Private typedef -----------------------------------------------------------*/
		92	/* Private define ------------------------------------------------------------*/
		93	/* Private macro -------------------------------------------------------------*/
		94	/* Private variables ---------------------------------------------------------*/
		95	/* Private function prototypes -----------------------------------------------*/
		96	/* Exported functions --------------------------------------------------------*/
		97
		98	/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
		99	* @{
		100	*/
		101
		102	/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
		103	* @brief Initialization and Configuration functions.
		104	*
		105	@verbatim
		106	==============================================================================
		107	##### SRAM Initialization and de_initialization functions #####
		108	==============================================================================
		109	[..] This section provides functions allowing to initialize/de-initialize
		110	the SRAM memory
		111
		112	@endverbatim
		113	* @{
		114	*/
		115
		116	/**
		117	* @brief Performs the SRAM device initialization sequence
		118	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		119	* the configuration information for SRAM module.
		120	* @param Timing Pointer to SRAM control timing structure
		121	* @param ExtTiming Pointer to SRAM extended mode timing structure
		122	* @retval HAL status
		123	*/
		124	HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef hsram, FSMC_NORSRAM_TimingTypeDef Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
		125	{
		126	/* Check the SRAM handle parameter */
		127	if(hsram == NULL)
		128	{
		129	return HAL_ERROR;
		130	}
		131
		132	if(hsram->State == HAL_SRAM_STATE_RESET)
		133	{
		134	/* Allocate lock resource and initialize it */
		135	hsram->Lock = HAL_UNLOCKED;
		136
		137	/* Initialize the low level hardware (MSP) */
		138	HAL_SRAM_MspInit(hsram);
		139	}
		140
		141	/* Initialize SRAM control Interface */
		142	FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
		143
		144	/* Initialize SRAM timing Interface */
		145	FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
		146
		147	/* Initialize SRAM extended mode timing Interface */
		148	FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
		149
		150	/* Enable the NORSRAM device */
		151	__FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
		152
		153	return HAL_OK;
		154	}
		155
		156	/**
		157	* @brief Performs the SRAM device De-initialization sequence.
		158	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		159	* the configuration information for SRAM module.
		160	* @retval HAL status
		161	*/
		162	HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
		163	{
		164	/* De-Initialize the low level hardware (MSP) */
		165	HAL_SRAM_MspDeInit(hsram);
		166
		167	/* Configure the SRAM registers with their reset values */
		168	FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
		169
		170	hsram->State = HAL_SRAM_STATE_RESET;
		171
		172	/* Release Lock */
		173	__HAL_UNLOCK(hsram);
		174
		175	return HAL_OK;
		176	}
		177
		178	/**
		179	* @brief SRAM MSP Init.
		180	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		181	* the configuration information for SRAM module.
		182	* @retval None
		183	*/
		184	__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
		185	{
		186	/* Prevent unused argument(s) compilation warning */
		187	UNUSED(hsram);
		188
		189	/* NOTE : This function Should not be modified, when the callback is needed,
		190	the HAL_SRAM_MspInit could be implemented in the user file
		191	*/
		192	}
		193
		194	/**
		195	* @brief SRAM MSP DeInit.
		196	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		197	* the configuration information for SRAM module.
		198	* @retval None
		199	*/
		200	__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
		201	{
		202	/* Prevent unused argument(s) compilation warning */
		203	UNUSED(hsram);
		204
		205	/* NOTE : This function Should not be modified, when the callback is needed,
		206	the HAL_SRAM_MspDeInit could be implemented in the user file
		207	*/
		208	}
		209
		210	/**
		211	* @brief DMA transfer complete callback.
		212	* @param hdma pointer to a SRAM_HandleTypeDef structure that contains
		213	* the configuration information for SRAM module.
		214	* @retval None
		215	*/
		216	__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
		217	{
		218	/* Prevent unused argument(s) compilation warning */
		219	UNUSED(hdma);
		220
		221	/* NOTE : This function Should not be modified, when the callback is needed,
		222	the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
		223	*/
		224	}
		225
		226	/**
		227	* @brief DMA transfer complete error callback.
		228	* @param hdma pointer to a SRAM_HandleTypeDef structure that contains
		229	* the configuration information for SRAM module.
		230	* @retval None
		231	*/
		232	__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
		233	{
		234	/* Prevent unused argument(s) compilation warning */
		235	UNUSED(hdma);
		236
		237	/* NOTE : This function Should not be modified, when the callback is needed,
		238	the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
		239	*/
		240	}
		241
		242	/**
		243	* @}
		244	*/
		245
		246	/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
		247	* @brief Input Output and memory control functions
		248	*
		249	@verbatim
		250	==============================================================================
		251	##### SRAM Input and Output functions #####
		252	==============================================================================
		253	[..]
		254	This section provides functions allowing to use and control the SRAM memory
		255
		256	@endverbatim
		257	* @{
		258	*/
		259
		260	/**
		261	* @brief Reads 8-bit buffer from SRAM memory.
		262	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		263	* the configuration information for SRAM module.
		264	* @param pAddress Pointer to read start address
		265	* @param pDstBuffer Pointer to destination buffer
		266	* @param BufferSize Size of the buffer to read from memory
		267	* @retval HAL status
		268	*/
		269	HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
		270	{
		271	__IO uint8_t * psramaddress = (uint8_t *)pAddress;
		272
		273	/* Process Locked */
		274	__HAL_LOCK(hsram);
		275
		276	/* Update the SRAM controller state */
		277	hsram->State = HAL_SRAM_STATE_BUSY;
		278
		279	/* Read data from memory */
		280	for(; BufferSize != 0; BufferSize--)
		281	{
		282	pDstBuffer = (__IO uint8_t *)psramaddress;
		283	pDstBuffer++;
		284	psramaddress++;
		285	}
		286
		287	/* Update the SRAM controller state */
		288	hsram->State = HAL_SRAM_STATE_READY;
		289
		290	/* Process unlocked */
		291	__HAL_UNLOCK(hsram);
		292
		293	return HAL_OK;
		294	}
		295
		296	/**
		297	* @brief Writes 8-bit buffer to SRAM memory.
		298	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		299	* the configuration information for SRAM module.
		300	* @param pAddress Pointer to write start address
		301	* @param pSrcBuffer Pointer to source buffer to write
		302	* @param BufferSize Size of the buffer to write to memory
		303	* @retval HAL status
		304	*/
		305	HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
		306	{
		307	__IO uint8_t * psramaddress = (uint8_t *)pAddress;
		308
		309	/* Check the SRAM controller state */
		310	if(hsram->State == HAL_SRAM_STATE_PROTECTED)
		311	{
		312	return HAL_ERROR;
		313	}
		314
		315	/* Process Locked */
		316	__HAL_LOCK(hsram);
		317
		318	/* Update the SRAM controller state */
		319	hsram->State = HAL_SRAM_STATE_BUSY;
		320
		321	/* Write data to memory */
		322	for(; BufferSize != 0; BufferSize--)
		323	{
		324	(__IO uint8_t )psramaddress = *pSrcBuffer;
		325	pSrcBuffer++;
		326	psramaddress++;
		327	}
		328
		329	/* Update the SRAM controller state */
		330	hsram->State = HAL_SRAM_STATE_READY;
		331
		332	/* Process unlocked */
		333	__HAL_UNLOCK(hsram);
		334
		335	return HAL_OK;
		336	}
		337
		338	/**
		339	* @brief Reads 16-bit buffer from SRAM memory.
		340	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		341	* the configuration information for SRAM module.
		342	* @param pAddress Pointer to read start address
		343	* @param pDstBuffer Pointer to destination buffer
		344	* @param BufferSize Size of the buffer to read from memory
		345	* @retval HAL status
		346	*/
		347	HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
		348	{
		349	__IO uint16_t * psramaddress = (uint16_t *)pAddress;
		350
		351	/* Process Locked */
		352	__HAL_LOCK(hsram);
		353
		354	/* Update the SRAM controller state */
		355	hsram->State = HAL_SRAM_STATE_BUSY;
		356
		357	/* Read data from memory */
		358	for(; BufferSize != 0; BufferSize--)
		359	{
		360	pDstBuffer = (__IO uint16_t *)psramaddress;
		361	pDstBuffer++;
		362	psramaddress++;
		363	}
		364
		365	/* Update the SRAM controller state */
		366	hsram->State = HAL_SRAM_STATE_READY;
		367
		368	/* Process unlocked */
		369	__HAL_UNLOCK(hsram);
		370
		371	return HAL_OK;
		372	}
		373
		374	/**
		375	* @brief Writes 16-bit buffer to SRAM memory.
		376	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		377	* the configuration information for SRAM module.
		378	* @param pAddress Pointer to write start address
		379	* @param pSrcBuffer Pointer to source buffer to write
		380	* @param BufferSize Size of the buffer to write to memory
		381	* @retval HAL status
		382	*/
		383	HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
		384	{
		385	__IO uint16_t * psramaddress = (uint16_t *)pAddress;
		386
		387	/* Check the SRAM controller state */
		388	if(hsram->State == HAL_SRAM_STATE_PROTECTED)
		389	{
		390	return HAL_ERROR;
		391	}
		392
		393	/* Process Locked */
		394	__HAL_LOCK(hsram);
		395
		396	/* Update the SRAM controller state */
		397	hsram->State = HAL_SRAM_STATE_BUSY;
		398
		399	/* Write data to memory */
		400	for(; BufferSize != 0; BufferSize--)
		401	{
		402	(__IO uint16_t )psramaddress = *pSrcBuffer;
		403	pSrcBuffer++;
		404	psramaddress++;
		405	}
		406
		407	/* Update the SRAM controller state */
		408	hsram->State = HAL_SRAM_STATE_READY;
		409
		410	/* Process unlocked */
		411	__HAL_UNLOCK(hsram);
		412
		413	return HAL_OK;
		414	}
		415
		416	/**
		417	* @brief Reads 32-bit buffer from SRAM memory.
		418	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		419	* the configuration information for SRAM module.
		420	* @param pAddress Pointer to read start address
		421	* @param pDstBuffer Pointer to destination buffer
		422	* @param BufferSize Size of the buffer to read from memory
		423	* @retval HAL status
		424	*/
		425	HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
		426	{
		427	/* Process Locked */
		428	__HAL_LOCK(hsram);
		429
		430	/* Update the SRAM controller state */
		431	hsram->State = HAL_SRAM_STATE_BUSY;
		432
		433	/* Read data from memory */
		434	for(; BufferSize != 0; BufferSize--)
		435	{
		436	pDstBuffer = (__IO uint32_t *)pAddress;
		437	pDstBuffer++;
		438	pAddress++;
		439	}
		440
		441	/* Update the SRAM controller state */
		442	hsram->State = HAL_SRAM_STATE_READY;
		443
		444	/* Process unlocked */
		445	__HAL_UNLOCK(hsram);
		446
		447	return HAL_OK;
		448	}
		449
		450	/**
		451	* @brief Writes 32-bit buffer to SRAM memory.
		452	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		453	* the configuration information for SRAM module.
		454	* @param pAddress Pointer to write start address
		455	* @param pSrcBuffer Pointer to source buffer to write
		456	* @param BufferSize Size of the buffer to write to memory
		457	* @retval HAL status
		458	*/
		459	HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
		460	{
		461	/* Check the SRAM controller state */
		462	if(hsram->State == HAL_SRAM_STATE_PROTECTED)
		463	{
		464	return HAL_ERROR;
		465	}
		466
		467	/* Process Locked */
		468	__HAL_LOCK(hsram);
		469
		470	/* Update the SRAM controller state */
		471	hsram->State = HAL_SRAM_STATE_BUSY;
		472
		473	/* Write data to memory */
		474	for(; BufferSize != 0; BufferSize--)
		475	{
		476	(__IO uint32_t )pAddress = *pSrcBuffer;
		477	pSrcBuffer++;
		478	pAddress++;
		479	}
		480
		481	/* Update the SRAM controller state */
		482	hsram->State = HAL_SRAM_STATE_READY;
		483
		484	/* Process unlocked */
		485	__HAL_UNLOCK(hsram);
		486
		487	return HAL_OK;
		488	}
		489
		490	/**
		491	* @brief Reads a Words data from the SRAM memory using DMA transfer.
		492	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		493	* the configuration information for SRAM module.
		494	* @param pAddress Pointer to read start address
		495	* @param pDstBuffer Pointer to destination buffer
		496	* @param BufferSize Size of the buffer to read from memory
		497	* @retval HAL status
		498	*/
		499	HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
		500	{
		501	/* Process Locked */
		502	__HAL_LOCK(hsram);
		503
		504	/* Update the SRAM controller state */
		505	hsram->State = HAL_SRAM_STATE_BUSY;
		506
		507	/* Configure DMA user callbacks */
		508	hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
		509	hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
		510
		511	/* Enable the DMA Channel */
		512	HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
		513
		514	/* Update the SRAM controller state */
		515	hsram->State = HAL_SRAM_STATE_READY;
		516
		517	/* Process unlocked */
		518	__HAL_UNLOCK(hsram);
		519
		520	return HAL_OK;
		521	}
		522
		523	/**
		524	* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
		525	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		526	* the configuration information for SRAM module.
		527	* @param pAddress Pointer to write start address
		528	* @param pSrcBuffer Pointer to source buffer to write
		529	* @param BufferSize Size of the buffer to write to memory
		530	* @retval HAL status
		531	*/
		532	HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef hsram, uint32_t pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
		533	{
		534	/* Check the SRAM controller state */
		535	if(hsram->State == HAL_SRAM_STATE_PROTECTED)
		536	{
		537	return HAL_ERROR;
		538	}
		539
		540	/* Process Locked */
		541	__HAL_LOCK(hsram);
		542
		543	/* Update the SRAM controller state */
		544	hsram->State = HAL_SRAM_STATE_BUSY;
		545
		546	/* Configure DMA user callbacks */
		547	hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
		548	hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
		549
		550	/* Enable the DMA Channel */
		551	HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
		552
		553	/* Update the SRAM controller state */
		554	hsram->State = HAL_SRAM_STATE_READY;
		555
		556	/* Process unlocked */
		557	__HAL_UNLOCK(hsram);
		558
		559	return HAL_OK;
		560	}
		561
		562	/**
		563	* @}
		564	*/
		565
		566	/** @defgroup SRAM_Exported_Functions_Group3 Control functions
		567	* @brief Control functions
		568	*
		569	@verbatim
		570	==============================================================================
		571	##### SRAM Control functions #####
		572	==============================================================================
		573	[..]
		574	This subsection provides a set of functions allowing to control dynamically
		575	the SRAM interface.
		576
		577	@endverbatim
		578	* @{
		579	*/
		580
		581	/**
		582	* @brief Enables dynamically SRAM write operation.
		583	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		584	* the configuration information for SRAM module.
		585	* @retval HAL status
		586	*/
		587	HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
		588	{
		589	/* Process Locked */
		590	__HAL_LOCK(hsram);
		591
		592	/* Enable write operation */
		593	FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
		594
		595	/* Update the SRAM controller state */
		596	hsram->State = HAL_SRAM_STATE_READY;
		597
		598	/* Process unlocked */
		599	__HAL_UNLOCK(hsram);
		600
		601	return HAL_OK;
		602	}
		603
		604	/**
		605	* @brief Disables dynamically SRAM write operation.
		606	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		607	* the configuration information for SRAM module.
		608	* @retval HAL status
		609	*/
		610	HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
		611	{
		612	/* Process Locked */
		613	__HAL_LOCK(hsram);
		614
		615	/* Update the SRAM controller state */
		616	hsram->State = HAL_SRAM_STATE_BUSY;
		617
		618	/* Disable write operation */
		619	FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
		620
		621	/* Update the SRAM controller state */
		622	hsram->State = HAL_SRAM_STATE_PROTECTED;
		623
		624	/* Process unlocked */
		625	__HAL_UNLOCK(hsram);
		626
		627	return HAL_OK;
		628	}
		629
		630	/**
		631	* @}
		632	*/
		633
		634	/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
		635	* @brief Peripheral State functions
		636	*
		637	@verbatim
		638	==============================================================================
		639	##### SRAM State functions #####
		640	==============================================================================
		641	[..]
		642	This subsection permits to get in run-time the status of the SRAM controller
		643	and the data flow.
		644
		645	@endverbatim
		646	* @{
		647	*/
		648
		649	/**
		650	* @brief Returns the SRAM controller state
		651	* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
		652	* the configuration information for SRAM module.
		653	* @retval HAL state
		654	*/
		655	HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
		656	{
		657	return hsram->State;
		658	}
		659
		660	/**
		661	* @}
		662	*/
		663
		664	/**
		665	* @}
		666	*/
		667
		668	/**
		669	* @}
		670	*/
		671	#endif /* STM32L151xD \|\| STM32L152xD \|\| STM32L162xD */
		672	#endif /* HAL_SRAM_MODULE_ENABLED */
		673
		674	/**
		675	* @}
		676	*/
		677
		678	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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