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56 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32l1xx_hal_adc.c |
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4 | * @author MCD Application Team |
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5 | * @brief This file provides firmware functions to manage the following |
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6 | * functionalities of the Analog to Digital Convertor (ADC) |
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7 | * peripheral: |
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8 | * + Initialization and de-initialization functions |
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9 | * ++ Initialization and Configuration of ADC |
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10 | * + Operation functions |
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11 | * ++ Start, stop, get result of conversions of regular |
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12 | * group, using 3 possible modes: polling, interruption or DMA. |
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13 | * + Control functions |
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14 | * ++ Channels configuration on regular group |
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15 | * ++ Channels configuration on injected group |
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16 | * ++ Analog Watchdog configuration |
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17 | * + State functions |
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18 | * ++ ADC state machine management |
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19 | * ++ Interrupts and flags management |
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20 | * Other functions (extended functions) are available in file |
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21 | * "stm32l1xx_hal_adc_ex.c". |
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22 | * |
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23 | @verbatim |
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24 | ============================================================================== |
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25 | ##### ADC peripheral features ##### |
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26 | ============================================================================== |
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27 | [..] |
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28 | (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution |
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29 | |||
30 | (+) Interrupt generation at the end of regular conversion, end of injected |
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31 | conversion, and in case of analog watchdog or overrun events. |
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32 | |||
33 | (+) Single and continuous conversion modes. |
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34 | |||
35 | (+) Scan mode for conversion of several channels sequentially. |
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36 | |||
37 | (+) Data alignment with in-built data coherency. |
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38 | |||
39 | (+) Programmable sampling time (channel wise) |
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40 | |||
41 | (+) ADC conversion of regular group and injected group. |
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42 | |||
43 | (+) External trigger (timer or EXTI) with configurable polarity |
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44 | for both regular and injected groups. |
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45 | |||
46 | (+) DMA request generation for transfer of conversions data of regular group. |
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47 | |||
48 | (+) ADC offset on injected channels |
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49 | |||
50 | (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
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51 | slower speed. |
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52 | |||
53 | (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to |
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54 | Vdda or to an external voltage reference). |
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55 | |||
56 | |||
57 | ##### How to use this driver ##### |
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58 | ============================================================================== |
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59 | [..] |
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60 | |||
61 | *** Configuration of top level parameters related to ADC *** |
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62 | ============================================================ |
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63 | [..] |
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64 | |||
65 | (#) Enable the ADC interface |
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66 | (++) As prerequisite, ADC clock must be configured at RCC top level. |
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67 | Caution: On STM32L1, ADC clock frequency max is 16MHz (refer |
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68 | to device datasheet). |
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69 | Therefore, ADC clock prescaler must be configured in |
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70 | function of ADC clock source frequency to remain below |
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71 | this maximum frequency. |
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72 | |||
73 | (++) Two clock settings are mandatory: |
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74 | (+++) ADC clock (core clock). |
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75 | (+++) ADC clock (conversions clock). |
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76 | Only one possible clock source: derived from HSI RC 16MHz oscillator |
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77 | (HSI). |
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78 | ADC is connected directly to HSI RC 16MHz oscillator. |
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79 | Therefore, RCC PLL setting has no impact on ADC. |
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80 | PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or |
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81 | enabled with HSI16 as clock source |
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82 | (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device |
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83 | main clock source SYSCLK. |
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84 | The only mandatory setting is ".HSIState = RCC_HSI_ON" |
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85 | |||
86 | (+++) Example: |
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87 | Into HAL_ADC_MspInit() (recommended code location) or with |
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88 | other device clock parameters configuration: |
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89 | (+++) __HAL_RCC_ADC1_CLK_ENABLE(); |
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90 | |||
91 | (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); |
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92 | (+++) RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI); |
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93 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON; |
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94 | (+++) RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
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95 | (+++) RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE; |
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96 | (+++) RCC_OscInitStructure.PLL.PLLSource = ... |
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97 | (+++) RCC_OscInitStructure.PLL... |
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98 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
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99 | |||
100 | (++) ADC clock prescaler is configured at ADC level with |
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101 | parameter "ClockPrescaler" using function HAL_ADC_Init(). |
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102 | |||
103 | (#) ADC pins configuration |
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104 | (++) Enable the clock for the ADC GPIOs |
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105 | using macro __HAL_RCC_GPIOx_CLK_ENABLE() |
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106 | (++) Configure these ADC pins in analog mode |
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107 | using function HAL_GPIO_Init() |
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108 | |||
109 | (#) Optionally, in case of usage of ADC with interruptions: |
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110 | (++) Configure the NVIC for ADC |
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111 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
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112 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
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113 | into the function of corresponding ADC interruption vector |
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114 | ADCx_IRQHandler(). |
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115 | |||
116 | (#) Optionally, in case of usage of DMA: |
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117 | (++) Configure the DMA (DMA channel, mode normal or circular, ...) |
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118 | using function HAL_DMA_Init(). |
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119 | (++) Configure the NVIC for DMA |
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120 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
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121 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
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122 | into the function of corresponding DMA interruption vector |
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123 | DMAx_Channelx_IRQHandler(). |
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124 | |||
125 | *** Configuration of ADC, groups regular/injected, channels parameters *** |
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126 | ========================================================================== |
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127 | [..] |
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128 | |||
129 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
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130 | and regular group parameters (conversion trigger, sequencer, ...) |
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131 | using function HAL_ADC_Init(). |
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132 | |||
133 | (#) Configure the channels for regular group parameters (channel number, |
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134 | channel rank into sequencer, ..., into regular group) |
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135 | using function HAL_ADC_ConfigChannel(). |
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136 | |||
137 | (#) Optionally, configure the injected group parameters (conversion trigger, |
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138 | sequencer, ..., of injected group) |
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139 | and the channels for injected group parameters (channel number, |
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140 | channel rank into sequencer, ..., into injected group) |
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141 | using function HAL_ADCEx_InjectedConfigChannel(). |
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142 | |||
143 | (#) Optionally, configure the analog watchdog parameters (channels |
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144 | monitored, thresholds, ...) |
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145 | using function HAL_ADC_AnalogWDGConfig(). |
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146 | |||
147 | (#) Optionally, for devices with several ADC instances: configure the |
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148 | multimode parameters |
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149 | using function HAL_ADCEx_MultiModeConfigChannel(). |
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150 | |||
151 | *** Execution of ADC conversions *** |
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152 | ==================================== |
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153 | [..] |
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154 | |||
155 | (#) ADC driver can be used among three modes: polling, interruption, |
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156 | transfer by DMA. |
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157 | |||
158 | (++) ADC conversion by polling: |
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159 | (+++) Activate the ADC peripheral and start conversions |
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160 | using function HAL_ADC_Start() |
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161 | (+++) Wait for ADC conversion completion |
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162 | using function HAL_ADC_PollForConversion() |
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163 | (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) |
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164 | (+++) Retrieve conversion results |
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165 | using function HAL_ADC_GetValue() |
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166 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
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167 | (+++) Stop conversion and disable the ADC peripheral |
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168 | using function HAL_ADC_Stop() |
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169 | |||
170 | (++) ADC conversion by interruption: |
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171 | (+++) Activate the ADC peripheral and start conversions |
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172 | using function HAL_ADC_Start_IT() |
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173 | (+++) Wait for ADC conversion completion by call of function |
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174 | HAL_ADC_ConvCpltCallback() |
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175 | (this function must be implemented in user program) |
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176 | (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) |
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177 | (+++) Retrieve conversion results |
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178 | using function HAL_ADC_GetValue() |
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179 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
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180 | (+++) Stop conversion and disable the ADC peripheral |
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181 | using function HAL_ADC_Stop_IT() |
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182 | |||
183 | (++) ADC conversion with transfer by DMA: |
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184 | (+++) Activate the ADC peripheral and start conversions |
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185 | using function HAL_ADC_Start_DMA() |
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186 | (+++) Wait for ADC conversion completion by call of function |
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187 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
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188 | (these functions must be implemented in user program) |
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189 | (+++) Conversion results are automatically transferred by DMA into |
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190 | destination variable address. |
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191 | (+++) Stop conversion and disable the ADC peripheral |
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192 | using function HAL_ADC_Stop_DMA() |
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193 | |||
194 | (++) For devices with several ADCs: ADC multimode conversion |
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195 | with transfer by DMA: |
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196 | (+++) Activate the ADC peripheral (slave) and start conversions |
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197 | using function HAL_ADC_Start() |
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198 | (+++) Activate the ADC peripheral (master) and start conversions |
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199 | using function HAL_ADCEx_MultiModeStart_DMA() |
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200 | (+++) Wait for ADC conversion completion by call of function |
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201 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
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202 | (these functions must be implemented in user program) |
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203 | (+++) Conversion results are automatically transferred by DMA into |
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204 | destination variable address. |
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205 | (+++) Stop conversion and disable the ADC peripheral (master) |
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206 | using function HAL_ADCEx_MultiModeStop_DMA() |
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207 | (+++) Stop conversion and disable the ADC peripheral (slave) |
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208 | using function HAL_ADC_Stop_IT() |
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209 | |||
210 | [..] |
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211 | |||
212 | (@) Callback functions must be implemented in user program: |
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213 | (+@) HAL_ADC_ErrorCallback() |
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214 | (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) |
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215 | (+@) HAL_ADC_ConvCpltCallback() |
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216 | (+@) HAL_ADC_ConvHalfCpltCallback |
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217 | (+@) HAL_ADCEx_InjectedConvCpltCallback() |
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218 | |||
219 | *** Deinitialization of ADC *** |
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220 | ============================================================ |
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221 | [..] |
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222 | |||
223 | (#) Disable the ADC interface |
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224 | (++) ADC clock can be hard reset and disabled at RCC top level. |
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225 | (++) Hard reset of ADC peripherals |
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226 | using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). |
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227 | (++) ADC clock disable |
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228 | using the equivalent macro/functions as configuration step. |
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229 | (+++) Example: |
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230 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
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231 | other device clock parameters configuration: |
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232 | (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); |
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233 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
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234 | (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) |
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235 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
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236 | |||
237 | (#) ADC pins configuration |
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238 | (++) Disable the clock for the ADC GPIOs |
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239 | using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
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240 | |||
241 | (#) Optionally, in case of usage of ADC with interruptions: |
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242 | (++) Disable the NVIC for ADC |
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243 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
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244 | |||
245 | (#) Optionally, in case of usage of DMA: |
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246 | (++) Deinitialize the DMA |
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247 | using function HAL_DMA_Init(). |
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248 | (++) Disable the NVIC for DMA |
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249 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
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250 | |||
251 | [..] |
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252 | |||
253 | *** Callback registration *** |
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254 | ============================================= |
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255 | [..] |
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256 | |||
257 | The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, |
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258 | allows the user to configure dynamically the driver callbacks. |
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259 | Use Functions @ref HAL_ADC_RegisterCallback() |
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260 | to register an interrupt callback. |
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261 | [..] |
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262 | |||
263 | Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: |
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264 | (+) ConvCpltCallback : ADC conversion complete callback |
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265 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
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266 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
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267 | (+) ErrorCallback : ADC error callback |
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268 | (+) InjectedConvCpltCallback : ADC group injected conversion complete callback |
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269 | (+) MspInitCallback : ADC Msp Init callback |
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270 | (+) MspDeInitCallback : ADC Msp DeInit callback |
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271 | This function takes as parameters the HAL peripheral handle, the Callback ID |
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272 | and a pointer to the user callback function. |
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273 | [..] |
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274 | |||
275 | Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default |
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276 | weak function. |
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277 | [..] |
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278 | |||
279 | @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, |
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280 | and the Callback ID. |
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281 | This function allows to reset following callbacks: |
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282 | (+) ConvCpltCallback : ADC conversion complete callback |
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283 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
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284 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
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285 | (+) ErrorCallback : ADC error callback |
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286 | (+) InjectedConvCpltCallback : ADC group injected conversion complete callback |
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287 | (+) MspInitCallback : ADC Msp Init callback |
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288 | (+) MspDeInitCallback : ADC Msp DeInit callback |
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289 | [..] |
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290 | |||
291 | By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET |
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292 | all callbacks are set to the corresponding weak functions: |
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293 | examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). |
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294 | Exception done for MspInit and MspDeInit functions that are |
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295 | reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when |
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296 | these callbacks are null (not registered beforehand). |
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297 | [..] |
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298 | |||
299 | If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() |
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300 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
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301 | [..] |
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302 | |||
303 | Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. |
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304 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
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305 | in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, |
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306 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
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307 | [..] |
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308 | |||
309 | Then, the user first registers the MspInit/MspDeInit user callbacks |
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310 | using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() |
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311 | or @ref HAL_ADC_Init() function. |
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312 | [..] |
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313 | |||
314 | When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or |
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315 | not defined, the callback registration feature is not available and all callbacks |
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316 | are set to the corresponding weak functions. |
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317 | |||
318 | @endverbatim |
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319 | ****************************************************************************** |
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320 | * @attention |
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321 | * |
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322 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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323 | * All rights reserved.</center></h2> |
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324 | * |
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325 | * This software component is licensed by ST under BSD 3-Clause license, |
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326 | * the "License"; You may not use this file except in compliance with the |
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327 | * License. You may obtain a copy of the License at: |
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328 | * opensource.org/licenses/BSD-3-Clause |
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329 | * |
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330 | ****************************************************************************** |
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331 | */ |
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332 | |||
333 | /* Includes ------------------------------------------------------------------*/ |
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334 | #include "stm32l1xx_hal.h" |
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335 | |||
336 | /** @addtogroup STM32L1xx_HAL_Driver |
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337 | * @{ |
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338 | */ |
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339 | |||
340 | /** @defgroup ADC ADC |
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341 | * @brief ADC HAL module driver |
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342 | * @{ |
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343 | */ |
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344 | |||
345 | #ifdef HAL_ADC_MODULE_ENABLED |
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346 | |||
347 | /* Private typedef -----------------------------------------------------------*/ |
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348 | /* Private define ------------------------------------------------------------*/ |
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349 | /** @defgroup ADC_Private_Constants ADC Private Constants |
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350 | * @{ |
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351 | */ |
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352 | |||
353 | /* Timeout values for ADC enable and disable settling time. */ |
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354 | /* Values defined to be higher than worst cases: low clocks freq, */ |
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355 | /* maximum prescaler. */ |
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356 | /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ |
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357 | /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ |
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358 | /* Unit: ms */ |
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359 | #define ADC_ENABLE_TIMEOUT (2U) |
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360 | #define ADC_DISABLE_TIMEOUT (2U) |
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361 | |||
362 | /* Delay for ADC stabilization time. */ |
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363 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
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364 | /* Unit: us */ |
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365 | #define ADC_STAB_DELAY_US (3U) |
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366 | |||
367 | /* Delay for temperature sensor stabilization time. */ |
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368 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
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369 | /* Unit: us */ |
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370 | #define ADC_TEMPSENSOR_DELAY_US (10U) |
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371 | |||
372 | /** |
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373 | * @} |
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374 | */ |
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375 | |||
376 | /* Private macro -------------------------------------------------------------*/ |
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377 | /* Private variables ---------------------------------------------------------*/ |
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378 | /* Private function prototypes -----------------------------------------------*/ |
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379 | /** @defgroup ADC_Private_Functions ADC Private Functions |
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380 | * @{ |
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381 | */ |
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382 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
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383 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
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384 | static void ADC_DMAError(DMA_HandleTypeDef *hdma); |
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385 | /** |
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386 | * @} |
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387 | */ |
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388 | |||
389 | /* Exported functions --------------------------------------------------------*/ |
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390 | |||
391 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
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392 | * @{ |
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393 | */ |
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394 | |||
395 | /** @defgroup ADC_Exported_Functions_Group1 ADC Initialization/de-initialization functions |
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396 | * @brief ADC Initialization and Configuration functions |
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397 | * |
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398 | @verbatim |
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399 | =============================================================================== |
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400 | ##### Initialization and de-initialization functions ##### |
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401 | =============================================================================== |
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402 | [..] This section provides functions allowing to: |
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403 | (+) Initialize and configure the ADC. |
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404 | (+) De-initialize the ADC. |
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405 | @endverbatim |
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406 | * @{ |
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407 | */ |
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408 | |||
409 | /** |
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410 | * @brief Initializes the ADC peripheral and regular group according to |
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411 | * parameters specified in structure "ADC_InitTypeDef". |
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412 | * @note As prerequisite, ADC clock must be configured at RCC top level |
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413 | * (clock source APB2). |
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414 | * See commented example code below that can be copied and uncommented |
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415 | * into HAL_ADC_MspInit(). |
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416 | * @note Possibility to update parameters on the fly: |
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417 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
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418 | * coming from ADC state reset. Following calls to this function can |
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419 | * be used to reconfigure some parameters of ADC_InitTypeDef |
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420 | * structure on the fly, without modifying MSP configuration. If ADC |
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421 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
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422 | * before HAL_ADC_Init(). |
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423 | * The setting of these parameters is conditioned to ADC state. |
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424 | * For parameters constraints, see comments of structure |
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425 | * "ADC_InitTypeDef". |
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426 | * @note This function configures the ADC within 2 scopes: scope of entire |
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427 | * ADC and scope of regular group. For parameters details, see comments |
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428 | * of structure "ADC_InitTypeDef". |
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429 | * @param hadc ADC handle |
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430 | * @retval HAL status |
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431 | */ |
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432 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
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433 | { |
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434 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
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435 | uint32_t tmp_cr1 = 0; |
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436 | uint32_t tmp_cr2 = 0; |
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437 | |||
438 | /* Check ADC handle */ |
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439 | if(hadc == NULL) |
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440 | { |
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441 | return HAL_ERROR; |
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442 | } |
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443 | |||
444 | /* Check the parameters */ |
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445 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
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446 | assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); |
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447 | assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); |
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448 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
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449 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
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450 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
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451 | assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait)); |
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452 | assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff)); |
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453 | assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank)); |
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454 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
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455 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
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456 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
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457 | |||
458 | if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) |
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459 | { |
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460 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
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461 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
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462 | if(hadc->Init.DiscontinuousConvMode != DISABLE) |
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463 | { |
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464 | assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); |
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465 | } |
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466 | } |
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467 | |||
468 | if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
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469 | { |
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470 | assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
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471 | } |
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472 | |||
473 | |||
474 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
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475 | /* at RCC top level. */ |
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476 | /* Refer to header of this file for more details on clock enabling */ |
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477 | /* procedure. */ |
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478 | |||
479 | /* Actions performed only if ADC is coming from state reset: */ |
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480 | /* - Initialization of ADC MSP */ |
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481 | if (hadc->State == HAL_ADC_STATE_RESET) |
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482 | { |
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483 | /* Initialize ADC error code */ |
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484 | ADC_CLEAR_ERRORCODE(hadc); |
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485 | |||
486 | /* Allocate lock resource and initialize it */ |
||
487 | hadc->Lock = HAL_UNLOCKED; |
||
488 | |||
489 | /* Enable SYSCFG clock to control the routing Interface (RI) */ |
||
490 | __HAL_RCC_SYSCFG_CLK_ENABLE(); |
||
491 | |||
492 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
493 | /* Init the ADC Callback settings */ |
||
494 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ |
||
495 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ |
||
496 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ |
||
497 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ |
||
498 | hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ |
||
499 | |||
500 | if (hadc->MspInitCallback == NULL) |
||
501 | { |
||
502 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
503 | } |
||
504 | |||
505 | /* Init the low level hardware */ |
||
506 | hadc->MspInitCallback(hadc); |
||
507 | #else |
||
508 | /* Init the low level hardware */ |
||
509 | HAL_ADC_MspInit(hadc); |
||
510 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
511 | } |
||
512 | |||
513 | /* Configuration of ADC parameters if previous preliminary actions are */ |
||
514 | /* correctly completed. */ |
||
515 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
||
516 | { |
||
517 | /* Set ADC state */ |
||
518 | ADC_STATE_CLR_SET(hadc->State, |
||
519 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
520 | HAL_ADC_STATE_BUSY_INTERNAL); |
||
521 | |||
522 | /* Set ADC parameters */ |
||
523 | |||
524 | /* Configuration of common ADC clock: clock source HSI with selectable */ |
||
525 | /* prescaler */ |
||
526 | MODIFY_REG(ADC->CCR , |
||
527 | ADC_CCR_ADCPRE , |
||
528 | hadc->Init.ClockPrescaler ); |
||
529 | |||
530 | /* Configuration of ADC: */ |
||
531 | /* - external trigger polarity */ |
||
532 | /* - End of conversion selection */ |
||
533 | /* - DMA continuous request */ |
||
534 | /* - Channels bank (Banks availability depends on devices categories) */ |
||
535 | /* - continuous conversion mode */ |
||
536 | tmp_cr2 |= (hadc->Init.DataAlign | |
||
537 | hadc->Init.EOCSelection | |
||
538 | ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) | |
||
539 | hadc->Init.ChannelsBank | |
||
540 | ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); |
||
541 | |||
542 | /* Enable external trigger if trigger selection is different of software */ |
||
543 | /* start. */ |
||
544 | /* Note: This configuration keeps the hardware feature of parameter */ |
||
545 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
||
546 | /* software start. */ |
||
547 | if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
||
548 | { |
||
549 | tmp_cr2 |= ( hadc->Init.ExternalTrigConv | |
||
550 | hadc->Init.ExternalTrigConvEdge ); |
||
551 | } |
||
552 | |||
553 | /* Parameters update conditioned to ADC state: */ |
||
554 | /* Parameters that can be updated only when ADC is disabled: */ |
||
555 | /* - delay selection (LowPowerAutoWait mode) */ |
||
556 | /* - resolution */ |
||
557 | /* - auto power off (LowPowerAutoPowerOff mode) */ |
||
558 | /* - scan mode */ |
||
559 | /* - discontinuous mode disable/enable */ |
||
560 | /* - discontinuous mode number of conversions */ |
||
561 | if ((ADC_IS_ENABLE(hadc) == RESET)) |
||
562 | { |
||
563 | tmp_cr2 |= hadc->Init.LowPowerAutoWait; |
||
564 | |||
565 | tmp_cr1 |= (hadc->Init.Resolution | |
||
566 | hadc->Init.LowPowerAutoPowerOff | |
||
567 | ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) ); |
||
568 | |||
569 | /* Enable discontinuous mode only if continuous mode is disabled */ |
||
570 | /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ |
||
571 | /* discontinuous is set anyway, but has no effect on ADC HW. */ |
||
572 | if (hadc->Init.DiscontinuousConvMode == ENABLE) |
||
573 | { |
||
574 | if (hadc->Init.ContinuousConvMode == DISABLE) |
||
575 | { |
||
576 | /* Enable the selected ADC regular discontinuous mode */ |
||
577 | /* Set the number of channels to be converted in discontinuous mode */ |
||
578 | SET_BIT(tmp_cr1, ADC_CR1_DISCEN | |
||
579 | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); |
||
580 | } |
||
581 | else |
||
582 | { |
||
583 | /* ADC regular group settings continuous and sequencer discontinuous*/ |
||
584 | /* cannot be enabled simultaneously. */ |
||
585 | |||
586 | /* Update ADC state machine to error */ |
||
587 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
588 | |||
589 | /* Set ADC error code to ADC IP internal error */ |
||
590 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
591 | } |
||
592 | } |
||
593 | |||
594 | /* Update ADC configuration register CR1 with previous settings */ |
||
595 | MODIFY_REG(hadc->Instance->CR1, |
||
596 | ADC_CR1_RES | |
||
597 | ADC_CR1_PDI | |
||
598 | ADC_CR1_PDD | |
||
599 | ADC_CR1_DISCNUM | |
||
600 | ADC_CR1_DISCEN | |
||
601 | ADC_CR1_SCAN , |
||
602 | tmp_cr1 ); |
||
603 | } |
||
604 | |||
605 | /* Update ADC configuration register CR2 with previous settings */ |
||
606 | MODIFY_REG(hadc->Instance->CR2 , |
||
607 | ADC_CR2_MASK_ADCINIT() , |
||
608 | tmp_cr2 ); |
||
609 | |||
610 | /* Configuration of regular group sequencer: */ |
||
611 | /* - if scan mode is disabled, regular channels sequence length is set to */ |
||
612 | /* 0x00: 1 channel converted (channel on regular rank 1) */ |
||
613 | /* Parameter "NbrOfConversion" is discarded. */ |
||
614 | /* Note: Scan mode is present by hardware on this device and, if */ |
||
615 | /* disabled, discards automatically nb of conversions. Anyway, nb of */ |
||
616 | /* conversions is forced to 0x00 for alignment over all STM32 devices. */ |
||
617 | /* - if scan mode is enabled, regular channels sequence length is set to */ |
||
618 | /* parameter "NbrOfConversion" */ |
||
619 | if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) |
||
620 | { |
||
621 | MODIFY_REG(hadc->Instance->SQR1 , |
||
622 | ADC_SQR1_L , |
||
623 | ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion) ); |
||
624 | } |
||
625 | else |
||
626 | { |
||
627 | MODIFY_REG(hadc->Instance->SQR1, |
||
628 | ADC_SQR1_L , |
||
629 | 0x00000000 ); |
||
630 | } |
||
631 | |||
632 | /* Check back that ADC registers have effectively been configured to */ |
||
633 | /* ensure of no potential problem of ADC core IP clocking. */ |
||
634 | /* Check through register CR2 (excluding execution control bits ADON, */ |
||
635 | /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */ |
||
636 | if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON | |
||
637 | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | |
||
638 | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL )) |
||
639 | == tmp_cr2) |
||
640 | { |
||
641 | /* Set ADC error code to none */ |
||
642 | ADC_CLEAR_ERRORCODE(hadc); |
||
643 | |||
644 | /* Set the ADC state */ |
||
645 | ADC_STATE_CLR_SET(hadc->State, |
||
646 | HAL_ADC_STATE_BUSY_INTERNAL, |
||
647 | HAL_ADC_STATE_READY); |
||
648 | } |
||
649 | else |
||
650 | { |
||
651 | /* Update ADC state machine to error */ |
||
652 | ADC_STATE_CLR_SET(hadc->State, |
||
653 | HAL_ADC_STATE_BUSY_INTERNAL, |
||
654 | HAL_ADC_STATE_ERROR_INTERNAL); |
||
655 | |||
656 | /* Set ADC error code to ADC IP internal error */ |
||
657 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
658 | |||
659 | tmp_hal_status = HAL_ERROR; |
||
660 | } |
||
661 | |||
662 | } |
||
663 | else |
||
664 | { |
||
665 | tmp_hal_status = HAL_ERROR; |
||
666 | } |
||
667 | |||
668 | /* Return function status */ |
||
669 | return tmp_hal_status; |
||
670 | } |
||
671 | |||
672 | /** |
||
673 | * @brief Deinitialize the ADC peripheral registers to its default reset values. |
||
674 | * @note To not impact other ADCs, reset of common ADC registers have been |
||
675 | * left commented below. |
||
676 | * If needed, the example code can be copied and uncommented into |
||
677 | * function HAL_ADC_MspDeInit(). |
||
678 | * @param hadc ADC handle |
||
679 | * @retval HAL status |
||
680 | */ |
||
681 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
||
682 | { |
||
683 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
684 | |||
685 | /* Check ADC handle */ |
||
686 | if(hadc == NULL) |
||
687 | { |
||
688 | return HAL_ERROR; |
||
689 | } |
||
690 | |||
691 | /* Check the parameters */ |
||
692 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
693 | |||
694 | /* Set ADC state */ |
||
695 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
||
696 | |||
697 | /* Stop potential conversion on going, on regular and injected groups */ |
||
698 | /* Disable ADC peripheral */ |
||
699 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
700 | |||
701 | |||
702 | /* Configuration of ADC parameters if previous preliminary actions are */ |
||
703 | /* correctly completed. */ |
||
704 | if (tmp_hal_status == HAL_OK) |
||
705 | { |
||
706 | /* ========== Reset ADC registers ========== */ |
||
707 | /* Reset register SR */ |
||
708 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | |
||
709 | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); |
||
710 | |||
711 | /* Reset register CR1 */ |
||
712 | CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN | |
||
713 | ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD | |
||
714 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | |
||
715 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | |
||
716 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE | |
||
717 | ADC_CR1_AWDCH )); |
||
718 | |||
719 | /* Reset register CR2 */ |
||
720 | ADC_CR2_CLEAR(hadc); |
||
721 | |||
722 | /* Reset register SMPR0 */ |
||
723 | ADC_SMPR0_CLEAR(hadc); |
||
724 | |||
725 | /* Reset register SMPR1 */ |
||
726 | ADC_SMPR1_CLEAR(hadc); |
||
727 | |||
728 | /* Reset register SMPR2 */ |
||
729 | CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | |
||
730 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | |
||
731 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | |
||
732 | ADC_SMPR2_SMP10 )); |
||
733 | |||
734 | /* Reset register SMPR3 */ |
||
735 | CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 | |
||
736 | ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 | |
||
737 | ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 | |
||
738 | ADC_SMPR3_SMP0 )); |
||
739 | |||
740 | /* Reset register JOFR1 */ |
||
741 | CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); |
||
742 | /* Reset register JOFR2 */ |
||
743 | CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); |
||
744 | /* Reset register JOFR3 */ |
||
745 | CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); |
||
746 | /* Reset register JOFR4 */ |
||
747 | CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); |
||
748 | |||
749 | /* Reset register HTR */ |
||
750 | CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); |
||
751 | /* Reset register LTR */ |
||
752 | CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); |
||
753 | |||
754 | /* Reset register SQR1 */ |
||
755 | CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L | __ADC_SQR1_SQXX)); |
||
756 | |||
757 | /* Reset register SQR2 */ |
||
758 | CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 | |
||
759 | ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19 )); |
||
760 | |||
761 | /* Reset register SQR3 */ |
||
762 | CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 | |
||
763 | ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13 )); |
||
764 | |||
765 | /* Reset register SQR4 */ |
||
766 | CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 | |
||
767 | ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 )); |
||
768 | |||
769 | /* Reset register SQR5 */ |
||
770 | CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 | |
||
771 | ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 )); |
||
772 | |||
773 | |||
774 | /* Reset register JSQR */ |
||
775 | CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL | |
||
776 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | |
||
777 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )); |
||
778 | |||
779 | /* Reset register DR */ |
||
780 | /* bits in access mode read only, no direct reset applicable*/ |
||
781 | |||
782 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
||
783 | /* bits in access mode read only, no direct reset applicable*/ |
||
784 | |||
785 | /* Reset register CCR */ |
||
786 | CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE); |
||
787 | |||
788 | /* ========== Hard reset ADC peripheral ========== */ |
||
789 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
||
790 | /* forced to a similar state after device power-on. */ |
||
791 | /* If needed, copy-paste and uncomment the following reset code into */ |
||
792 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
||
793 | /* */ |
||
794 | /* __HAL_RCC_ADC1_FORCE_RESET() */ |
||
795 | /* __HAL_RCC_ADC1_RELEASE_RESET() */ |
||
796 | |||
797 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
798 | if (hadc->MspDeInitCallback == NULL) |
||
799 | { |
||
800 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
801 | } |
||
802 | |||
803 | /* DeInit the low level hardware */ |
||
804 | hadc->MspDeInitCallback(hadc); |
||
805 | #else |
||
806 | /* DeInit the low level hardware */ |
||
807 | HAL_ADC_MspDeInit(hadc); |
||
808 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
809 | |||
810 | /* Set ADC error code to none */ |
||
811 | ADC_CLEAR_ERRORCODE(hadc); |
||
812 | |||
813 | /* Set ADC state */ |
||
814 | hadc->State = HAL_ADC_STATE_RESET; |
||
815 | |||
816 | } |
||
817 | |||
818 | /* Process unlocked */ |
||
819 | __HAL_UNLOCK(hadc); |
||
820 | |||
821 | /* Return function status */ |
||
822 | return tmp_hal_status; |
||
823 | } |
||
824 | |||
825 | /** |
||
826 | * @brief Initializes the ADC MSP. |
||
827 | * @param hadc ADC handle |
||
828 | * @retval None |
||
829 | */ |
||
830 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
||
831 | { |
||
832 | /* Prevent unused argument(s) compilation warning */ |
||
833 | UNUSED(hadc); |
||
834 | |||
835 | /* NOTE : This function should not be modified. When the callback is needed, |
||
836 | function HAL_ADC_MspInit must be implemented in the user file. |
||
837 | */ |
||
838 | } |
||
839 | |||
840 | /** |
||
841 | * @brief DeInitializes the ADC MSP. |
||
842 | * @param hadc ADC handle |
||
843 | * @retval None |
||
844 | */ |
||
845 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
||
846 | { |
||
847 | /* Prevent unused argument(s) compilation warning */ |
||
848 | UNUSED(hadc); |
||
849 | |||
850 | /* NOTE : This function should not be modified. When the callback is needed, |
||
851 | function HAL_ADC_MspDeInit must be implemented in the user file. |
||
852 | */ |
||
853 | } |
||
854 | |||
855 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
856 | /** |
||
857 | * @brief Register a User ADC Callback |
||
858 | * To be used instead of the weak predefined callback |
||
859 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
||
860 | * the configuration information for the specified ADC. |
||
861 | * @param CallbackID ID of the callback to be registered |
||
862 | * This parameter can be one of the following values: |
||
863 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
||
864 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
||
865 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
||
866 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
||
867 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
||
868 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
||
869 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
||
870 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
||
871 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
||
872 | * @param pCallback pointer to the Callback function |
||
873 | * @retval HAL status |
||
874 | */ |
||
875 | HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) |
||
876 | { |
||
877 | HAL_StatusTypeDef status = HAL_OK; |
||
878 | |||
879 | if (pCallback == NULL) |
||
880 | { |
||
881 | /* Update the error code */ |
||
882 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
883 | |||
884 | return HAL_ERROR; |
||
885 | } |
||
886 | |||
887 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
||
888 | { |
||
889 | switch (CallbackID) |
||
890 | { |
||
891 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
||
892 | hadc->ConvCpltCallback = pCallback; |
||
893 | break; |
||
894 | |||
895 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
||
896 | hadc->ConvHalfCpltCallback = pCallback; |
||
897 | break; |
||
898 | |||
899 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
||
900 | hadc->LevelOutOfWindowCallback = pCallback; |
||
901 | break; |
||
902 | |||
903 | case HAL_ADC_ERROR_CB_ID : |
||
904 | hadc->ErrorCallback = pCallback; |
||
905 | break; |
||
906 | |||
907 | case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : |
||
908 | hadc->InjectedConvCpltCallback = pCallback; |
||
909 | break; |
||
910 | |||
911 | case HAL_ADC_MSPINIT_CB_ID : |
||
912 | hadc->MspInitCallback = pCallback; |
||
913 | break; |
||
914 | |||
915 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
916 | hadc->MspDeInitCallback = pCallback; |
||
917 | break; |
||
918 | |||
919 | default : |
||
920 | /* Update the error code */ |
||
921 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
922 | |||
923 | /* Return error status */ |
||
924 | status = HAL_ERROR; |
||
925 | break; |
||
926 | } |
||
927 | } |
||
928 | else if (HAL_ADC_STATE_RESET == hadc->State) |
||
929 | { |
||
930 | switch (CallbackID) |
||
931 | { |
||
932 | case HAL_ADC_MSPINIT_CB_ID : |
||
933 | hadc->MspInitCallback = pCallback; |
||
934 | break; |
||
935 | |||
936 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
937 | hadc->MspDeInitCallback = pCallback; |
||
938 | break; |
||
939 | |||
940 | default : |
||
941 | /* Update the error code */ |
||
942 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
943 | |||
944 | /* Return error status */ |
||
945 | status = HAL_ERROR; |
||
946 | break; |
||
947 | } |
||
948 | } |
||
949 | else |
||
950 | { |
||
951 | /* Update the error code */ |
||
952 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
953 | |||
954 | /* Return error status */ |
||
955 | status = HAL_ERROR; |
||
956 | } |
||
957 | |||
958 | return status; |
||
959 | } |
||
960 | |||
961 | /** |
||
962 | * @brief Unregister a ADC Callback |
||
963 | * ADC callback is redirected to the weak predefined callback |
||
964 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
||
965 | * the configuration information for the specified ADC. |
||
966 | * @param CallbackID ID of the callback to be unregistered |
||
967 | * This parameter can be one of the following values: |
||
968 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
||
969 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
||
970 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
||
971 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
||
972 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
||
973 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
||
974 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
||
975 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
||
976 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
||
977 | * @retval HAL status |
||
978 | */ |
||
979 | HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) |
||
980 | { |
||
981 | HAL_StatusTypeDef status = HAL_OK; |
||
982 | |||
983 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
||
984 | { |
||
985 | switch (CallbackID) |
||
986 | { |
||
987 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
||
988 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; |
||
989 | break; |
||
990 | |||
991 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
||
992 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; |
||
993 | break; |
||
994 | |||
995 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
||
996 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; |
||
997 | break; |
||
998 | |||
999 | case HAL_ADC_ERROR_CB_ID : |
||
1000 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; |
||
1001 | break; |
||
1002 | |||
1003 | case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : |
||
1004 | hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; |
||
1005 | break; |
||
1006 | |||
1007 | case HAL_ADC_MSPINIT_CB_ID : |
||
1008 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
1009 | break; |
||
1010 | |||
1011 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
1012 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
1013 | break; |
||
1014 | |||
1015 | default : |
||
1016 | /* Update the error code */ |
||
1017 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
1018 | |||
1019 | /* Return error status */ |
||
1020 | status = HAL_ERROR; |
||
1021 | break; |
||
1022 | } |
||
1023 | } |
||
1024 | else if (HAL_ADC_STATE_RESET == hadc->State) |
||
1025 | { |
||
1026 | switch (CallbackID) |
||
1027 | { |
||
1028 | case HAL_ADC_MSPINIT_CB_ID : |
||
1029 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
1030 | break; |
||
1031 | |||
1032 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
1033 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
1034 | break; |
||
1035 | |||
1036 | default : |
||
1037 | /* Update the error code */ |
||
1038 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
1039 | |||
1040 | /* Return error status */ |
||
1041 | status = HAL_ERROR; |
||
1042 | break; |
||
1043 | } |
||
1044 | } |
||
1045 | else |
||
1046 | { |
||
1047 | /* Update the error code */ |
||
1048 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
1049 | |||
1050 | /* Return error status */ |
||
1051 | status = HAL_ERROR; |
||
1052 | } |
||
1053 | |||
1054 | return status; |
||
1055 | } |
||
1056 | |||
1057 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
1058 | |||
1059 | /** |
||
1060 | * @} |
||
1061 | */ |
||
1062 | |||
1063 | /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions |
||
1064 | * @brief ADC IO operation functions |
||
1065 | * |
||
1066 | @verbatim |
||
1067 | =============================================================================== |
||
1068 | ##### IO operation functions ##### |
||
1069 | =============================================================================== |
||
1070 | [..] This section provides functions allowing to: |
||
1071 | (+) Start conversion of regular group. |
||
1072 | (+) Stop conversion of regular group. |
||
1073 | (+) Poll for conversion complete on regular group. |
||
1074 | (+) Poll for conversion event. |
||
1075 | (+) Get result of regular channel conversion. |
||
1076 | (+) Start conversion of regular group and enable interruptions. |
||
1077 | (+) Stop conversion of regular group and disable interruptions. |
||
1078 | (+) Handle ADC interrupt request |
||
1079 | (+) Start conversion of regular group and enable DMA transfer. |
||
1080 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
||
1081 | @endverbatim |
||
1082 | * @{ |
||
1083 | */ |
||
1084 | |||
1085 | /** |
||
1086 | * @brief Enables ADC, starts conversion of regular group. |
||
1087 | * Interruptions enabled in this function: None. |
||
1088 | * @param hadc ADC handle |
||
1089 | * @retval HAL status |
||
1090 | */ |
||
1091 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
||
1092 | { |
||
1093 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1094 | |||
1095 | /* Check the parameters */ |
||
1096 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1097 | |||
1098 | /* Process locked */ |
||
1099 | __HAL_LOCK(hadc); |
||
1100 | |||
1101 | /* Enable the ADC peripheral */ |
||
1102 | tmp_hal_status = ADC_Enable(hadc); |
||
1103 | |||
1104 | /* Start conversion if ADC is effectively enabled */ |
||
1105 | if (tmp_hal_status == HAL_OK) |
||
1106 | { |
||
1107 | /* Set ADC state */ |
||
1108 | /* - Clear state bitfield related to regular group conversion results */ |
||
1109 | /* - Set state bitfield related to regular group operation */ |
||
1110 | ADC_STATE_CLR_SET(hadc->State, |
||
1111 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
||
1112 | HAL_ADC_STATE_REG_BUSY); |
||
1113 | |||
1114 | /* If conversions on group regular are also triggering group injected, */ |
||
1115 | /* update ADC state. */ |
||
1116 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
||
1117 | { |
||
1118 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
1119 | } |
||
1120 | |||
1121 | /* State machine update: Check if an injected conversion is ongoing */ |
||
1122 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
1123 | { |
||
1124 | /* Reset ADC error code fields related to conversions on group regular */ |
||
1125 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
||
1126 | } |
||
1127 | else |
||
1128 | { |
||
1129 | /* Reset ADC all error code fields */ |
||
1130 | ADC_CLEAR_ERRORCODE(hadc); |
||
1131 | } |
||
1132 | |||
1133 | /* Process unlocked */ |
||
1134 | /* Unlock before starting ADC conversions: in case of potential */ |
||
1135 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
1136 | __HAL_UNLOCK(hadc); |
||
1137 | |||
1138 | /* Clear regular group conversion flag and overrun flag */ |
||
1139 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
||
1140 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
||
1141 | |||
1142 | /* Enable conversion of regular group. */ |
||
1143 | /* If software start has been selected, conversion starts immediately. */ |
||
1144 | /* If external trigger has been selected, conversion will start at next */ |
||
1145 | /* trigger event. */ |
||
1146 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
||
1147 | { |
||
1148 | /* Start ADC conversion on regular group */ |
||
1149 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
||
1150 | } |
||
1151 | } |
||
1152 | |||
1153 | /* Return function status */ |
||
1154 | return tmp_hal_status; |
||
1155 | } |
||
1156 | |||
1157 | /** |
||
1158 | * @brief Stop ADC conversion of regular group (and injected channels in |
||
1159 | * case of auto_injection mode), disable ADC peripheral. |
||
1160 | * @note: ADC peripheral disable is forcing stop of potential |
||
1161 | * conversion on injected group. If injected group is under use, it |
||
1162 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
||
1163 | * @param hadc ADC handle |
||
1164 | * @retval HAL status. |
||
1165 | */ |
||
1166 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
||
1167 | { |
||
1168 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1169 | |||
1170 | /* Check the parameters */ |
||
1171 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1172 | |||
1173 | /* Process locked */ |
||
1174 | __HAL_LOCK(hadc); |
||
1175 | |||
1176 | /* Stop potential conversion on going, on regular and injected groups */ |
||
1177 | /* Disable ADC peripheral */ |
||
1178 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
1179 | |||
1180 | /* Check if ADC is effectively disabled */ |
||
1181 | if (tmp_hal_status == HAL_OK) |
||
1182 | { |
||
1183 | /* Set ADC state */ |
||
1184 | ADC_STATE_CLR_SET(hadc->State, |
||
1185 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
1186 | HAL_ADC_STATE_READY); |
||
1187 | } |
||
1188 | |||
1189 | /* Process unlocked */ |
||
1190 | __HAL_UNLOCK(hadc); |
||
1191 | |||
1192 | /* Return function status */ |
||
1193 | return tmp_hal_status; |
||
1194 | } |
||
1195 | |||
1196 | /** |
||
1197 | * @brief Wait for regular group conversion to be completed. |
||
1198 | * @note ADC conversion flags EOS (end of sequence) and EOC (end of |
||
1199 | * conversion) are cleared by this function, with an exception: |
||
1200 | * if low power feature "LowPowerAutoWait" is enabled, flags are |
||
1201 | * not cleared to not interfere with this feature until data register |
||
1202 | * is read using function HAL_ADC_GetValue(). |
||
1203 | * @note This function cannot be used in a particular setup: ADC configured |
||
1204 | * in DMA mode and polling for end of each conversion (ADC init |
||
1205 | * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). |
||
1206 | * In this case, DMA resets the flag EOC and polling cannot be |
||
1207 | * performed on each conversion. Nevertheless, polling can still |
||
1208 | * be performed on the complete sequence (ADC init |
||
1209 | * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). |
||
1210 | * @param hadc ADC handle |
||
1211 | * @param Timeout Timeout value in millisecond. |
||
1212 | * @retval HAL status |
||
1213 | */ |
||
1214 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
||
1215 | { |
||
1216 | uint32_t tickstart = 0; |
||
1217 | |||
1218 | /* Check the parameters */ |
||
1219 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1220 | |||
1221 | /* Verification that ADC configuration is compliant with polling for */ |
||
1222 | /* each conversion: */ |
||
1223 | /* Particular case is ADC configured in DMA mode and ADC sequencer with */ |
||
1224 | /* several ranks and polling for end of each conversion. */ |
||
1225 | /* For code simplicity sake, this particular case is generalized to */ |
||
1226 | /* ADC configured in DMA mode and and polling for end of each conversion. */ |
||
1227 | if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && |
||
1228 | HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) |
||
1229 | { |
||
1230 | /* Update ADC state machine to error */ |
||
1231 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
1232 | |||
1233 | /* Process unlocked */ |
||
1234 | __HAL_UNLOCK(hadc); |
||
1235 | |||
1236 | return HAL_ERROR; |
||
1237 | } |
||
1238 | |||
1239 | /* Get tick count */ |
||
1240 | tickstart = HAL_GetTick(); |
||
1241 | |||
1242 | /* Wait until End of Conversion flag is raised */ |
||
1243 | while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) |
||
1244 | { |
||
1245 | /* Check if timeout is disabled (set to infinite wait) */ |
||
1246 | if(Timeout != HAL_MAX_DELAY) |
||
1247 | { |
||
1248 | if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) |
||
1249 | { |
||
1250 | /* Update ADC state machine to timeout */ |
||
1251 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
||
1252 | |||
1253 | /* Process unlocked */ |
||
1254 | __HAL_UNLOCK(hadc); |
||
1255 | |||
1256 | return HAL_TIMEOUT; |
||
1257 | } |
||
1258 | } |
||
1259 | } |
||
1260 | |||
1261 | /* Clear end of conversion flag of regular group if low power feature */ |
||
1262 | /* "Auto Wait" is disabled, to not interfere with this feature until data */ |
||
1263 | /* register is read using function HAL_ADC_GetValue(). */ |
||
1264 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
||
1265 | { |
||
1266 | /* Clear regular group conversion flag */ |
||
1267 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
||
1268 | } |
||
1269 | |||
1270 | /* Update ADC state machine */ |
||
1271 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
1272 | |||
1273 | /* Determine whether any further conversion upcoming on group regular */ |
||
1274 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
1275 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
||
1276 | /* The test of scan sequence on going is done either with scan */ |
||
1277 | /* sequence disabled or with end of conversion flag set to */ |
||
1278 | /* of end of sequence. */ |
||
1279 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
1280 | (hadc->Init.ContinuousConvMode == DISABLE) && |
||
1281 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
||
1282 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
||
1283 | { |
||
1284 | /* Set ADC state */ |
||
1285 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
||
1286 | |||
1287 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
1288 | { |
||
1289 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
1290 | } |
||
1291 | } |
||
1292 | |||
1293 | /* Return ADC state */ |
||
1294 | return HAL_OK; |
||
1295 | } |
||
1296 | |||
1297 | /** |
||
1298 | * @brief Poll for conversion event. |
||
1299 | * @param hadc ADC handle |
||
1300 | * @param EventType the ADC event type. |
||
1301 | * This parameter can be one of the following values: |
||
1302 | * @arg ADC_AWD_EVENT: ADC Analog watchdog event. |
||
1303 | * @arg ADC_OVR_EVENT: ADC Overrun event. |
||
1304 | * @param Timeout Timeout value in millisecond. |
||
1305 | * @retval HAL status |
||
1306 | */ |
||
1307 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
||
1308 | { |
||
1309 | uint32_t tickstart = 0; |
||
1310 | |||
1311 | /* Check the parameters */ |
||
1312 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1313 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
||
1314 | |||
1315 | /* Get tick count */ |
||
1316 | tickstart = HAL_GetTick(); |
||
1317 | |||
1318 | /* Check selected event flag */ |
||
1319 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
||
1320 | { |
||
1321 | /* Check if timeout is disabled (set to infinite wait) */ |
||
1322 | if(Timeout != HAL_MAX_DELAY) |
||
1323 | { |
||
1324 | if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) |
||
1325 | { |
||
1326 | /* Update ADC state machine to timeout */ |
||
1327 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
||
1328 | |||
1329 | /* Process unlocked */ |
||
1330 | __HAL_UNLOCK(hadc); |
||
1331 | |||
1332 | return HAL_TIMEOUT; |
||
1333 | } |
||
1334 | } |
||
1335 | } |
||
1336 | |||
1337 | switch(EventType) |
||
1338 | { |
||
1339 | /* Analog watchdog (level out of window) event */ |
||
1340 | case ADC_AWD_EVENT: |
||
1341 | /* Set ADC state */ |
||
1342 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
||
1343 | |||
1344 | /* Clear ADC analog watchdog flag */ |
||
1345 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
||
1346 | break; |
||
1347 | |||
1348 | /* Overrun event */ |
||
1349 | default: /* Case ADC_OVR_EVENT */ |
||
1350 | /* Note: On STM32L1, ADC overrun can be set through other parameters */ |
||
1351 | /* refer to description of parameter "EOCSelection" for more */ |
||
1352 | /* details. */ |
||
1353 | |||
1354 | /* Set ADC state */ |
||
1355 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); |
||
1356 | /* Set ADC error code to overrun */ |
||
1357 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
||
1358 | |||
1359 | /* Clear ADC overrun flag */ |
||
1360 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
||
1361 | break; |
||
1362 | } |
||
1363 | |||
1364 | /* Return ADC state */ |
||
1365 | return HAL_OK; |
||
1366 | } |
||
1367 | |||
1368 | /** |
||
1369 | * @brief Enables ADC, starts conversion of regular group with interruption. |
||
1370 | * Interruptions enabled in this function: |
||
1371 | * - EOC (end of conversion of regular group) |
||
1372 | * - overrun |
||
1373 | * Each of these interruptions has its dedicated callback function. |
||
1374 | * @param hadc ADC handle |
||
1375 | * @retval HAL status |
||
1376 | */ |
||
1377 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
||
1378 | { |
||
1379 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1380 | |||
1381 | /* Check the parameters */ |
||
1382 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1383 | |||
1384 | /* Process locked */ |
||
1385 | __HAL_LOCK(hadc); |
||
1386 | |||
1387 | /* Enable the ADC peripheral */ |
||
1388 | tmp_hal_status = ADC_Enable(hadc); |
||
1389 | |||
1390 | /* Start conversion if ADC is effectively enabled */ |
||
1391 | if (tmp_hal_status == HAL_OK) |
||
1392 | { |
||
1393 | /* Set ADC state */ |
||
1394 | /* - Clear state bitfield related to regular group conversion results */ |
||
1395 | /* - Set state bitfield related to regular group operation */ |
||
1396 | ADC_STATE_CLR_SET(hadc->State, |
||
1397 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
||
1398 | HAL_ADC_STATE_REG_BUSY); |
||
1399 | |||
1400 | /* If conversions on group regular are also triggering group injected, */ |
||
1401 | /* update ADC state. */ |
||
1402 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
||
1403 | { |
||
1404 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
1405 | } |
||
1406 | |||
1407 | /* State machine update: Check if an injected conversion is ongoing */ |
||
1408 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
1409 | { |
||
1410 | /* Reset ADC error code fields related to conversions on group regular */ |
||
1411 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
||
1412 | } |
||
1413 | else |
||
1414 | { |
||
1415 | /* Reset ADC all error code fields */ |
||
1416 | ADC_CLEAR_ERRORCODE(hadc); |
||
1417 | } |
||
1418 | |||
1419 | /* Process unlocked */ |
||
1420 | /* Unlock before starting ADC conversions: in case of potential */ |
||
1421 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
1422 | __HAL_UNLOCK(hadc); |
||
1423 | |||
1424 | /* Clear regular group conversion flag and overrun flag */ |
||
1425 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
||
1426 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
||
1427 | |||
1428 | /* Enable end of conversion interrupt for regular group */ |
||
1429 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); |
||
1430 | |||
1431 | /* Enable conversion of regular group. */ |
||
1432 | /* If software start has been selected, conversion starts immediately. */ |
||
1433 | /* If external trigger has been selected, conversion will start at next */ |
||
1434 | /* trigger event. */ |
||
1435 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
||
1436 | { |
||
1437 | /* Start ADC conversion on regular group */ |
||
1438 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
||
1439 | } |
||
1440 | } |
||
1441 | |||
1442 | /* Return function status */ |
||
1443 | return tmp_hal_status; |
||
1444 | } |
||
1445 | |||
1446 | /** |
||
1447 | * @brief Stop ADC conversion of regular group (and injected group in |
||
1448 | * case of auto_injection mode), disable interrution of |
||
1449 | * end-of-conversion, disable ADC peripheral. |
||
1450 | * @param hadc ADC handle |
||
1451 | * @retval None |
||
1452 | */ |
||
1453 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
||
1454 | { |
||
1455 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1456 | |||
1457 | /* Check the parameters */ |
||
1458 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1459 | |||
1460 | /* Process locked */ |
||
1461 | __HAL_LOCK(hadc); |
||
1462 | |||
1463 | /* Stop potential conversion on going, on regular and injected groups */ |
||
1464 | /* Disable ADC peripheral */ |
||
1465 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
1466 | |||
1467 | /* Check if ADC is effectively disabled */ |
||
1468 | if (tmp_hal_status == HAL_OK) |
||
1469 | { |
||
1470 | /* Disable ADC end of conversion interrupt for regular group */ |
||
1471 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
||
1472 | |||
1473 | /* Set ADC state */ |
||
1474 | ADC_STATE_CLR_SET(hadc->State, |
||
1475 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
1476 | HAL_ADC_STATE_READY); |
||
1477 | } |
||
1478 | |||
1479 | /* Process unlocked */ |
||
1480 | __HAL_UNLOCK(hadc); |
||
1481 | |||
1482 | /* Return function status */ |
||
1483 | return tmp_hal_status; |
||
1484 | } |
||
1485 | |||
1486 | /** |
||
1487 | * @brief Enables ADC, starts conversion of regular group and transfers result |
||
1488 | * through DMA. |
||
1489 | * Interruptions enabled in this function: |
||
1490 | * - DMA transfer complete |
||
1491 | * - DMA half transfer |
||
1492 | * - overrun |
||
1493 | * Each of these interruptions has its dedicated callback function. |
||
1494 | * @param hadc ADC handle |
||
1495 | * @param pData The destination Buffer address. |
||
1496 | * @param Length The length of data to be transferred from ADC peripheral to memory. |
||
1497 | * @retval None |
||
1498 | */ |
||
1499 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
||
1500 | { |
||
1501 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1502 | |||
1503 | /* Check the parameters */ |
||
1504 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1505 | |||
1506 | /* Process locked */ |
||
1507 | __HAL_LOCK(hadc); |
||
1508 | |||
1509 | /* Enable the ADC peripheral */ |
||
1510 | tmp_hal_status = ADC_Enable(hadc); |
||
1511 | |||
1512 | /* Start conversion if ADC is effectively enabled */ |
||
1513 | if (tmp_hal_status == HAL_OK) |
||
1514 | { |
||
1515 | /* Set ADC state */ |
||
1516 | /* - Clear state bitfield related to regular group conversion results */ |
||
1517 | /* - Set state bitfield related to regular group operation */ |
||
1518 | ADC_STATE_CLR_SET(hadc->State, |
||
1519 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, |
||
1520 | HAL_ADC_STATE_REG_BUSY); |
||
1521 | |||
1522 | /* If conversions on group regular are also triggering group injected, */ |
||
1523 | /* update ADC state. */ |
||
1524 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
||
1525 | { |
||
1526 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
||
1527 | } |
||
1528 | |||
1529 | /* State machine update: Check if an injected conversion is ongoing */ |
||
1530 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
1531 | { |
||
1532 | /* Reset ADC error code fields related to conversions on group regular */ |
||
1533 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
||
1534 | } |
||
1535 | else |
||
1536 | { |
||
1537 | /* Reset ADC all error code fields */ |
||
1538 | ADC_CLEAR_ERRORCODE(hadc); |
||
1539 | } |
||
1540 | |||
1541 | /* Process unlocked */ |
||
1542 | /* Unlock before starting ADC conversions: in case of potential */ |
||
1543 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
1544 | __HAL_UNLOCK(hadc); |
||
1545 | |||
1546 | /* Set the DMA transfer complete callback */ |
||
1547 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
||
1548 | |||
1549 | /* Set the DMA half transfer complete callback */ |
||
1550 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
||
1551 | |||
1552 | /* Set the DMA error callback */ |
||
1553 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
||
1554 | |||
1555 | |||
1556 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
||
1557 | /* start (in case of SW start): */ |
||
1558 | |||
1559 | /* Clear regular group conversion flag and overrun flag */ |
||
1560 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
||
1561 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); |
||
1562 | |||
1563 | /* Enable ADC overrun interrupt */ |
||
1564 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
||
1565 | |||
1566 | /* Enable ADC DMA mode */ |
||
1567 | hadc->Instance->CR2 |= ADC_CR2_DMA; |
||
1568 | |||
1569 | /* Start the DMA channel */ |
||
1570 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
||
1571 | |||
1572 | /* Enable conversion of regular group. */ |
||
1573 | /* If software start has been selected, conversion starts immediately. */ |
||
1574 | /* If external trigger has been selected, conversion will start at next */ |
||
1575 | /* trigger event. */ |
||
1576 | /* Note: Alternate trigger for single conversion could be to force an */ |
||
1577 | /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ |
||
1578 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
||
1579 | { |
||
1580 | /* Start ADC conversion on regular group */ |
||
1581 | SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); |
||
1582 | } |
||
1583 | } |
||
1584 | |||
1585 | /* Return function status */ |
||
1586 | return tmp_hal_status; |
||
1587 | } |
||
1588 | |||
1589 | /** |
||
1590 | * @brief Stop ADC conversion of regular group (and injected group in |
||
1591 | * case of auto_injection mode), disable ADC DMA transfer, disable |
||
1592 | * ADC peripheral. |
||
1593 | * @note: ADC peripheral disable is forcing stop of potential |
||
1594 | * conversion on injected group. If injected group is under use, it |
||
1595 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
||
1596 | * @param hadc ADC handle |
||
1597 | * @retval HAL status. |
||
1598 | */ |
||
1599 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
||
1600 | { |
||
1601 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1602 | |||
1603 | /* Check the parameters */ |
||
1604 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1605 | |||
1606 | /* Process locked */ |
||
1607 | __HAL_LOCK(hadc); |
||
1608 | |||
1609 | /* Stop potential conversion on going, on regular and injected groups */ |
||
1610 | /* Disable ADC peripheral */ |
||
1611 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
||
1612 | |||
1613 | /* Check if ADC is effectively disabled */ |
||
1614 | if (tmp_hal_status == HAL_OK) |
||
1615 | { |
||
1616 | /* Disable ADC DMA mode */ |
||
1617 | hadc->Instance->CR2 &= ~ADC_CR2_DMA; |
||
1618 | |||
1619 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
||
1620 | /* DMA transfer is on going) */ |
||
1621 | HAL_DMA_Abort(hadc->DMA_Handle); |
||
1622 | |||
1623 | /* Set ADC state */ |
||
1624 | ADC_STATE_CLR_SET(hadc->State, |
||
1625 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
||
1626 | HAL_ADC_STATE_READY); |
||
1627 | |||
1628 | /* Disable ADC overrun interrupt */ |
||
1629 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
||
1630 | } |
||
1631 | |||
1632 | /* Process unlocked */ |
||
1633 | __HAL_UNLOCK(hadc); |
||
1634 | |||
1635 | /* Return function status */ |
||
1636 | return tmp_hal_status; |
||
1637 | } |
||
1638 | |||
1639 | /** |
||
1640 | * @brief Get ADC regular group conversion result. |
||
1641 | * @note Reading register DR automatically clears ADC flag EOC |
||
1642 | * (ADC group regular end of unitary conversion). |
||
1643 | * @note This function does not clear ADC flag EOS |
||
1644 | * (ADC group regular end of sequence conversion). |
||
1645 | * Occurrence of flag EOS rising: |
||
1646 | * - If sequencer is composed of 1 rank, flag EOS is equivalent |
||
1647 | * to flag EOC. |
||
1648 | * - If sequencer is composed of several ranks, during the scan |
||
1649 | * sequence flag EOC only is raised, at the end of the scan sequence |
||
1650 | * both flags EOC and EOS are raised. |
||
1651 | * To clear this flag, either use function: |
||
1652 | * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming |
||
1653 | * model polling: @ref HAL_ADC_PollForConversion() |
||
1654 | * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). |
||
1655 | * @param hadc ADC handle |
||
1656 | * @retval ADC group regular conversion data |
||
1657 | */ |
||
1658 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
||
1659 | { |
||
1660 | /* Check the parameters */ |
||
1661 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1662 | |||
1663 | /* Note: EOC flag is not cleared here by software because automatically */ |
||
1664 | /* cleared by hardware when reading register DR. */ |
||
1665 | |||
1666 | /* Return ADC converted value */ |
||
1667 | return hadc->Instance->DR; |
||
1668 | } |
||
1669 | |||
1670 | /** |
||
1671 | * @brief Handles ADC interrupt request |
||
1672 | * @param hadc ADC handle |
||
1673 | * @retval None |
||
1674 | */ |
||
1675 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
||
1676 | { |
||
1677 | /* Check the parameters */ |
||
1678 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1679 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
||
1680 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
||
1681 | |||
1682 | |||
1683 | /* ========== Check End of Conversion flag for regular group ========== */ |
||
1684 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) |
||
1685 | { |
||
1686 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) |
||
1687 | { |
||
1688 | /* Update state machine on conversion status if not in error state */ |
||
1689 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
||
1690 | { |
||
1691 | /* Set ADC state */ |
||
1692 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
1693 | } |
||
1694 | |||
1695 | /* Determine whether any further conversion upcoming on group regular */ |
||
1696 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
1697 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
||
1698 | /* The test of scan sequence on going is done either with scan */ |
||
1699 | /* sequence disabled or with end of conversion flag set to */ |
||
1700 | /* of end of sequence. */ |
||
1701 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
1702 | (hadc->Init.ContinuousConvMode == DISABLE) && |
||
1703 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
||
1704 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
||
1705 | { |
||
1706 | /* Disable ADC end of single conversion interrupt on group regular */ |
||
1707 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
||
1708 | /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ |
||
1709 | /* by overrun IRQ process below. */ |
||
1710 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
||
1711 | |||
1712 | /* Set ADC state */ |
||
1713 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
||
1714 | |||
1715 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
1716 | { |
||
1717 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
1718 | } |
||
1719 | } |
||
1720 | |||
1721 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
1722 | hadc->ConvCpltCallback(hadc); |
||
1723 | #else |
||
1724 | HAL_ADC_ConvCpltCallback(hadc); |
||
1725 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
1726 | |||
1727 | /* Clear regular group conversion flag */ |
||
1728 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
||
1729 | } |
||
1730 | } |
||
1731 | |||
1732 | /* ========== Check End of Conversion flag for injected group ========== */ |
||
1733 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) |
||
1734 | { |
||
1735 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) |
||
1736 | { |
||
1737 | /* Update state machine on conversion status if not in error state */ |
||
1738 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
||
1739 | { |
||
1740 | /* Set ADC state */ |
||
1741 | SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); |
||
1742 | } |
||
1743 | |||
1744 | /* Determine whether any further conversion upcoming on group injected */ |
||
1745 | /* by external trigger, scan sequence on going or by automatic injected */ |
||
1746 | /* conversion from group regular (same conditions as group regular */ |
||
1747 | /* interruption disabling above). */ |
||
1748 | if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && |
||
1749 | (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || |
||
1750 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && |
||
1751 | (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && |
||
1752 | (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
1753 | (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) |
||
1754 | { |
||
1755 | /* Disable ADC end of single conversion interrupt on group injected */ |
||
1756 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
||
1757 | |||
1758 | /* Set ADC state */ |
||
1759 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); |
||
1760 | |||
1761 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) |
||
1762 | { |
||
1763 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
1764 | } |
||
1765 | } |
||
1766 | |||
1767 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
1768 | hadc->InjectedConvCpltCallback(hadc); |
||
1769 | #else |
||
1770 | HAL_ADCEx_InjectedConvCpltCallback(hadc); |
||
1771 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
1772 | |||
1773 | /* Clear injected group conversion flag */ |
||
1774 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); |
||
1775 | } |
||
1776 | } |
||
1777 | |||
1778 | /* ========== Check Analog watchdog flags ========== */ |
||
1779 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) |
||
1780 | { |
||
1781 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) |
||
1782 | { |
||
1783 | /* Set ADC state */ |
||
1784 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
||
1785 | |||
1786 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
1787 | hadc->LevelOutOfWindowCallback(hadc); |
||
1788 | #else |
||
1789 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
||
1790 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
1791 | |||
1792 | /* Clear the ADC analog watchdog flag */ |
||
1793 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
||
1794 | } |
||
1795 | } |
||
1796 | |||
1797 | /* ========== Check Overrun flag ========== */ |
||
1798 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) |
||
1799 | { |
||
1800 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR)) |
||
1801 | { |
||
1802 | /* Note: On STM32L1, ADC overrun can be set through other parameters */ |
||
1803 | /* refer to description of parameter "EOCSelection" for more */ |
||
1804 | /* details. */ |
||
1805 | |||
1806 | /* Set ADC error code to overrun */ |
||
1807 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
||
1808 | |||
1809 | /* Clear ADC overrun flag */ |
||
1810 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
||
1811 | |||
1812 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
1813 | hadc->ErrorCallback(hadc); |
||
1814 | #else |
||
1815 | HAL_ADC_ErrorCallback(hadc); |
||
1816 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
1817 | |||
1818 | /* Clear the Overrun flag */ |
||
1819 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
||
1820 | } |
||
1821 | } |
||
1822 | |||
1823 | } |
||
1824 | |||
1825 | /** |
||
1826 | * @brief Conversion complete callback in non blocking mode |
||
1827 | * @param hadc ADC handle |
||
1828 | * @retval None |
||
1829 | */ |
||
1830 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
||
1831 | { |
||
1832 | /* Prevent unused argument(s) compilation warning */ |
||
1833 | UNUSED(hadc); |
||
1834 | |||
1835 | /* NOTE : This function should not be modified. When the callback is needed, |
||
1836 | function HAL_ADC_ConvCpltCallback must be implemented in the user file. |
||
1837 | */ |
||
1838 | } |
||
1839 | |||
1840 | /** |
||
1841 | * @brief Conversion DMA half-transfer callback in non blocking mode |
||
1842 | * @param hadc ADC handle |
||
1843 | * @retval None |
||
1844 | */ |
||
1845 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
||
1846 | { |
||
1847 | /* Prevent unused argument(s) compilation warning */ |
||
1848 | UNUSED(hadc); |
||
1849 | |||
1850 | /* NOTE : This function should not be modified. When the callback is needed, |
||
1851 | function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. |
||
1852 | */ |
||
1853 | } |
||
1854 | |||
1855 | /** |
||
1856 | * @brief Analog watchdog callback in non blocking mode. |
||
1857 | * @param hadc ADC handle |
||
1858 | * @retval None |
||
1859 | */ |
||
1860 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
||
1861 | { |
||
1862 | /* Prevent unused argument(s) compilation warning */ |
||
1863 | UNUSED(hadc); |
||
1864 | |||
1865 | /* NOTE : This function should not be modified. When the callback is needed, |
||
1866 | function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. |
||
1867 | */ |
||
1868 | } |
||
1869 | |||
1870 | /** |
||
1871 | * @brief ADC error callback in non blocking mode |
||
1872 | * (ADC conversion with interruption or transfer by DMA) |
||
1873 | * @note In case of error due to overrun when using ADC with DMA transfer |
||
1874 | * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): |
||
1875 | * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". |
||
1876 | * - If needed, restart a new ADC conversion using function |
||
1877 | * "HAL_ADC_Start_DMA()" |
||
1878 | * (this function is also clearing overrun flag) |
||
1879 | * @param hadc ADC handle |
||
1880 | * @retval None |
||
1881 | */ |
||
1882 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
||
1883 | { |
||
1884 | /* Prevent unused argument(s) compilation warning */ |
||
1885 | UNUSED(hadc); |
||
1886 | |||
1887 | /* NOTE : This function should not be modified. When the callback is needed, |
||
1888 | function HAL_ADC_ErrorCallback must be implemented in the user file. |
||
1889 | */ |
||
1890 | } |
||
1891 | |||
1892 | |||
1893 | /** |
||
1894 | * @} |
||
1895 | */ |
||
1896 | |||
1897 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
||
1898 | * @brief Peripheral Control functions |
||
1899 | * |
||
1900 | @verbatim |
||
1901 | =============================================================================== |
||
1902 | ##### Peripheral Control functions ##### |
||
1903 | =============================================================================== |
||
1904 | [..] This section provides functions allowing to: |
||
1905 | (+) Configure channels on regular group |
||
1906 | (+) Configure the analog watchdog |
||
1907 | |||
1908 | @endverbatim |
||
1909 | * @{ |
||
1910 | */ |
||
1911 | |||
1912 | /** |
||
1913 | * @brief Configures the the selected channel to be linked to the regular |
||
1914 | * group. |
||
1915 | * @note In case of usage of internal measurement channels: |
||
1916 | * Vbat/VrefInt/TempSensor. |
||
1917 | * These internal paths can be be disabled using function |
||
1918 | * HAL_ADC_DeInit(). |
||
1919 | * @note Possibility to update parameters on the fly: |
||
1920 | * This function initializes channel into regular group, following |
||
1921 | * calls to this function can be used to reconfigure some parameters |
||
1922 | * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting |
||
1923 | * the ADC. |
||
1924 | * The setting of these parameters is conditioned to ADC state. |
||
1925 | * For parameters constraints, see comments of structure |
||
1926 | * "ADC_ChannelConfTypeDef". |
||
1927 | * @param hadc ADC handle |
||
1928 | * @param sConfig Structure of ADC channel for regular group. |
||
1929 | * @retval HAL status |
||
1930 | */ |
||
1931 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
||
1932 | { |
||
1933 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1934 | __IO uint32_t wait_loop_index = 0; |
||
1935 | |||
1936 | /* Check the parameters */ |
||
1937 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1938 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
||
1939 | assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); |
||
1940 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
||
1941 | |||
1942 | /* Process locked */ |
||
1943 | __HAL_LOCK(hadc); |
||
1944 | |||
1945 | |||
1946 | /* Regular sequence configuration */ |
||
1947 | /* For Rank 1 to 6 */ |
||
1948 | if (sConfig->Rank < 7) |
||
1949 | { |
||
1950 | MODIFY_REG(hadc->Instance->SQR5, |
||
1951 | ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank), |
||
1952 | ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) ); |
||
1953 | } |
||
1954 | /* For Rank 7 to 12 */ |
||
1955 | else if (sConfig->Rank < 13) |
||
1956 | { |
||
1957 | MODIFY_REG(hadc->Instance->SQR4, |
||
1958 | ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank), |
||
1959 | ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) ); |
||
1960 | } |
||
1961 | /* For Rank 13 to 18 */ |
||
1962 | else if (sConfig->Rank < 19) |
||
1963 | { |
||
1964 | MODIFY_REG(hadc->Instance->SQR3, |
||
1965 | ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank), |
||
1966 | ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); |
||
1967 | } |
||
1968 | /* For Rank 19 to 24 */ |
||
1969 | else if (sConfig->Rank < 25) |
||
1970 | { |
||
1971 | MODIFY_REG(hadc->Instance->SQR2, |
||
1972 | ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank), |
||
1973 | ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); |
||
1974 | } |
||
1975 | /* For Rank 25 to 28 */ |
||
1976 | else |
||
1977 | { |
||
1978 | MODIFY_REG(hadc->Instance->SQR1, |
||
1979 | ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank), |
||
1980 | ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); |
||
1981 | } |
||
1982 | |||
1983 | |||
1984 | /* Channel sampling time configuration */ |
||
1985 | /* For channels 0 to 9 */ |
||
1986 | if (sConfig->Channel < ADC_CHANNEL_10) |
||
1987 | { |
||
1988 | MODIFY_REG(hadc->Instance->SMPR3, |
||
1989 | ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel), |
||
1990 | ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) ); |
||
1991 | } |
||
1992 | /* For channels 10 to 19 */ |
||
1993 | else if (sConfig->Channel < ADC_CHANNEL_20) |
||
1994 | { |
||
1995 | MODIFY_REG(hadc->Instance->SMPR2, |
||
1996 | ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel), |
||
1997 | ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); |
||
1998 | } |
||
1999 | /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ |
||
2000 | /* For channels 20 to 29 for devices Cat4, Cat.5 */ |
||
2001 | else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX) |
||
2002 | { |
||
2003 | MODIFY_REG(hadc->Instance->SMPR1, |
||
2004 | ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel), |
||
2005 | ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); |
||
2006 | } |
||
2007 | /* For channels 30 to 31 for devices Cat4, Cat.5 */ |
||
2008 | else |
||
2009 | { |
||
2010 | ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel); |
||
2011 | } |
||
2012 | |||
2013 | /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ |
||
2014 | /* and VREFINT measurement path. */ |
||
2015 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || |
||
2016 | (sConfig->Channel == ADC_CHANNEL_VREFINT) ) |
||
2017 | { |
||
2018 | if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET) |
||
2019 | { |
||
2020 | SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); |
||
2021 | |||
2022 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) |
||
2023 | { |
||
2024 | /* Delay for temperature sensor stabilization time */ |
||
2025 | /* Compute number of CPU cycles to wait for */ |
||
2026 | wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); |
||
2027 | while(wait_loop_index != 0) |
||
2028 | { |
||
2029 | wait_loop_index--; |
||
2030 | } |
||
2031 | } |
||
2032 | } |
||
2033 | } |
||
2034 | |||
2035 | /* Process unlocked */ |
||
2036 | __HAL_UNLOCK(hadc); |
||
2037 | |||
2038 | /* Return function status */ |
||
2039 | return tmp_hal_status; |
||
2040 | } |
||
2041 | |||
2042 | /** |
||
2043 | * @brief Configures the analog watchdog. |
||
2044 | * @note Analog watchdog thresholds can be modified while ADC conversion |
||
2045 | * is on going. |
||
2046 | * In this case, some constraints must be taken into account: |
||
2047 | * the programmed threshold values are effective from the next |
||
2048 | * ADC EOC (end of unitary conversion). |
||
2049 | * Considering that registers write delay may happen due to |
||
2050 | * bus activity, this might cause an uncertainty on the |
||
2051 | * effective timing of the new programmed threshold values. |
||
2052 | * @param hadc ADC handle |
||
2053 | * @param AnalogWDGConfig Structure of ADC analog watchdog configuration |
||
2054 | * @retval HAL status |
||
2055 | */ |
||
2056 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
||
2057 | { |
||
2058 | /* Check the parameters */ |
||
2059 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
2060 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
||
2061 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
||
2062 | assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); |
||
2063 | assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); |
||
2064 | |||
2065 | if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || |
||
2066 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || |
||
2067 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) |
||
2068 | { |
||
2069 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
||
2070 | } |
||
2071 | |||
2072 | /* Process locked */ |
||
2073 | __HAL_LOCK(hadc); |
||
2074 | |||
2075 | /* Analog watchdog configuration */ |
||
2076 | |||
2077 | /* Configure ADC Analog watchdog interrupt */ |
||
2078 | if(AnalogWDGConfig->ITMode == ENABLE) |
||
2079 | { |
||
2080 | /* Enable the ADC Analog watchdog interrupt */ |
||
2081 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
||
2082 | } |
||
2083 | else |
||
2084 | { |
||
2085 | /* Disable the ADC Analog watchdog interrupt */ |
||
2086 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
||
2087 | } |
||
2088 | |||
2089 | /* Configuration of analog watchdog: */ |
||
2090 | /* - Set the analog watchdog enable mode: regular and/or injected groups, */ |
||
2091 | /* one or all channels. */ |
||
2092 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
||
2093 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
||
2094 | hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL | |
||
2095 | ADC_CR1_JAWDEN | |
||
2096 | ADC_CR1_AWDEN | |
||
2097 | ADC_CR1_AWDCH ); |
||
2098 | |||
2099 | hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode | |
||
2100 | AnalogWDGConfig->Channel ); |
||
2101 | |||
2102 | /* Set the high threshold */ |
||
2103 | hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; |
||
2104 | |||
2105 | /* Set the low threshold */ |
||
2106 | hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; |
||
2107 | |||
2108 | /* Process unlocked */ |
||
2109 | __HAL_UNLOCK(hadc); |
||
2110 | |||
2111 | /* Return function status */ |
||
2112 | return HAL_OK; |
||
2113 | } |
||
2114 | |||
2115 | |||
2116 | /** |
||
2117 | * @} |
||
2118 | */ |
||
2119 | |||
2120 | |||
2121 | /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions |
||
2122 | * @brief Peripheral State functions |
||
2123 | * |
||
2124 | @verbatim |
||
2125 | =============================================================================== |
||
2126 | ##### Peripheral State and Errors functions ##### |
||
2127 | =============================================================================== |
||
2128 | [..] |
||
2129 | This subsection provides functions to get in run-time the status of the |
||
2130 | peripheral. |
||
2131 | (+) Check the ADC state |
||
2132 | (+) Check the ADC error code |
||
2133 | |||
2134 | @endverbatim |
||
2135 | * @{ |
||
2136 | */ |
||
2137 | |||
2138 | /** |
||
2139 | * @brief return the ADC state |
||
2140 | * @param hadc ADC handle |
||
2141 | * @retval HAL state |
||
2142 | */ |
||
2143 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
||
2144 | { |
||
2145 | /* Return ADC state */ |
||
2146 | return hadc->State; |
||
2147 | } |
||
2148 | |||
2149 | /** |
||
2150 | * @brief Return the ADC error code |
||
2151 | * @param hadc ADC handle |
||
2152 | * @retval ADC Error Code |
||
2153 | */ |
||
2154 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
||
2155 | { |
||
2156 | return hadc->ErrorCode; |
||
2157 | } |
||
2158 | |||
2159 | /** |
||
2160 | * @} |
||
2161 | */ |
||
2162 | |||
2163 | /** |
||
2164 | * @} |
||
2165 | */ |
||
2166 | |||
2167 | /** @defgroup ADC_Private_Functions ADC Private Functions |
||
2168 | * @{ |
||
2169 | */ |
||
2170 | |||
2171 | /** |
||
2172 | * @brief Enable the selected ADC. |
||
2173 | * @note Prerequisite condition to use this function: ADC must be disabled |
||
2174 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
||
2175 | * @note If low power mode AutoPowerOff is enabled, power-on/off phases are |
||
2176 | * performed automatically by hardware. |
||
2177 | * In this mode, this function is useless and must not be called because |
||
2178 | * flag ADC_FLAG_RDY is not usable. |
||
2179 | * Therefore, this function must be called under condition of |
||
2180 | * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". |
||
2181 | * @param hadc ADC handle |
||
2182 | * @retval HAL status. |
||
2183 | */ |
||
2184 | HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
||
2185 | { |
||
2186 | uint32_t tickstart = 0; |
||
2187 | __IO uint32_t wait_loop_index = 0; |
||
2188 | |||
2189 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
||
2190 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
||
2191 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
||
2192 | /* causes: ADC clock not running, ...). */ |
||
2193 | if (ADC_IS_ENABLE(hadc) == RESET) |
||
2194 | { |
||
2195 | /* Enable the Peripheral */ |
||
2196 | __HAL_ADC_ENABLE(hadc); |
||
2197 | |||
2198 | /* Delay for ADC stabilization time */ |
||
2199 | /* Compute number of CPU cycles to wait for */ |
||
2200 | wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); |
||
2201 | while(wait_loop_index != 0) |
||
2202 | { |
||
2203 | wait_loop_index--; |
||
2204 | } |
||
2205 | |||
2206 | /* Get tick count */ |
||
2207 | tickstart = HAL_GetTick(); |
||
2208 | |||
2209 | /* Wait for ADC effectively enabled */ |
||
2210 | while(ADC_IS_ENABLE(hadc) == RESET) |
||
2211 | { |
||
2212 | if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT) |
||
2213 | { |
||
2214 | /* Update ADC state machine to error */ |
||
2215 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
2216 | |||
2217 | /* Set ADC error code to ADC IP internal error */ |
||
2218 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
2219 | |||
2220 | /* Process unlocked */ |
||
2221 | __HAL_UNLOCK(hadc); |
||
2222 | |||
2223 | return HAL_ERROR; |
||
2224 | } |
||
2225 | } |
||
2226 | } |
||
2227 | |||
2228 | /* Return HAL status */ |
||
2229 | return HAL_OK; |
||
2230 | } |
||
2231 | |||
2232 | /** |
||
2233 | * @brief Stop ADC conversion and disable the selected ADC |
||
2234 | * @note Prerequisite condition to use this function: ADC conversions must be |
||
2235 | * stopped to disable the ADC. |
||
2236 | * @param hadc ADC handle |
||
2237 | * @retval HAL status. |
||
2238 | */ |
||
2239 | HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) |
||
2240 | { |
||
2241 | uint32_t tickstart = 0; |
||
2242 | |||
2243 | /* Verification if ADC is not already disabled */ |
||
2244 | if (ADC_IS_ENABLE(hadc) != RESET) |
||
2245 | { |
||
2246 | /* Disable the ADC peripheral */ |
||
2247 | __HAL_ADC_DISABLE(hadc); |
||
2248 | |||
2249 | /* Get tick count */ |
||
2250 | tickstart = HAL_GetTick(); |
||
2251 | |||
2252 | /* Wait for ADC effectively disabled */ |
||
2253 | while(ADC_IS_ENABLE(hadc) != RESET) |
||
2254 | { |
||
2255 | if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT) |
||
2256 | { |
||
2257 | /* Update ADC state machine to error */ |
||
2258 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
2259 | |||
2260 | /* Set ADC error code to ADC IP internal error */ |
||
2261 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
2262 | |||
2263 | return HAL_ERROR; |
||
2264 | } |
||
2265 | } |
||
2266 | } |
||
2267 | |||
2268 | /* Return HAL status */ |
||
2269 | return HAL_OK; |
||
2270 | } |
||
2271 | |||
2272 | /** |
||
2273 | * @brief DMA transfer complete callback. |
||
2274 | * @param hdma pointer to DMA handle. |
||
2275 | * @retval None |
||
2276 | */ |
||
2277 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
||
2278 | { |
||
2279 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
2280 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
2281 | |||
2282 | /* Update state machine on conversion status if not in error state */ |
||
2283 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
||
2284 | { |
||
2285 | /* Update ADC state machine */ |
||
2286 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
2287 | |||
2288 | /* Determine whether any further conversion upcoming on group regular */ |
||
2289 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
2290 | /* Note: On STM32L1, there is no independent flag of end of sequence. */ |
||
2291 | /* The test of scan sequence on going is done either with scan */ |
||
2292 | /* sequence disabled or with end of conversion flag set to */ |
||
2293 | /* of end of sequence. */ |
||
2294 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
2295 | (hadc->Init.ContinuousConvMode == DISABLE) && |
||
2296 | (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || |
||
2297 | HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) |
||
2298 | { |
||
2299 | /* Disable ADC end of single conversion interrupt on group regular */ |
||
2300 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
||
2301 | /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ |
||
2302 | /* by overrun IRQ process below. */ |
||
2303 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
||
2304 | |||
2305 | /* Set ADC state */ |
||
2306 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
||
2307 | |||
2308 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
||
2309 | { |
||
2310 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
||
2311 | } |
||
2312 | } |
||
2313 | |||
2314 | /* Conversion complete callback */ |
||
2315 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
2316 | hadc->ConvCpltCallback(hadc); |
||
2317 | #else |
||
2318 | HAL_ADC_ConvCpltCallback(hadc); |
||
2319 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
2320 | } |
||
2321 | else |
||
2322 | { |
||
2323 | /* Call DMA error callback */ |
||
2324 | hadc->DMA_Handle->XferErrorCallback(hdma); |
||
2325 | } |
||
2326 | } |
||
2327 | |||
2328 | /** |
||
2329 | * @brief DMA half transfer complete callback. |
||
2330 | * @param hdma pointer to DMA handle. |
||
2331 | * @retval None |
||
2332 | */ |
||
2333 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
||
2334 | { |
||
2335 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
2336 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
2337 | |||
2338 | /* Half conversion callback */ |
||
2339 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
2340 | hadc->ConvHalfCpltCallback(hadc); |
||
2341 | #else |
||
2342 | HAL_ADC_ConvHalfCpltCallback(hadc); |
||
2343 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
2344 | } |
||
2345 | |||
2346 | /** |
||
2347 | * @brief DMA error callback |
||
2348 | * @param hdma pointer to DMA handle. |
||
2349 | * @retval None |
||
2350 | */ |
||
2351 | static void ADC_DMAError(DMA_HandleTypeDef *hdma) |
||
2352 | { |
||
2353 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
2354 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
2355 | |||
2356 | /* Set ADC state */ |
||
2357 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
||
2358 | |||
2359 | /* Set ADC error code to DMA error */ |
||
2360 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); |
||
2361 | |||
2362 | /* Error callback */ |
||
2363 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
2364 | hadc->ErrorCallback(hadc); |
||
2365 | #else |
||
2366 | HAL_ADC_ErrorCallback(hadc); |
||
2367 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
2368 | } |
||
2369 | |||
2370 | /** |
||
2371 | * @} |
||
2372 | */ |
||
2373 | |||
2374 | #endif /* HAL_ADC_MODULE_ENABLED */ |
||
2375 | /** |
||
2376 | * @} |
||
2377 | */ |
||
2378 | |||
2379 | /** |
||
2380 | * @} |
||
2381 | */ |
||
2382 | |||
2383 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |