WebSVN – DashDisplay – Blame – /branches/Dashboard_L152_210623/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h

Rev	Author	Line No.	Line
56	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32l1xx_ll_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef __STM32L1xx_LL_TIM_H
		22	#define __STM32L1xx_LL_TIM_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32l1xx.h"
		30
		31	/** @addtogroup STM32L1xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM6) \|\| defined (TIM7)
		36
		37	/** @defgroup TIM_LL TIM
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
		44	* @{
		45	*/
		46	static const uint8_t OFFSET_TAB_CCMRx[] =
		47	{
		48	0x00U, /* 0: TIMx_CH1 */
		49	0x00U, /* 1: NA */
		50	0x00U, /* 2: TIMx_CH2 */
		51	0x00U, /* 3: NA */
		52	0x04U, /* 4: TIMx_CH3 */
		53	0x00U, /* 5: NA */
		54	0x04U /* 6: TIMx_CH4 */
		55	};
		56
		57	static const uint8_t SHIFT_TAB_OCxx[] =
		58	{
		59	0U, /* 0: OC1M, OC1FE, OC1PE */
		60	0U, /* 1: - NA */
		61	8U, /* 2: OC2M, OC2FE, OC2PE */
		62	0U, /* 3: - NA */
		63	0U, /* 4: OC3M, OC3FE, OC3PE */
		64	0U, /* 5: - NA */
		65	8U /* 6: OC4M, OC4FE, OC4PE */
		66	};
		67
		68	static const uint8_t SHIFT_TAB_ICxx[] =
		69	{
		70	0U, /* 0: CC1S, IC1PSC, IC1F */
		71	0U, /* 1: - NA */
		72	8U, /* 2: CC2S, IC2PSC, IC2F */
		73	0U, /* 3: - NA */
		74	0U, /* 4: CC3S, IC3PSC, IC3F */
		75	0U, /* 5: - NA */
		76	8U /* 6: CC4S, IC4PSC, IC4F */
		77	};
		78
		79	static const uint8_t SHIFT_TAB_CCxP[] =
		80	{
		81	0U, /* 0: CC1P */
		82	0U, /* 1: NA */
		83	4U, /* 2: CC2P */
		84	0U, /* 3: NA */
		85	8U, /* 4: CC3P */
		86	0U, /* 5: NA */
		87	12U /* 6: CC4P */
		88	};
		89
		90	/**
		91	* @}
		92	*/
		93
		94	/* Private constants ---------------------------------------------------------*/
		95	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
		96	* @{
		97	*/
		98
		99
		100	#define TIMx_OR_RMP_SHIFT 16U
		101	#define TIMx_OR_RMP_MASK 0x0000FFFFU
		102	#define TIM_OR_RMP_MASK ((TIM_OR_TI1RMP \| TIM_OR_ETR_RMP \| TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT)
		103	#define TIM9_OR_RMP_MASK ((TIM_OR_TI1RMP \| TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
		104	#define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
		105	#define TIM3_OR_RMP_MASK (TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT)
		106
		107
		108
		109	/**
		110	* @}
		111	*/
		112
		113	/* Private macros ------------------------------------------------------------*/
		114	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
		115	* @{
		116	*/
		117	/** @brief Convert channel id into channel index.
		118	* @param __CHANNEL__ This parameter can be one of the following values:
		119	* @arg @ref LL_TIM_CHANNEL_CH1
		120	* @arg @ref LL_TIM_CHANNEL_CH2
		121	* @arg @ref LL_TIM_CHANNEL_CH3
		122	* @arg @ref LL_TIM_CHANNEL_CH4
		123	* @retval none
		124	*/
		125	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
		126	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
		127	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
		128	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
		129
		130	/**
		131	* @}
		132	*/
		133
		134
		135	/* Exported types ------------------------------------------------------------*/
		136	#if defined(USE_FULL_LL_DRIVER)
		137	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
		138	* @{
		139	*/
		140
		141	/**
		142	* @brief TIM Time Base configuration structure definition.
		143	*/
		144	typedef struct
		145	{
		146	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		147	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		148
61	mjames	149	This feature can be modified afterwards using unitary function
		150	@ref LL_TIM_SetPrescaler().*/
56	mjames	151
		152	uint32_t CounterMode; /*!< Specifies the counter mode.
		153	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
		154
61	mjames	155	This feature can be modified afterwards using unitary function
		156	@ref LL_TIM_SetCounterMode().*/
56	mjames	157
		158	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
		159	Auto-Reload Register at the next update event.
		160	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
61	mjames	161	Some timer instances may support 32 bits counters. In that case this parameter must
		162	be a number between 0x0000 and 0xFFFFFFFF.
56	mjames	163
61	mjames	164	This feature can be modified afterwards using unitary function
		165	@ref LL_TIM_SetAutoReload().*/
56	mjames	166
		167	uint32_t ClockDivision; /*!< Specifies the clock division.
		168	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
		169
61	mjames	170	This feature can be modified afterwards using unitary function
		171	@ref LL_TIM_SetClockDivision().*/
56	mjames	172	} LL_TIM_InitTypeDef;
		173
		174	/**
		175	* @brief TIM Output Compare configuration structure definition.
		176	*/
		177	typedef struct
		178	{
		179	uint32_t OCMode; /*!< Specifies the output mode.
		180	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
		181
61	mjames	182	This feature can be modified afterwards using unitary function
		183	@ref LL_TIM_OC_SetMode().*/
56	mjames	184
		185	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
		186	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		187
61	mjames	188	This feature can be modified afterwards using unitary functions
		189	@ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
56	mjames	190
		191	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
		192	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		193
61	mjames	194	This feature can be modified afterwards using unitary function
		195	LL_TIM_OC_SetCompareCHx (x=1..6).*/
56	mjames	196
		197	uint32_t OCPolarity; /*!< Specifies the output polarity.
		198	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		199
61	mjames	200	This feature can be modified afterwards using unitary function
		201	@ref LL_TIM_OC_SetPolarity().*/
56	mjames	202
		203
		204	} LL_TIM_OC_InitTypeDef;
		205
		206	/**
		207	* @brief TIM Input Capture configuration structure definition.
		208	*/
		209
		210	typedef struct
		211	{
		212
		213	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		214	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		215
61	mjames	216	This feature can be modified afterwards using unitary function
		217	@ref LL_TIM_IC_SetPolarity().*/
56	mjames	218
		219	uint32_t ICActiveInput; /*!< Specifies the input.
		220	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		221
61	mjames	222	This feature can be modified afterwards using unitary function
		223	@ref LL_TIM_IC_SetActiveInput().*/
56	mjames	224
		225	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		226	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		227
61	mjames	228	This feature can be modified afterwards using unitary function
		229	@ref LL_TIM_IC_SetPrescaler().*/
56	mjames	230
		231	uint32_t ICFilter; /*!< Specifies the input capture filter.
		232	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		233
61	mjames	234	This feature can be modified afterwards using unitary function
		235	@ref LL_TIM_IC_SetFilter().*/
56	mjames	236	} LL_TIM_IC_InitTypeDef;
		237
		238
		239	/**
		240	* @brief TIM Encoder interface configuration structure definition.
		241	*/
		242	typedef struct
		243	{
		244	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
		245	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
		246
61	mjames	247	This feature can be modified afterwards using unitary function
		248	@ref LL_TIM_SetEncoderMode().*/
56	mjames	249
		250	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		251	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		252
61	mjames	253	This feature can be modified afterwards using unitary function
		254	@ref LL_TIM_IC_SetPolarity().*/
56	mjames	255
		256	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
		257	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		258
61	mjames	259	This feature can be modified afterwards using unitary function
		260	@ref LL_TIM_IC_SetActiveInput().*/
56	mjames	261
		262	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		263	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		264
61	mjames	265	This feature can be modified afterwards using unitary function
		266	@ref LL_TIM_IC_SetPrescaler().*/
56	mjames	267
		268	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		269	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		270
61	mjames	271	This feature can be modified afterwards using unitary function
		272	@ref LL_TIM_IC_SetFilter().*/
56	mjames	273
		274	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
		275	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		276
61	mjames	277	This feature can be modified afterwards using unitary function
		278	@ref LL_TIM_IC_SetPolarity().*/
56	mjames	279
		280	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
		281	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		282
61	mjames	283	This feature can be modified afterwards using unitary function
		284	@ref LL_TIM_IC_SetActiveInput().*/
56	mjames	285
		286	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
		287	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		288
61	mjames	289	This feature can be modified afterwards using unitary function
		290	@ref LL_TIM_IC_SetPrescaler().*/
56	mjames	291
		292	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
		293	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		294
61	mjames	295	This feature can be modified afterwards using unitary function
		296	@ref LL_TIM_IC_SetFilter().*/
56	mjames	297
		298	} LL_TIM_ENCODER_InitTypeDef;
		299
		300
		301	/**
		302	* @}
		303	*/
		304	#endif /* USE_FULL_LL_DRIVER */
		305
		306	/* Exported constants --------------------------------------------------------*/
		307	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
		308	* @{
		309	*/
		310
		311	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
		312	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
		313	* @{
		314	*/
		315	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
		316	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
		317	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
		318	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
		319	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
		320	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
		321	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
		322	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
		323	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
		324	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
		325	/**
		326	* @}
		327	*/
		328
		329	/** @defgroup TIM_LL_EC_IT IT Defines
		330	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
		331	* @{
		332	*/
		333	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
		334	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
		335	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
		336	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
		337	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
		338	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
		339	/**
		340	* @}
		341	*/
		342
		343	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
		344	* @{
		345	*/
		346	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
		347	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
		348	/**
		349	* @}
		350	*/
		351
		352	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
		353	* @{
		354	*/
61	mjames	355	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter stops counting at the next update event /
		356	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter is not stopped at update event /
56	mjames	357	/**
		358	* @}
		359	*/
		360
		361	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
		362	* @{
		363	*/
		364	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
		365	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
		366	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
		367	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
		368	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
		369	/**
		370	* @}
		371	*/
		372
		373	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
		374	* @{
		375	*/
		376	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
		377	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
		378	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
		379	/**
		380	* @}
		381	*/
		382
		383	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
		384	* @{
		385	*/
		386	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
		387	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
		388	/**
		389	* @}
		390	*/
		391
		392
		393	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
		394	* @{
		395	*/
		396	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
		397	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
		398	/**
		399	* @}
		400	*/
		401
		402
		403	/** @defgroup TIM_LL_EC_CHANNEL Channel
		404	* @{
		405	*/
		406	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
		407	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
		408	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
		409	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
		410	/**
		411	* @}
		412	*/
		413
		414	#if defined(USE_FULL_LL_DRIVER)
		415	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
		416	* @{
		417	*/
		418	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
		419	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
		420	/**
		421	* @}
		422	*/
		423	#endif /* USE_FULL_LL_DRIVER */
		424
		425	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
		426	* @{
		427	*/
		428	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
		429	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
		430	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
		431	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
		432	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
		433	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
		434	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
		435	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
		436	/**
		437	* @}
		438	*/
		439
		440	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
		441	* @{
		442	*/
		443	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
		444	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
		445	/**
		446	* @}
		447	*/
		448
		449
		450
		451	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
		452	* @{
		453	*/
		454	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
		455	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
		456	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
		457	/**
		458	* @}
		459	*/
		460
		461	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
		462	* @{
		463	*/
		464	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
		465	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
		466	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
		467	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
		468	/**
		469	* @}
		470	*/
		471
		472	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
		473	* @{
		474	*/
		475	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		476	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
		477	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
		478	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
		479	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
		480	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
		481	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
		482	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
		483	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
		484	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
		485	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
		486	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
		487	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
		488	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
		489	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
		490	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
		491	/**
		492	* @}
		493	*/
		494
		495	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
		496	* @{
		497	*/
		498	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
		499	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
		500	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
		501	/**
		502	* @}
		503	*/
		504
		505	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
		506	* @{
		507	*/
		508	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
		509	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
		510	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
		511	/**
		512	* @}
		513	*/
		514
		515	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
		516	* @{
		517	*/
		518	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
		519	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
		520	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
		521	/**
		522	* @}
		523	*/
		524
		525	/** @defgroup TIM_LL_EC_TRGO Trigger Output
		526	* @{
		527	*/
		528	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
		529	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
		530	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
		531	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
		532	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
		533	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
		534	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
		535	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
		536	/**
		537	* @}
		538	*/
		539
		540
		541	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
		542	* @{
		543	*/
		544	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
		545	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
		546	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
		547	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
		548	/**
		549	* @}
		550	*/
		551
		552	/** @defgroup TIM_LL_EC_TS Trigger Selection
		553	* @{
		554	*/
		555	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
		556	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
		557	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
		558	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
		559	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
		560	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
		561	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
		562	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
		563	/**
		564	* @}
		565	*/
		566
		567	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
		568	* @{
		569	*/
		570	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
		571	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
		572	/**
		573	* @}
		574	*/
		575
		576	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
		577	* @{
		578	*/
		579	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
		580	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
		581	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
		582	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
		583	/**
		584	* @}
		585	*/
		586
		587	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
		588	* @{
		589	*/
		590	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		591	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
		592	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
		593	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
		594	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
		595	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
		596	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
		597	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
		598	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
		599	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
		600	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
		601	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
		602	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
		603	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
		604	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
		605	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
		606	/**
		607	* @}
		608	*/
		609
		610
		611
		612
		613
		614
		615
		616	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
		617	* @{
		618	*/
		619	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
		620	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
		621	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
		622	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
		623	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
		624	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
		625	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
		626	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
		627	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
		628	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
		629	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
		630	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
		631	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
		632	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
		633	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
		634	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
		635	#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_OR register is the DMA base address for DMA burst /
		636	/**
		637	* @}
		638	*/
		639
		640	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
		641	* @{
		642	*/
		643	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
		644	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
		645	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
		646	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
		647	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
		648	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
		649	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
		650	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
		651	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
		652	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
		653	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
		654	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
		655	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
		656	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
		657	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
		658	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
		659	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
		660	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
		661	/**
		662	* @}
		663	*/
		664
		665	/** @defgroup TIM_LL_EC_TIM10_TI1_RMP TIM10 input 1 remapping capability
		666	* @{
		667	*/
		668	#define LL_TIM_TIM10_TI1_RMP_GPIO TIM_OR_RMP_MASK /!< TIM10 channel1 is connected to GPIO /
		669	#define LL_TIM_TIM10_TI1_RMP_LSI (TIM_OR_TI1RMP_0 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to LSI internal clock /
		670	#define LL_TIM_TIM10_TI1_RMP_LSE (TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to LSE internal clock /
		671	#define LL_TIM_TIM10_TI1_RMP_RTC (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to RTC wakeup interrupt signal /
		672	/**
		673	* @}
		674	*/
		675
		676	/** @defgroup TIM_LL_EC_TIM10_ETR_RMP TIM10 ETR remap
		677	* @{
		678	*/
		679	#define LL_TIM_TIM10_ETR_RMP_LSE TIM_OR_RMP_MASK /!< TIM10 ETR input is connected to LSE /
		680	#define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP \| TIM_OR_RMP_MASK) /!< TIM10 ETR input is connected to TIM9 TGO /
		681	/**
		682	* @}
		683	*/
		684
		685	/** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI)
		686	* @{
		687	*/
		688	#define LL_TIM_TIM10_TI1_RMP TIM_OR_RMP_MASK /!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values /
		689	#define LL_TIM_TIM10_TI1_RMP_RI (TIM_OR_TI1_RMP_RI \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to RI /
		690	/**
		691	* @}
		692	*/
		693
		694	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 input 1 remapping capability
		695	* @{
		696	*/
		697	#define LL_TIM_TIM11_TI1_RMP_GPIO TIM_OR_RMP_MASK /!< TIM11 channel1 is connected to GPIO /
		698	#define LL_TIM_TIM11_TI1_RMP_MSI (TIM_OR_TI1RMP_0 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to MSI internal clock /
		699	#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to HSE RTC clock /
		700	#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to GPIO /
		701	/**
		702	* @}
		703	*/
		704
		705	/** @defgroup TIM_LL_EC_TIM11_ETR_RMP TIM11 ETR remap
		706	* @{
		707	*/
		708	#define LL_TIM_TIM11_ETR_RMP_LSE TIM_OR_RMP_MASK /!< TIM11 ETR input is connected to LSE /
		709	#define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP \| TIM_OR_RMP_MASK) /!< TIM11 ETR input is connected to TIM9 TGO clock /
		710	/**
		711	* @}
		712	*/
		713
		714	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI)
		715	* @{
		716	*/
		717	#define LL_TIM_TIM11_TI1_RMP TIM_OR_RMP_MASK /!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values /
		718	#define LL_TIM_TIM11_TI1_RMP_RI (TIM_OR_TI1_RMP_RI \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to RI /
		719	/**
		720	* @}
		721	*/
		722
		723	/** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap
		724	* @{
		725	*/
		726	#define LL_TIM_TIM9_TI1_RMP_GPIO TIM9_OR_RMP_MASK /!< TIM9 channel1 is connected to GPIO /
		727	#define LL_TIM_TIM9_TI1_RMP_LSE (TIM_OR_TI1RMP_0 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to LSE internal clock /
		728	#define LL_TIM_TIM9_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_1 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to GPIO /
		729	#define LL_TIM_TIM9_TI1_RMP_GPIO2 (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to GPIO /
		730	/**
		731	* @}
		732	*/
		733
		734	/** @defgroup TIM_LL_EC_TIM9_ITR1_RMP TIM9 ITR1 remap
		735	* @{
		736	*/
		737	#define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO TIM9_OR_RMP_MASK /!< TIM9 channel1 is connected to TIM3 TGO signal /
		738	#define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (TIM9_OR_ITR1_RMP \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to touch sensing I/O /
		739	/**
		740	* @}
		741	*/
		742
		743	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 internal trigger 1 remap
		744	* @{
		745	*/
		746	#define LL_TIM_TIM2_TIR1_RMP_TIM10_OC TIM9_OR_RMP_MASK /!< TIM2 ITR1 input is connected to TIM10 OC/
		747	#define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (TIM2_OR_ITR1_RMP \| TIM9_OR_RMP_MASK) /!< TIM2 ITR1 input is connected to TIM5 TGO /
		748	/**
		749	* @}
		750	*/
		751
		752	/** @defgroup TIM_LL_EC_TIM3_ITR2_RMP TIM3 internal trigger 2 remap
		753	* @{
		754	*/
		755	#define LL_TIM_TIM3_TIR2_RMP_TIM11_OC TIM9_OR_RMP_MASK /!< TIM3 ITR2 input is connected to TIM11 OC /
		756	#define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (TIM3_OR_ITR2_RMP \| TIM9_OR_RMP_MASK) /!< TIM3 ITR2 input is connected to TIM5 TGO /
		757	/**
		758	* @}
		759	*/
		760
		761
		762	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
		763	* @{
		764	*/
		765	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
		766	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
		767	/**
		768	* @}
		769	*/
		770
		771	/**
		772	* @}
		773	*/
		774
		775	/* Exported macro ------------------------------------------------------------*/
		776	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
		777	* @{
		778	*/
		779
		780	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
		781	* @{
		782	*/
		783	/**
		784	* @brief Write a value in TIM register.
		785	* @param __INSTANCE__ TIM Instance
		786	* @param __REG__ Register to be written
		787	* @param __VALUE__ Value to be written in the register
		788	* @retval None
		789	*/
		790	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
		791
		792	/**
		793	* @brief Read a value in TIM register.
		794	* @param __INSTANCE__ TIM Instance
		795	* @param __REG__ Register to be read
		796	* @retval Register value
		797	*/
		798	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
		799	/**
		800	* @}
		801	*/
		802
		803	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
		804	* @{
		805	*/
		806
		807	/**
		808	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
		809	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
		810	* @param __TIMCLK__ timer input clock frequency (in Hz)
		811	* @param __CNTCLK__ counter clock frequency (in Hz)
		812	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
		813	*/
		814	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
		815	(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
		816
		817	/**
		818	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
		819	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
		820	* @param __TIMCLK__ timer input clock frequency (in Hz)
		821	* @param __PSC__ prescaler
		822	* @param __FREQ__ output signal frequency (in Hz)
		823	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		824	*/
		825	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
		826	((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
		827
		828	/**
61	mjames	829	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare
		830	* active/inactive delay.
56	mjames	831	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
		832	* @param __TIMCLK__ timer input clock frequency (in Hz)
		833	* @param __PSC__ prescaler
		834	* @param __DELAY__ timer output compare active/inactive delay (in us)
		835	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
		836	*/
		837	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
		838	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
		839	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
		840
		841	/**
61	mjames	842	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
		843	* (when the timer operates in one pulse mode).
56	mjames	844	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
		845	* @param __TIMCLK__ timer input clock frequency (in Hz)
		846	* @param __PSC__ prescaler
		847	* @param __DELAY__ timer output compare active/inactive delay (in us)
		848	* @param __PULSE__ pulse duration (in us)
		849	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		850	*/
		851	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
		852	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
		853	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
		854
		855	/**
		856	* @brief HELPER macro retrieving the ratio of the input capture prescaler
		857	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
		858	* @param __ICPSC__ This parameter can be one of the following values:
		859	* @arg @ref LL_TIM_ICPSC_DIV1
		860	* @arg @ref LL_TIM_ICPSC_DIV2
		861	* @arg @ref LL_TIM_ICPSC_DIV4
		862	* @arg @ref LL_TIM_ICPSC_DIV8
		863	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
		864	*/
		865	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
		866	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
		867
		868
		869	/**
		870	* @}
		871	*/
		872
		873
		874	/**
		875	* @}
		876	*/
		877
		878	/* Exported functions --------------------------------------------------------*/
		879	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
		880	* @{
		881	*/
		882
		883	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
		884	* @{
		885	*/
		886	/**
		887	* @brief Enable timer counter.
		888	* @rmtoll CR1 CEN LL_TIM_EnableCounter
		889	* @param TIMx Timer instance
		890	* @retval None
		891	*/
		892	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
		893	{
		894	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
		895	}
		896
		897	/**
		898	* @brief Disable timer counter.
		899	* @rmtoll CR1 CEN LL_TIM_DisableCounter
		900	* @param TIMx Timer instance
		901	* @retval None
		902	*/
		903	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
		904	{
		905	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
		906	}
		907
		908	/**
		909	* @brief Indicates whether the timer counter is enabled.
		910	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
		911	* @param TIMx Timer instance
		912	* @retval State of bit (1 or 0).
		913	*/
		914	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
		915	{
		916	return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
		917	}
		918
		919	/**
		920	* @brief Enable update event generation.
		921	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
		922	* @param TIMx Timer instance
		923	* @retval None
		924	*/
		925	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
		926	{
		927	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
		928	}
		929
		930	/**
		931	* @brief Disable update event generation.
		932	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
		933	* @param TIMx Timer instance
		934	* @retval None
		935	*/
		936	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
		937	{
		938	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
		939	}
		940
		941	/**
		942	* @brief Indicates whether update event generation is enabled.
		943	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
		944	* @param TIMx Timer instance
		945	* @retval Inverted state of bit (0 or 1).
		946	*/
		947	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
		948	{
		949	return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
		950	}
		951
		952	/**
		953	* @brief Set update event source
		954	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
		955	* generate an update interrupt or DMA request if enabled:
		956	* - Counter overflow/underflow
		957	* - Setting the UG bit
		958	* - Update generation through the slave mode controller
		959	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
		960	* overflow/underflow generates an update interrupt or DMA request if enabled.
		961	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
		962	* @param TIMx Timer instance
		963	* @param UpdateSource This parameter can be one of the following values:
		964	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		965	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		966	* @retval None
		967	*/
		968	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
		969	{
		970	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
		971	}
		972
		973	/**
		974	* @brief Get actual event update source
		975	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
		976	* @param TIMx Timer instance
		977	* @retval Returned value can be one of the following values:
		978	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		979	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		980	*/
		981	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
		982	{
		983	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
		984	}
		985
		986	/**
		987	* @brief Set one pulse mode (one shot v.s. repetitive).
		988	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
		989	* @param TIMx Timer instance
		990	* @param OnePulseMode This parameter can be one of the following values:
		991	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		992	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		993	* @retval None
		994	*/
		995	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
		996	{
		997	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
		998	}
		999
		1000	/**
		1001	* @brief Get actual one pulse mode.
		1002	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
		1003	* @param TIMx Timer instance
		1004	* @retval Returned value can be one of the following values:
		1005	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1006	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1007	*/
		1008	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
		1009	{
		1010	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
		1011	}
		1012
		1013	/**
		1014	* @brief Set the timer counter counting mode.
		1015	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1016	* check whether or not the counter mode selection feature is supported
		1017	* by a timer instance.
		1018	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		1019	* requires a timer reset to avoid unexpected direction
		1020	* due to DIR bit readonly in center aligned mode.
		1021	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
		1022	* CR1 CMS LL_TIM_SetCounterMode
		1023	* @param TIMx Timer instance
		1024	* @param CounterMode This parameter can be one of the following values:
		1025	* @arg @ref LL_TIM_COUNTERMODE_UP
		1026	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1027	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1028	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1029	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1030	* @retval None
		1031	*/
		1032	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
		1033	{
		1034	MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR \| TIM_CR1_CMS), CounterMode);
		1035	}
		1036
		1037	/**
		1038	* @brief Get actual counter mode.
		1039	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1040	* check whether or not the counter mode selection feature is supported
		1041	* by a timer instance.
		1042	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
		1043	* CR1 CMS LL_TIM_GetCounterMode
		1044	* @param TIMx Timer instance
		1045	* @retval Returned value can be one of the following values:
		1046	* @arg @ref LL_TIM_COUNTERMODE_UP
		1047	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1048	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1049	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1050	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1051	*/
		1052	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
		1053	{
61	mjames	1054	uint32_t counter_mode;
		1055
		1056	counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
		1057
		1058	if (counter_mode == 0U)
		1059	{
		1060	counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
		1061	}
		1062
		1063	return counter_mode;
56	mjames	1064	}
		1065
		1066	/**
		1067	* @brief Enable auto-reload (ARR) preload.
		1068	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
		1069	* @param TIMx Timer instance
		1070	* @retval None
		1071	*/
		1072	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
		1073	{
		1074	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1075	}
		1076
		1077	/**
		1078	* @brief Disable auto-reload (ARR) preload.
		1079	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
		1080	* @param TIMx Timer instance
		1081	* @retval None
		1082	*/
		1083	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
		1084	{
		1085	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1086	}
		1087
		1088	/**
		1089	* @brief Indicates whether auto-reload (ARR) preload is enabled.
		1090	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
		1091	* @param TIMx Timer instance
		1092	* @retval State of bit (1 or 0).
		1093	*/
		1094	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
		1095	{
		1096	return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
		1097	}
		1098
		1099	/**
61	mjames	1100	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
		1101	* (when supported) and the digital filters.
56	mjames	1102	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1103	* whether or not the clock division feature is supported by the timer
		1104	* instance.
		1105	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
		1106	* @param TIMx Timer instance
		1107	* @param ClockDivision This parameter can be one of the following values:
		1108	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1109	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1110	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1111	* @retval None
		1112	*/
		1113	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
		1114	{
		1115	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
		1116	}
		1117
		1118	/**
61	mjames	1119	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
		1120	* generators (when supported) and the digital filters.
56	mjames	1121	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1122	* whether or not the clock division feature is supported by the timer
		1123	* instance.
		1124	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
		1125	* @param TIMx Timer instance
		1126	* @retval Returned value can be one of the following values:
		1127	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1128	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1129	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1130	*/
		1131	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
		1132	{
		1133	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
		1134	}
		1135
		1136	/**
		1137	* @brief Set the counter value.
		1138	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1139	* whether or not a timer instance supports a 32 bits counter.
		1140	* @rmtoll CNT CNT LL_TIM_SetCounter
		1141	* @param TIMx Timer instance
		1142	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
		1143	* @retval None
		1144	*/
		1145	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
		1146	{
		1147	WRITE_REG(TIMx->CNT, Counter);
		1148	}
		1149
		1150	/**
		1151	* @brief Get the counter value.
		1152	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1153	* whether or not a timer instance supports a 32 bits counter.
		1154	* @rmtoll CNT CNT LL_TIM_GetCounter
		1155	* @param TIMx Timer instance
		1156	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
		1157	*/
		1158	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
		1159	{
		1160	return (uint32_t)(READ_REG(TIMx->CNT));
		1161	}
		1162
		1163	/**
		1164	* @brief Get the current direction of the counter
		1165	* @rmtoll CR1 DIR LL_TIM_GetDirection
		1166	* @param TIMx Timer instance
		1167	* @retval Returned value can be one of the following values:
		1168	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
		1169	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
		1170	*/
		1171	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
		1172	{
		1173	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
		1174	}
		1175
		1176	/**
		1177	* @brief Set the prescaler value.
		1178	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
		1179	* @note The prescaler can be changed on the fly as this control register is buffered. The new
		1180	* prescaler ratio is taken into account at the next update event.
		1181	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
		1182	* @rmtoll PSC PSC LL_TIM_SetPrescaler
		1183	* @param TIMx Timer instance
		1184	* @param Prescaler between Min_Data=0 and Max_Data=65535
		1185	* @retval None
		1186	*/
		1187	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
		1188	{
		1189	WRITE_REG(TIMx->PSC, Prescaler);
		1190	}
		1191
		1192	/**
		1193	* @brief Get the prescaler value.
		1194	* @rmtoll PSC PSC LL_TIM_GetPrescaler
		1195	* @param TIMx Timer instance
		1196	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
		1197	*/
		1198	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
		1199	{
		1200	return (uint32_t)(READ_REG(TIMx->PSC));
		1201	}
		1202
		1203	/**
		1204	* @brief Set the auto-reload value.
		1205	* @note The counter is blocked while the auto-reload value is null.
		1206	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1207	* whether or not a timer instance supports a 32 bits counter.
		1208	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
		1209	* @rmtoll ARR ARR LL_TIM_SetAutoReload
		1210	* @param TIMx Timer instance
		1211	* @param AutoReload between Min_Data=0 and Max_Data=65535
		1212	* @retval None
		1213	*/
		1214	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
		1215	{
		1216	WRITE_REG(TIMx->ARR, AutoReload);
		1217	}
		1218
		1219	/**
		1220	* @brief Get the auto-reload value.
		1221	* @rmtoll ARR ARR LL_TIM_GetAutoReload
		1222	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1223	* whether or not a timer instance supports a 32 bits counter.
		1224	* @param TIMx Timer instance
		1225	* @retval Auto-reload value
		1226	*/
		1227	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
		1228	{
		1229	return (uint32_t)(READ_REG(TIMx->ARR));
		1230	}
		1231
		1232	/**
		1233	* @}
		1234	*/
		1235
		1236	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
		1237	* @{
		1238	*/
		1239	/**
		1240	* @brief Set the trigger of the capture/compare DMA request.
		1241	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
		1242	* @param TIMx Timer instance
		1243	* @param DMAReqTrigger This parameter can be one of the following values:
		1244	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1245	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1246	* @retval None
		1247	*/
		1248	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
		1249	{
		1250	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
		1251	}
		1252
		1253	/**
		1254	* @brief Get actual trigger of the capture/compare DMA request.
		1255	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
		1256	* @param TIMx Timer instance
		1257	* @retval Returned value can be one of the following values:
		1258	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1259	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1260	*/
		1261	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
		1262	{
		1263	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
		1264	}
		1265
		1266	/**
		1267	* @brief Enable capture/compare channels.
		1268	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
		1269	* CCER CC2E LL_TIM_CC_EnableChannel\n
		1270	* CCER CC3E LL_TIM_CC_EnableChannel\n
		1271	* CCER CC4E LL_TIM_CC_EnableChannel
		1272	* @param TIMx Timer instance
		1273	* @param Channels This parameter can be a combination of the following values:
		1274	* @arg @ref LL_TIM_CHANNEL_CH1
		1275	* @arg @ref LL_TIM_CHANNEL_CH2
		1276	* @arg @ref LL_TIM_CHANNEL_CH3
		1277	* @arg @ref LL_TIM_CHANNEL_CH4
		1278	* @retval None
		1279	*/
		1280	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1281	{
		1282	SET_BIT(TIMx->CCER, Channels);
		1283	}
		1284
		1285	/**
		1286	* @brief Disable capture/compare channels.
		1287	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
		1288	* CCER CC2E LL_TIM_CC_DisableChannel\n
		1289	* CCER CC3E LL_TIM_CC_DisableChannel\n
		1290	* CCER CC4E LL_TIM_CC_DisableChannel
		1291	* @param TIMx Timer instance
		1292	* @param Channels This parameter can be a combination of the following values:
		1293	* @arg @ref LL_TIM_CHANNEL_CH1
		1294	* @arg @ref LL_TIM_CHANNEL_CH2
		1295	* @arg @ref LL_TIM_CHANNEL_CH3
		1296	* @arg @ref LL_TIM_CHANNEL_CH4
		1297	* @retval None
		1298	*/
		1299	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1300	{
		1301	CLEAR_BIT(TIMx->CCER, Channels);
		1302	}
		1303
		1304	/**
		1305	* @brief Indicate whether channel(s) is(are) enabled.
		1306	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
		1307	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
		1308	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
		1309	* CCER CC4E LL_TIM_CC_IsEnabledChannel
		1310	* @param TIMx Timer instance
		1311	* @param Channels This parameter can be a combination of the following values:
		1312	* @arg @ref LL_TIM_CHANNEL_CH1
		1313	* @arg @ref LL_TIM_CHANNEL_CH2
		1314	* @arg @ref LL_TIM_CHANNEL_CH3
		1315	* @arg @ref LL_TIM_CHANNEL_CH4
		1316	* @retval State of bit (1 or 0).
		1317	*/
		1318	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1319	{
		1320	return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
		1321	}
		1322
		1323	/**
		1324	* @}
		1325	*/
		1326
		1327	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
		1328	* @{
		1329	*/
		1330	/**
		1331	* @brief Configure an output channel.
		1332	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
		1333	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
		1334	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
		1335	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
		1336	* CCER CC1P LL_TIM_OC_ConfigOutput\n
		1337	* CCER CC2P LL_TIM_OC_ConfigOutput\n
		1338	* CCER CC3P LL_TIM_OC_ConfigOutput\n
		1339	* CCER CC4P LL_TIM_OC_ConfigOutput\n
		1340	* @param TIMx Timer instance
		1341	* @param Channel This parameter can be one of the following values:
		1342	* @arg @ref LL_TIM_CHANNEL_CH1
		1343	* @arg @ref LL_TIM_CHANNEL_CH2
		1344	* @arg @ref LL_TIM_CHANNEL_CH3
		1345	* @arg @ref LL_TIM_CHANNEL_CH4
		1346	* @param Configuration This parameter must be a combination of all the following values:
		1347	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
		1348	* @retval None
		1349	*/
		1350	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		1351	{
61	mjames	1352	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1353	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1354	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
		1355	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
		1356	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
		1357	}
		1358
		1359	/**
		1360	* @brief Define the behavior of the output reference signal OCxREF from which
		1361	* OCx and OCxN (when relevant) are derived.
		1362	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
		1363	* CCMR1 OC2M LL_TIM_OC_SetMode\n
		1364	* CCMR2 OC3M LL_TIM_OC_SetMode\n
		1365	* CCMR2 OC4M LL_TIM_OC_SetMode
		1366	* @param TIMx Timer instance
		1367	* @param Channel This parameter can be one of the following values:
		1368	* @arg @ref LL_TIM_CHANNEL_CH1
		1369	* @arg @ref LL_TIM_CHANNEL_CH2
		1370	* @arg @ref LL_TIM_CHANNEL_CH3
		1371	* @arg @ref LL_TIM_CHANNEL_CH4
		1372	* @param Mode This parameter can be one of the following values:
		1373	* @arg @ref LL_TIM_OCMODE_FROZEN
		1374	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1375	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1376	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1377	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1378	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1379	* @arg @ref LL_TIM_OCMODE_PWM1
		1380	* @arg @ref LL_TIM_OCMODE_PWM2
		1381	* @retval None
		1382	*/
		1383	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
		1384	{
61	mjames	1385	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1386	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1387	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
56	mjames	1388	}
		1389
		1390	/**
		1391	* @brief Get the output compare mode of an output channel.
		1392	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
		1393	* CCMR1 OC2M LL_TIM_OC_GetMode\n
		1394	* CCMR2 OC3M LL_TIM_OC_GetMode\n
		1395	* CCMR2 OC4M LL_TIM_OC_GetMode
		1396	* @param TIMx Timer instance
		1397	* @param Channel This parameter can be one of the following values:
		1398	* @arg @ref LL_TIM_CHANNEL_CH1
		1399	* @arg @ref LL_TIM_CHANNEL_CH2
		1400	* @arg @ref LL_TIM_CHANNEL_CH3
		1401	* @arg @ref LL_TIM_CHANNEL_CH4
		1402	* @retval Returned value can be one of the following values:
		1403	* @arg @ref LL_TIM_OCMODE_FROZEN
		1404	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1405	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1406	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1407	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1408	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1409	* @arg @ref LL_TIM_OCMODE_PWM1
		1410	* @arg @ref LL_TIM_OCMODE_PWM2
		1411	*/
		1412	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
		1413	{
61	mjames	1414	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1415	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1416	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
56	mjames	1417	}
		1418
		1419	/**
		1420	* @brief Set the polarity of an output channel.
		1421	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
		1422	* CCER CC2P LL_TIM_OC_SetPolarity\n
		1423	* CCER CC3P LL_TIM_OC_SetPolarity\n
		1424	* CCER CC4P LL_TIM_OC_SetPolarity
		1425	* @param TIMx Timer instance
		1426	* @param Channel This parameter can be one of the following values:
		1427	* @arg @ref LL_TIM_CHANNEL_CH1
		1428	* @arg @ref LL_TIM_CHANNEL_CH2
		1429	* @arg @ref LL_TIM_CHANNEL_CH3
		1430	* @arg @ref LL_TIM_CHANNEL_CH4
		1431	* @param Polarity This parameter can be one of the following values:
		1432	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1433	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1434	* @retval None
		1435	*/
		1436	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
		1437	{
61	mjames	1438	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
56	mjames	1439	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
		1440	}
		1441
		1442	/**
		1443	* @brief Get the polarity of an output channel.
		1444	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
		1445	* CCER CC2P LL_TIM_OC_GetPolarity\n
		1446	* CCER CC3P LL_TIM_OC_GetPolarity\n
		1447	* CCER CC4P LL_TIM_OC_GetPolarity
		1448	* @param TIMx Timer instance
		1449	* @param Channel This parameter can be one of the following values:
		1450	* @arg @ref LL_TIM_CHANNEL_CH1
		1451	* @arg @ref LL_TIM_CHANNEL_CH2
		1452	* @arg @ref LL_TIM_CHANNEL_CH3
		1453	* @arg @ref LL_TIM_CHANNEL_CH4
		1454	* @retval Returned value can be one of the following values:
		1455	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1456	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1457	*/
		1458	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		1459	{
61	mjames	1460	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
56	mjames	1461	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
		1462	}
		1463
		1464	/**
		1465	* @brief Enable fast mode for the output channel.
		1466	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
		1467	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
		1468	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
		1469	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
		1470	* CCMR2 OC4FE LL_TIM_OC_EnableFast
		1471	* @param TIMx Timer instance
		1472	* @param Channel This parameter can be one of the following values:
		1473	* @arg @ref LL_TIM_CHANNEL_CH1
		1474	* @arg @ref LL_TIM_CHANNEL_CH2
		1475	* @arg @ref LL_TIM_CHANNEL_CH3
		1476	* @arg @ref LL_TIM_CHANNEL_CH4
		1477	* @retval None
		1478	*/
		1479	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1480	{
61	mjames	1481	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1482	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1483	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1484
		1485	}
		1486
		1487	/**
		1488	* @brief Disable fast mode for the output channel.
		1489	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
		1490	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
		1491	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
		1492	* CCMR2 OC4FE LL_TIM_OC_DisableFast
		1493	* @param TIMx Timer instance
		1494	* @param Channel This parameter can be one of the following values:
		1495	* @arg @ref LL_TIM_CHANNEL_CH1
		1496	* @arg @ref LL_TIM_CHANNEL_CH2
		1497	* @arg @ref LL_TIM_CHANNEL_CH3
		1498	* @arg @ref LL_TIM_CHANNEL_CH4
		1499	* @retval None
		1500	*/
		1501	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1502	{
61	mjames	1503	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1504	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1505	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1506
		1507	}
		1508
		1509	/**
		1510	* @brief Indicates whether fast mode is enabled for the output channel.
		1511	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
		1512	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
		1513	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
		1514	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
		1515	* @param TIMx Timer instance
		1516	* @param Channel This parameter can be one of the following values:
		1517	* @arg @ref LL_TIM_CHANNEL_CH1
		1518	* @arg @ref LL_TIM_CHANNEL_CH2
		1519	* @arg @ref LL_TIM_CHANNEL_CH3
		1520	* @arg @ref LL_TIM_CHANNEL_CH4
		1521	* @retval State of bit (1 or 0).
		1522	*/
		1523	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1524	{
61	mjames	1525	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1526	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1527	uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
56	mjames	1528	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1529	}
		1530
		1531	/**
		1532	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
		1533	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
		1534	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
		1535	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
		1536	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
		1537	* @param TIMx Timer instance
		1538	* @param Channel This parameter can be one of the following values:
		1539	* @arg @ref LL_TIM_CHANNEL_CH1
		1540	* @arg @ref LL_TIM_CHANNEL_CH2
		1541	* @arg @ref LL_TIM_CHANNEL_CH3
		1542	* @arg @ref LL_TIM_CHANNEL_CH4
		1543	* @retval None
		1544	*/
		1545	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1546	{
61	mjames	1547	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1548	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1549	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1550	}
		1551
		1552	/**
		1553	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
		1554	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
		1555	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
		1556	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
		1557	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
		1558	* @param TIMx Timer instance
		1559	* @param Channel This parameter can be one of the following values:
		1560	* @arg @ref LL_TIM_CHANNEL_CH1
		1561	* @arg @ref LL_TIM_CHANNEL_CH2
		1562	* @arg @ref LL_TIM_CHANNEL_CH3
		1563	* @arg @ref LL_TIM_CHANNEL_CH4
		1564	* @retval None
		1565	*/
		1566	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1567	{
61	mjames	1568	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1569	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1570	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1571	}
		1572
		1573	/**
		1574	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
		1575	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
		1576	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
		1577	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
		1578	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
		1579	* @param TIMx Timer instance
		1580	* @param Channel This parameter can be one of the following values:
		1581	* @arg @ref LL_TIM_CHANNEL_CH1
		1582	* @arg @ref LL_TIM_CHANNEL_CH2
		1583	* @arg @ref LL_TIM_CHANNEL_CH3
		1584	* @arg @ref LL_TIM_CHANNEL_CH4
		1585	* @retval State of bit (1 or 0).
		1586	*/
		1587	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1588	{
61	mjames	1589	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1590	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1591	uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
56	mjames	1592	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1593	}
		1594
		1595	/**
		1596	* @brief Enable clearing the output channel on an external event.
		1597	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1598	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1599	* or not a timer instance can clear the OCxREF signal on an external event.
		1600	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
		1601	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
		1602	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
		1603	* CCMR2 OC4CE LL_TIM_OC_EnableClear
		1604	* @param TIMx Timer instance
		1605	* @param Channel This parameter can be one of the following values:
		1606	* @arg @ref LL_TIM_CHANNEL_CH1
		1607	* @arg @ref LL_TIM_CHANNEL_CH2
		1608	* @arg @ref LL_TIM_CHANNEL_CH3
		1609	* @arg @ref LL_TIM_CHANNEL_CH4
		1610	* @retval None
		1611	*/
		1612	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1613	{
61	mjames	1614	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1615	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1616	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1617	}
		1618
		1619	/**
		1620	* @brief Disable clearing the output channel on an external event.
		1621	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1622	* or not a timer instance can clear the OCxREF signal on an external event.
		1623	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
		1624	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
		1625	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
		1626	* CCMR2 OC4CE LL_TIM_OC_DisableClear
		1627	* @param TIMx Timer instance
		1628	* @param Channel This parameter can be one of the following values:
		1629	* @arg @ref LL_TIM_CHANNEL_CH1
		1630	* @arg @ref LL_TIM_CHANNEL_CH2
		1631	* @arg @ref LL_TIM_CHANNEL_CH3
		1632	* @arg @ref LL_TIM_CHANNEL_CH4
		1633	* @retval None
		1634	*/
		1635	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1636	{
61	mjames	1637	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1638	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1639	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1640	}
		1641
		1642	/**
		1643	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
		1644	* @note This function enables clearing the output channel on an external event.
		1645	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1646	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1647	* or not a timer instance can clear the OCxREF signal on an external event.
		1648	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
		1649	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
		1650	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
		1651	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
		1652	* @param TIMx Timer instance
		1653	* @param Channel This parameter can be one of the following values:
		1654	* @arg @ref LL_TIM_CHANNEL_CH1
		1655	* @arg @ref LL_TIM_CHANNEL_CH2
		1656	* @arg @ref LL_TIM_CHANNEL_CH3
		1657	* @arg @ref LL_TIM_CHANNEL_CH4
		1658	* @retval State of bit (1 or 0).
		1659	*/
		1660	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1661	{
61	mjames	1662	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1663	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1664	uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
56	mjames	1665	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1666	}
		1667
		1668	/**
		1669	* @brief Set compare value for output channel 1 (TIMx_CCR1).
		1670	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		1671	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1672	* whether or not a timer instance supports a 32 bits counter.
		1673	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		1674	* output channel 1 is supported by a timer instance.
		1675	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
		1676	* @param TIMx Timer instance
		1677	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1678	* @retval None
		1679	*/
		1680	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1681	{
		1682	WRITE_REG(TIMx->CCR1, CompareValue);
		1683	}
		1684
		1685	/**
		1686	* @brief Set compare value for output channel 2 (TIMx_CCR2).
		1687	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		1688	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1689	* whether or not a timer instance supports a 32 bits counter.
		1690	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		1691	* output channel 2 is supported by a timer instance.
		1692	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
		1693	* @param TIMx Timer instance
		1694	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1695	* @retval None
		1696	*/
		1697	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1698	{
		1699	WRITE_REG(TIMx->CCR2, CompareValue);
		1700	}
		1701
		1702	/**
		1703	* @brief Set compare value for output channel 3 (TIMx_CCR3).
		1704	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		1705	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1706	* whether or not a timer instance supports a 32 bits counter.
		1707	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		1708	* output channel is supported by a timer instance.
		1709	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
		1710	* @param TIMx Timer instance
		1711	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1712	* @retval None
		1713	*/
		1714	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1715	{
		1716	WRITE_REG(TIMx->CCR3, CompareValue);
		1717	}
		1718
		1719	/**
		1720	* @brief Set compare value for output channel 4 (TIMx_CCR4).
		1721	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		1722	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1723	* whether or not a timer instance supports a 32 bits counter.
		1724	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		1725	* output channel 4 is supported by a timer instance.
		1726	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
		1727	* @param TIMx Timer instance
		1728	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1729	* @retval None
		1730	*/
		1731	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1732	{
		1733	WRITE_REG(TIMx->CCR4, CompareValue);
		1734	}
		1735
		1736	/**
		1737	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
		1738	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		1739	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1740	* whether or not a timer instance supports a 32 bits counter.
		1741	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		1742	* output channel 1 is supported by a timer instance.
		1743	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
		1744	* @param TIMx Timer instance
		1745	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		1746	*/
		1747	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
		1748	{
		1749	return (uint32_t)(READ_REG(TIMx->CCR1));
		1750	}
		1751
		1752	/**
		1753	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
		1754	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		1755	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1756	* whether or not a timer instance supports a 32 bits counter.
		1757	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		1758	* output channel 2 is supported by a timer instance.
		1759	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
		1760	* @param TIMx Timer instance
		1761	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		1762	*/
		1763	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
		1764	{
		1765	return (uint32_t)(READ_REG(TIMx->CCR2));
		1766	}
		1767
		1768	/**
		1769	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
		1770	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		1771	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1772	* whether or not a timer instance supports a 32 bits counter.
		1773	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		1774	* output channel 3 is supported by a timer instance.
		1775	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
		1776	* @param TIMx Timer instance
		1777	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		1778	*/
		1779	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
		1780	{
		1781	return (uint32_t)(READ_REG(TIMx->CCR3));
		1782	}
		1783
		1784	/**
		1785	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
		1786	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		1787	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1788	* whether or not a timer instance supports a 32 bits counter.
		1789	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		1790	* output channel 4 is supported by a timer instance.
		1791	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
		1792	* @param TIMx Timer instance
		1793	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		1794	*/
		1795	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
		1796	{
		1797	return (uint32_t)(READ_REG(TIMx->CCR4));
		1798	}
		1799
		1800	/**
		1801	* @}
		1802	*/
		1803
		1804	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
		1805	* @{
		1806	*/
		1807	/**
		1808	* @brief Configure input channel.
		1809	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
		1810	* CCMR1 IC1PSC LL_TIM_IC_Config\n
		1811	* CCMR1 IC1F LL_TIM_IC_Config\n
		1812	* CCMR1 CC2S LL_TIM_IC_Config\n
		1813	* CCMR1 IC2PSC LL_TIM_IC_Config\n
		1814	* CCMR1 IC2F LL_TIM_IC_Config\n
		1815	* CCMR2 CC3S LL_TIM_IC_Config\n
		1816	* CCMR2 IC3PSC LL_TIM_IC_Config\n
		1817	* CCMR2 IC3F LL_TIM_IC_Config\n
		1818	* CCMR2 CC4S LL_TIM_IC_Config\n
		1819	* CCMR2 IC4PSC LL_TIM_IC_Config\n
		1820	* CCMR2 IC4F LL_TIM_IC_Config\n
		1821	* CCER CC1P LL_TIM_IC_Config\n
		1822	* CCER CC1NP LL_TIM_IC_Config\n
		1823	* CCER CC2P LL_TIM_IC_Config\n
		1824	* CCER CC2NP LL_TIM_IC_Config\n
		1825	* CCER CC3P LL_TIM_IC_Config\n
		1826	* CCER CC3NP LL_TIM_IC_Config\n
		1827	* CCER CC4P LL_TIM_IC_Config\n
		1828	* CCER CC4NP LL_TIM_IC_Config
		1829	* @param TIMx Timer instance
		1830	* @param Channel This parameter can be one of the following values:
		1831	* @arg @ref LL_TIM_CHANNEL_CH1
		1832	* @arg @ref LL_TIM_CHANNEL_CH2
		1833	* @arg @ref LL_TIM_CHANNEL_CH3
		1834	* @arg @ref LL_TIM_CHANNEL_CH4
		1835	* @param Configuration This parameter must be a combination of all the following values:
		1836	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
		1837	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
		1838	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
		1839	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
		1840	* @retval None
		1841	*/
		1842	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		1843	{
61	mjames	1844	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1845	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1846	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
61	mjames	1847	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) \
		1848	<< SHIFT_TAB_ICxx[iChannel]);
56	mjames	1849	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		1850	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
		1851	}
		1852
		1853	/**
		1854	* @brief Set the active input.
		1855	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
		1856	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
		1857	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
		1858	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
		1859	* @param TIMx Timer instance
		1860	* @param Channel This parameter can be one of the following values:
		1861	* @arg @ref LL_TIM_CHANNEL_CH1
		1862	* @arg @ref LL_TIM_CHANNEL_CH2
		1863	* @arg @ref LL_TIM_CHANNEL_CH3
		1864	* @arg @ref LL_TIM_CHANNEL_CH4
		1865	* @param ICActiveInput This parameter can be one of the following values:
		1866	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		1867	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		1868	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		1869	* @retval None
		1870	*/
		1871	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
		1872	{
61	mjames	1873	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1874	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1875	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		1876	}
		1877
		1878	/**
		1879	* @brief Get the current active input.
		1880	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
		1881	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
		1882	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
		1883	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
		1884	* @param TIMx Timer instance
		1885	* @param Channel This parameter can be one of the following values:
		1886	* @arg @ref LL_TIM_CHANNEL_CH1
		1887	* @arg @ref LL_TIM_CHANNEL_CH2
		1888	* @arg @ref LL_TIM_CHANNEL_CH3
		1889	* @arg @ref LL_TIM_CHANNEL_CH4
		1890	* @retval Returned value can be one of the following values:
		1891	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		1892	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		1893	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		1894	*/
		1895	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
		1896	{
61	mjames	1897	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1898	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1899	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		1900	}
		1901
		1902	/**
		1903	* @brief Set the prescaler of input channel.
		1904	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
		1905	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
		1906	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
		1907	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
		1908	* @param TIMx Timer instance
		1909	* @param Channel This parameter can be one of the following values:
		1910	* @arg @ref LL_TIM_CHANNEL_CH1
		1911	* @arg @ref LL_TIM_CHANNEL_CH2
		1912	* @arg @ref LL_TIM_CHANNEL_CH3
		1913	* @arg @ref LL_TIM_CHANNEL_CH4
		1914	* @param ICPrescaler This parameter can be one of the following values:
		1915	* @arg @ref LL_TIM_ICPSC_DIV1
		1916	* @arg @ref LL_TIM_ICPSC_DIV2
		1917	* @arg @ref LL_TIM_ICPSC_DIV4
		1918	* @arg @ref LL_TIM_ICPSC_DIV8
		1919	* @retval None
		1920	*/
		1921	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
		1922	{
61	mjames	1923	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1924	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1925	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		1926	}
		1927
		1928	/**
		1929	* @brief Get the current prescaler value acting on an input channel.
		1930	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
		1931	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
		1932	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
		1933	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
		1934	* @param TIMx Timer instance
		1935	* @param Channel This parameter can be one of the following values:
		1936	* @arg @ref LL_TIM_CHANNEL_CH1
		1937	* @arg @ref LL_TIM_CHANNEL_CH2
		1938	* @arg @ref LL_TIM_CHANNEL_CH3
		1939	* @arg @ref LL_TIM_CHANNEL_CH4
		1940	* @retval Returned value can be one of the following values:
		1941	* @arg @ref LL_TIM_ICPSC_DIV1
		1942	* @arg @ref LL_TIM_ICPSC_DIV2
		1943	* @arg @ref LL_TIM_ICPSC_DIV4
		1944	* @arg @ref LL_TIM_ICPSC_DIV8
		1945	*/
		1946	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
		1947	{
61	mjames	1948	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1949	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1950	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		1951	}
		1952
		1953	/**
		1954	* @brief Set the input filter duration.
		1955	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
		1956	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
		1957	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
		1958	* CCMR2 IC4F LL_TIM_IC_SetFilter
		1959	* @param TIMx Timer instance
		1960	* @param Channel This parameter can be one of the following values:
		1961	* @arg @ref LL_TIM_CHANNEL_CH1
		1962	* @arg @ref LL_TIM_CHANNEL_CH2
		1963	* @arg @ref LL_TIM_CHANNEL_CH3
		1964	* @arg @ref LL_TIM_CHANNEL_CH4
		1965	* @param ICFilter This parameter can be one of the following values:
		1966	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		1967	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		1968	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		1969	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		1970	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		1971	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		1972	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		1973	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		1974	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		1975	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		1976	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		1977	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		1978	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		1979	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		1980	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		1981	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		1982	* @retval None
		1983	*/
		1984	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
		1985	{
61	mjames	1986	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1987	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	1988	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		1989	}
		1990
		1991	/**
		1992	* @brief Get the input filter duration.
		1993	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
		1994	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
		1995	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
		1996	* CCMR2 IC4F LL_TIM_IC_GetFilter
		1997	* @param TIMx Timer instance
		1998	* @param Channel This parameter can be one of the following values:
		1999	* @arg @ref LL_TIM_CHANNEL_CH1
		2000	* @arg @ref LL_TIM_CHANNEL_CH2
		2001	* @arg @ref LL_TIM_CHANNEL_CH3
		2002	* @arg @ref LL_TIM_CHANNEL_CH4
		2003	* @retval Returned value can be one of the following values:
		2004	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2005	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2006	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2007	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2008	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2009	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2010	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2011	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2012	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2013	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2014	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2015	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2016	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2017	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2018	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2019	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2020	*/
		2021	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
		2022	{
61	mjames	2023	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2024	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
56	mjames	2025	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2026	}
		2027
		2028	/**
		2029	* @brief Set the input channel polarity.
		2030	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
		2031	* CCER CC1NP LL_TIM_IC_SetPolarity\n
		2032	* CCER CC2P LL_TIM_IC_SetPolarity\n
		2033	* CCER CC2NP LL_TIM_IC_SetPolarity\n
		2034	* CCER CC3P LL_TIM_IC_SetPolarity\n
		2035	* CCER CC3NP LL_TIM_IC_SetPolarity\n
		2036	* CCER CC4P LL_TIM_IC_SetPolarity\n
		2037	* CCER CC4NP LL_TIM_IC_SetPolarity
		2038	* @param TIMx Timer instance
		2039	* @param Channel This parameter can be one of the following values:
		2040	* @arg @ref LL_TIM_CHANNEL_CH1
		2041	* @arg @ref LL_TIM_CHANNEL_CH2
		2042	* @arg @ref LL_TIM_CHANNEL_CH3
		2043	* @arg @ref LL_TIM_CHANNEL_CH4
		2044	* @param ICPolarity This parameter can be one of the following values:
		2045	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2046	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2047	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
		2048	* @retval None
		2049	*/
		2050	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
		2051	{
61	mjames	2052	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
56	mjames	2053	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2054	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
		2055	}
		2056
		2057	/**
		2058	* @brief Get the current input channel polarity.
		2059	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
		2060	* CCER CC1NP LL_TIM_IC_GetPolarity\n
		2061	* CCER CC2P LL_TIM_IC_GetPolarity\n
		2062	* CCER CC2NP LL_TIM_IC_GetPolarity\n
		2063	* CCER CC3P LL_TIM_IC_GetPolarity\n
		2064	* CCER CC3NP LL_TIM_IC_GetPolarity\n
		2065	* CCER CC4P LL_TIM_IC_GetPolarity\n
		2066	* CCER CC4NP LL_TIM_IC_GetPolarity
		2067	* @param TIMx Timer instance
		2068	* @param Channel This parameter can be one of the following values:
		2069	* @arg @ref LL_TIM_CHANNEL_CH1
		2070	* @arg @ref LL_TIM_CHANNEL_CH2
		2071	* @arg @ref LL_TIM_CHANNEL_CH3
		2072	* @arg @ref LL_TIM_CHANNEL_CH4
		2073	* @retval Returned value can be one of the following values:
		2074	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2075	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2076	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
		2077	*/
		2078	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		2079	{
61	mjames	2080	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
56	mjames	2081	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
		2082	SHIFT_TAB_CCxP[iChannel]);
		2083	}
		2084
		2085	/**
		2086	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
		2087	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2088	* a timer instance provides an XOR input.
		2089	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
		2090	* @param TIMx Timer instance
		2091	* @retval None
		2092	*/
		2093	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
		2094	{
		2095	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2096	}
		2097
		2098	/**
		2099	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
		2100	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2101	* a timer instance provides an XOR input.
		2102	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
		2103	* @param TIMx Timer instance
		2104	* @retval None
		2105	*/
		2106	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
		2107	{
		2108	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2109	}
		2110
		2111	/**
		2112	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
		2113	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2114	* a timer instance provides an XOR input.
		2115	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
		2116	* @param TIMx Timer instance
		2117	* @retval State of bit (1 or 0).
		2118	*/
		2119	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
		2120	{
		2121	return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
		2122	}
		2123
		2124	/**
		2125	* @brief Get captured value for input channel 1.
		2126	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2127	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2128	* whether or not a timer instance supports a 32 bits counter.
		2129	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2130	* input channel 1 is supported by a timer instance.
		2131	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
		2132	* @param TIMx Timer instance
		2133	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2134	*/
		2135	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
		2136	{
		2137	return (uint32_t)(READ_REG(TIMx->CCR1));
		2138	}
		2139
		2140	/**
		2141	* @brief Get captured value for input channel 2.
		2142	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2143	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2144	* whether or not a timer instance supports a 32 bits counter.
		2145	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2146	* input channel 2 is supported by a timer instance.
		2147	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
		2148	* @param TIMx Timer instance
		2149	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2150	*/
		2151	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
		2152	{
		2153	return (uint32_t)(READ_REG(TIMx->CCR2));
		2154	}
		2155
		2156	/**
		2157	* @brief Get captured value for input channel 3.
		2158	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2159	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2160	* whether or not a timer instance supports a 32 bits counter.
		2161	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2162	* input channel 3 is supported by a timer instance.
		2163	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
		2164	* @param TIMx Timer instance
		2165	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2166	*/
		2167	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
		2168	{
		2169	return (uint32_t)(READ_REG(TIMx->CCR3));
		2170	}
		2171
		2172	/**
		2173	* @brief Get captured value for input channel 4.
		2174	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2175	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2176	* whether or not a timer instance supports a 32 bits counter.
		2177	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2178	* input channel 4 is supported by a timer instance.
		2179	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
		2180	* @param TIMx Timer instance
		2181	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2182	*/
		2183	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
		2184	{
		2185	return (uint32_t)(READ_REG(TIMx->CCR4));
		2186	}
		2187
		2188	/**
		2189	* @}
		2190	*/
		2191
		2192	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
		2193	* @{
		2194	*/
		2195	/**
		2196	* @brief Enable external clock mode 2.
		2197	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
		2198	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2199	* whether or not a timer instance supports external clock mode2.
		2200	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
		2201	* @param TIMx Timer instance
		2202	* @retval None
		2203	*/
		2204	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
		2205	{
		2206	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2207	}
		2208
		2209	/**
		2210	* @brief Disable external clock mode 2.
		2211	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2212	* whether or not a timer instance supports external clock mode2.
		2213	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
		2214	* @param TIMx Timer instance
		2215	* @retval None
		2216	*/
		2217	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
		2218	{
		2219	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2220	}
		2221
		2222	/**
		2223	* @brief Indicate whether external clock mode 2 is enabled.
		2224	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2225	* whether or not a timer instance supports external clock mode2.
		2226	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
		2227	* @param TIMx Timer instance
		2228	* @retval State of bit (1 or 0).
		2229	*/
		2230	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
		2231	{
		2232	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
		2233	}
		2234
		2235	/**
		2236	* @brief Set the clock source of the counter clock.
		2237	* @note when selected clock source is external clock mode 1, the timer input
		2238	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
		2239	* function. This timer input must be configured by calling
		2240	* the @ref LL_TIM_IC_Config() function.
		2241	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
		2242	* whether or not a timer instance supports external clock mode1.
		2243	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2244	* whether or not a timer instance supports external clock mode2.
		2245	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
		2246	* SMCR ECE LL_TIM_SetClockSource
		2247	* @param TIMx Timer instance
		2248	* @param ClockSource This parameter can be one of the following values:
		2249	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
		2250	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
		2251	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
		2252	* @retval None
		2253	*/
		2254	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
		2255	{
		2256	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
		2257	}
		2258
		2259	/**
		2260	* @brief Set the encoder interface mode.
		2261	* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
		2262	* whether or not a timer instance supports the encoder mode.
		2263	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
		2264	* @param TIMx Timer instance
		2265	* @param EncoderMode This parameter can be one of the following values:
		2266	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
		2267	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
		2268	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
		2269	* @retval None
		2270	*/
		2271	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
		2272	{
		2273	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
		2274	}
		2275
		2276	/**
		2277	* @}
		2278	*/
		2279
		2280	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
		2281	* @{
		2282	*/
		2283	/**
		2284	* @brief Set the trigger output (TRGO) used for timer synchronization .
		2285	* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
		2286	* whether or not a timer instance can operate as a master timer.
		2287	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
		2288	* @param TIMx Timer instance
		2289	* @param TimerSynchronization This parameter can be one of the following values:
		2290	* @arg @ref LL_TIM_TRGO_RESET
		2291	* @arg @ref LL_TIM_TRGO_ENABLE
		2292	* @arg @ref LL_TIM_TRGO_UPDATE
		2293	* @arg @ref LL_TIM_TRGO_CC1IF
		2294	* @arg @ref LL_TIM_TRGO_OC1REF
		2295	* @arg @ref LL_TIM_TRGO_OC2REF
		2296	* @arg @ref LL_TIM_TRGO_OC3REF
		2297	* @arg @ref LL_TIM_TRGO_OC4REF
		2298	* @retval None
		2299	*/
		2300	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
		2301	{
		2302	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
		2303	}
		2304
		2305	/**
		2306	* @brief Set the synchronization mode of a slave timer.
		2307	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2308	* a timer instance can operate as a slave timer.
		2309	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
		2310	* @param TIMx Timer instance
		2311	* @param SlaveMode This parameter can be one of the following values:
		2312	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
		2313	* @arg @ref LL_TIM_SLAVEMODE_RESET
		2314	* @arg @ref LL_TIM_SLAVEMODE_GATED
		2315	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
		2316	* @retval None
		2317	*/
		2318	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
		2319	{
		2320	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
		2321	}
		2322
		2323	/**
		2324	* @brief Set the selects the trigger input to be used to synchronize the counter.
		2325	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2326	* a timer instance can operate as a slave timer.
		2327	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
		2328	* @param TIMx Timer instance
		2329	* @param TriggerInput This parameter can be one of the following values:
		2330	* @arg @ref LL_TIM_TS_ITR0
		2331	* @arg @ref LL_TIM_TS_ITR1
		2332	* @arg @ref LL_TIM_TS_ITR2
		2333	* @arg @ref LL_TIM_TS_ITR3
		2334	* @arg @ref LL_TIM_TS_TI1F_ED
		2335	* @arg @ref LL_TIM_TS_TI1FP1
		2336	* @arg @ref LL_TIM_TS_TI2FP2
		2337	* @arg @ref LL_TIM_TS_ETRF
		2338	* @retval None
		2339	*/
		2340	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
		2341	{
		2342	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
		2343	}
		2344
		2345	/**
		2346	* @brief Enable the Master/Slave mode.
		2347	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2348	* a timer instance can operate as a slave timer.
		2349	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
		2350	* @param TIMx Timer instance
		2351	* @retval None
		2352	*/
		2353	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
		2354	{
		2355	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2356	}
		2357
		2358	/**
		2359	* @brief Disable the Master/Slave mode.
		2360	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2361	* a timer instance can operate as a slave timer.
		2362	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
		2363	* @param TIMx Timer instance
		2364	* @retval None
		2365	*/
		2366	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
		2367	{
		2368	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2369	}
		2370
		2371	/**
		2372	* @brief Indicates whether the Master/Slave mode is enabled.
		2373	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2374	* a timer instance can operate as a slave timer.
		2375	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
		2376	* @param TIMx Timer instance
		2377	* @retval State of bit (1 or 0).
		2378	*/
		2379	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
		2380	{
		2381	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
		2382	}
		2383
		2384	/**
		2385	* @brief Configure the external trigger (ETR) input.
		2386	* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
		2387	* a timer instance provides an external trigger input.
		2388	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
		2389	* SMCR ETPS LL_TIM_ConfigETR\n
		2390	* SMCR ETF LL_TIM_ConfigETR
		2391	* @param TIMx Timer instance
		2392	* @param ETRPolarity This parameter can be one of the following values:
		2393	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
		2394	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
		2395	* @param ETRPrescaler This parameter can be one of the following values:
		2396	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
		2397	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
		2398	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
		2399	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
		2400	* @param ETRFilter This parameter can be one of the following values:
		2401	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
		2402	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
		2403	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
		2404	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
		2405	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
		2406	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
		2407	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
		2408	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
		2409	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
		2410	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
		2411	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
		2412	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
		2413	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
		2414	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
		2415	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
		2416	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
		2417	* @retval None
		2418	*/
		2419	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
		2420	uint32_t ETRFilter)
		2421	{
		2422	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
		2423	}
		2424
		2425	/**
		2426	* @}
		2427	*/
		2428
		2429	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
		2430	* @{
		2431	*/
		2432	/**
		2433	* @brief Configures the timer DMA burst feature.
		2434	* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
		2435	* not a timer instance supports the DMA burst mode.
		2436	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
		2437	* DCR DBA LL_TIM_ConfigDMABurst
		2438	* @param TIMx Timer instance
		2439	* @param DMABurstBaseAddress This parameter can be one of the following values:
		2440	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
		2441	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
		2442	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
		2443	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
		2444	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
		2445	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
		2446	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
		2447	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
		2448	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
		2449	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
		2450	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
		2451	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
		2452	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
		2453	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
		2454	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
		2455	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
		2456	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
		2457	* @param DMABurstLength This parameter can be one of the following values:
		2458	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
		2459	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
		2460	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
		2461	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
		2462	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
		2463	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
		2464	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
		2465	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
		2466	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
		2467	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
		2468	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
		2469	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
		2470	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
		2471	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
		2472	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
		2473	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
		2474	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
		2475	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
		2476	* @retval None
		2477	*/
		2478	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
		2479	{
		2480	MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL \| TIM_DCR_DBA), (DMABurstBaseAddress \| DMABurstLength));
		2481	}
		2482
		2483	/**
		2484	* @}
		2485	*/
		2486
		2487	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
		2488	* @{
		2489	*/
		2490	/**
		2491	* @brief Remap TIM inputs (input channel, internal/external triggers).
		2492	* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
		2493	* a some timer inputs can be remapped.
		2494	* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
		2495	* TIM3_OR ITR2_RMP LL_TIM_SetRemap\n
		2496	* TIM9_OR TI1_RMP LL_TIM_SetRemap\n
		2497	* TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
		2498	* TIM10_OR TI1_RMP LL_TIM_SetRemap\n
		2499	* TIM10_OR ETR_RMP LL_TIM_SetRemap\n
		2500	* TIM10_OR TI1_RMP_RI LL_TIM_SetRemap\n
		2501	* TIM11_OR TI1_RMP LL_TIM_SetRemap\n
		2502	* TIM11_OR ETR_RMP LL_TIM_SetRemap\n
		2503	* TIM11_OR TI1_RMP_RI LL_TIM_SetRemap
		2504	* @param TIMx Timer instance
		2505	* @param Remap Remap params depends on the TIMx. Description available only
		2506	* in CHM version of the User Manual (not in .pdf).
		2507	* Otherwise see Reference Manual description of OR registers.
		2508	*
		2509	* Below description summarizes "Timer Instance" and "Remap" param combinations:
		2510	*
		2511	* TIM2: any combination of ITR1_RMP where
		2512	*
		2513	* . . ITR1_RMP can be one of the following values
		2514	* @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM10_OC (**)
		2515	* @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (**)
		2516	*
		2517	* TIM3: any combination of ITR2_RMP where
		2518	*
		2519	* . . ITR2_RMP can be one of the following values
		2520	* @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM11_OC (**)
		2521	* @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (**)
		2522	*
		2523	* TIM9: any combination of TI1_RMP, ITR1_RMP where
		2524	*
		2525	* . . TI1_RMP can be one of the following values
		2526	* @arg @ref LL_TIM_TIM9_TI1_RMP_LSE
		2527	* @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
		2528	*
		2529	* . . ITR1_RMP can be one of the following values
		2530	* @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TGO (*)
		2531	* @arg @ref LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (*)
		2532	*
		2533	*
		2534	* TIM10: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
		2535	*
		2536	* . . TI1_RMP can be one of the following values
		2537	* @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO
		2538	* @arg @ref LL_TIM_TIM10_TI1_RMP_LSI
		2539	* @arg @ref LL_TIM_TIM10_TI1_RMP_LSE
		2540	* @arg @ref LL_TIM_TIM10_TI1_RMP_RTC
		2541	*
		2542	* . . ETR_RMP can be one of the following values
		2543	* @arg @ref LL_TIM_TIM10_ETR_RMP_TIM9_TGO (*)
		2544	*
		2545	* . . TI1_RMP_RI can be one of the following values
		2546	* @arg @ref LL_TIM_TIM10_TI1_RMP_RI (*)
		2547	*
		2548	*
		2549	* TIM11: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
		2550	*
		2551	* . . TI1_RMP can be one of the following values
		2552	* @arg @ref LL_TIM_TIM11_TI1_RMP_MSI
		2553	* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
		2554	* @arg @ref LL_TIM_TIM11_TI1_RMP
		2555	*
		2556	* . . ETR_RMP can be one of the following values
		2557	* @arg @ref LL_TIM_TIM11_ETR_RMP_TIM9_TGO (*)
		2558	*
		2559	* . . TI1_RMP_RI can be one of the following values
		2560	* @arg @ref LL_TIM_TIM11_TI1_RMP_RI (*)
		2561	*
		2562	* (*) value not available in all devices categories
		2563	* (**) register not available in all devices categories
		2564	*
		2565	* @note Option registers are available only for cat.3, cat.4 and cat.5 devices
		2566	* @retval None
		2567	*/
		2568	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
		2569	{
		2570	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
		2571	}
		2572
		2573	/**
		2574	* @}
		2575	*/
		2576
		2577	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
		2578	* @{
		2579	*/
		2580	/**
		2581	* @brief Set the OCREF clear input source
		2582	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
		2583	* @note This function can only be used in Output compare and PWM modes.
		2584	* @note the ETR signal can be connected to the output of a comparator to be used for current handling
		2585	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
		2586	* @param TIMx Timer instance
		2587	* @param OCRefClearInputSource This parameter can be one of the following values:
		2588	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
		2589	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
		2590	* @retval None
		2591	*/
		2592	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
		2593	{
		2594	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
		2595	}
		2596	/**
		2597	* @}
		2598	*/
		2599
		2600	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
		2601	* @{
		2602	*/
		2603	/**
		2604	* @brief Clear the update interrupt flag (UIF).
		2605	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
		2606	* @param TIMx Timer instance
		2607	* @retval None
		2608	*/
		2609	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
		2610	{
		2611	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
		2612	}
		2613
		2614	/**
		2615	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
		2616	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
		2617	* @param TIMx Timer instance
		2618	* @retval State of bit (1 or 0).
		2619	*/
		2620	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
		2621	{
		2622	return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
		2623	}
		2624
		2625	/**
		2626	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
		2627	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
		2628	* @param TIMx Timer instance
		2629	* @retval None
		2630	*/
		2631	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
		2632	{
		2633	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
		2634	}
		2635
		2636	/**
		2637	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
		2638	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
		2639	* @param TIMx Timer instance
		2640	* @retval State of bit (1 or 0).
		2641	*/
		2642	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
		2643	{
		2644	return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
		2645	}
		2646
		2647	/**
		2648	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
		2649	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
		2650	* @param TIMx Timer instance
		2651	* @retval None
		2652	*/
		2653	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
		2654	{
		2655	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
		2656	}
		2657
		2658	/**
		2659	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
		2660	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
		2661	* @param TIMx Timer instance
		2662	* @retval State of bit (1 or 0).
		2663	*/
		2664	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
		2665	{
		2666	return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
		2667	}
		2668
		2669	/**
		2670	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
		2671	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
		2672	* @param TIMx Timer instance
		2673	* @retval None
		2674	*/
		2675	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
		2676	{
		2677	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
		2678	}
		2679
		2680	/**
		2681	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
		2682	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
		2683	* @param TIMx Timer instance
		2684	* @retval State of bit (1 or 0).
		2685	*/
		2686	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
		2687	{
		2688	return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
		2689	}
		2690
		2691	/**
		2692	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
		2693	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
		2694	* @param TIMx Timer instance
		2695	* @retval None
		2696	*/
		2697	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
		2698	{
		2699	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
		2700	}
		2701
		2702	/**
		2703	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
		2704	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
		2705	* @param TIMx Timer instance
		2706	* @retval State of bit (1 or 0).
		2707	*/
		2708	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
		2709	{
		2710	return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
		2711	}
		2712
		2713	/**
		2714	* @brief Clear the trigger interrupt flag (TIF).
		2715	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
		2716	* @param TIMx Timer instance
		2717	* @retval None
		2718	*/
		2719	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
		2720	{
		2721	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
		2722	}
		2723
		2724	/**
		2725	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
		2726	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
		2727	* @param TIMx Timer instance
		2728	* @retval State of bit (1 or 0).
		2729	*/
		2730	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
		2731	{
		2732	return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
		2733	}
		2734
		2735	/**
		2736	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
		2737	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
		2738	* @param TIMx Timer instance
		2739	* @retval None
		2740	*/
		2741	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
		2742	{
		2743	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
		2744	}
		2745
		2746	/**
61	mjames	2747	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
		2748	* (Capture/Compare 1 interrupt is pending).
56	mjames	2749	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
		2750	* @param TIMx Timer instance
		2751	* @retval State of bit (1 or 0).
		2752	*/
		2753	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
		2754	{
		2755	return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
		2756	}
		2757
		2758	/**
		2759	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
		2760	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
		2761	* @param TIMx Timer instance
		2762	* @retval None
		2763	*/
		2764	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
		2765	{
		2766	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
		2767	}
		2768
		2769	/**
61	mjames	2770	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
		2771	* (Capture/Compare 2 over-capture interrupt is pending).
56	mjames	2772	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
		2773	* @param TIMx Timer instance
		2774	* @retval State of bit (1 or 0).
		2775	*/
		2776	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
		2777	{
		2778	return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
		2779	}
		2780
		2781	/**
		2782	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
		2783	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
		2784	* @param TIMx Timer instance
		2785	* @retval None
		2786	*/
		2787	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
		2788	{
		2789	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
		2790	}
		2791
		2792	/**
61	mjames	2793	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
		2794	* (Capture/Compare 3 over-capture interrupt is pending).
56	mjames	2795	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
		2796	* @param TIMx Timer instance
		2797	* @retval State of bit (1 or 0).
		2798	*/
		2799	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
		2800	{
		2801	return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
		2802	}
		2803
		2804	/**
		2805	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
		2806	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
		2807	* @param TIMx Timer instance
		2808	* @retval None
		2809	*/
		2810	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
		2811	{
		2812	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
		2813	}
		2814
		2815	/**
61	mjames	2816	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
		2817	* (Capture/Compare 4 over-capture interrupt is pending).
56	mjames	2818	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
		2819	* @param TIMx Timer instance
		2820	* @retval State of bit (1 or 0).
		2821	*/
		2822	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
		2823	{
		2824	return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
		2825	}
		2826
		2827	/**
		2828	* @}
		2829	*/
		2830
		2831	/** @defgroup TIM_LL_EF_IT_Management IT-Management
		2832	* @{
		2833	*/
		2834	/**
		2835	* @brief Enable update interrupt (UIE).
		2836	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
		2837	* @param TIMx Timer instance
		2838	* @retval None
		2839	*/
		2840	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
		2841	{
		2842	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
		2843	}
		2844
		2845	/**
		2846	* @brief Disable update interrupt (UIE).
		2847	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
		2848	* @param TIMx Timer instance
		2849	* @retval None
		2850	*/
		2851	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
		2852	{
		2853	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
		2854	}
		2855
		2856	/**
		2857	* @brief Indicates whether the update interrupt (UIE) is enabled.
		2858	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
		2859	* @param TIMx Timer instance
		2860	* @retval State of bit (1 or 0).
		2861	*/
		2862	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
		2863	{
		2864	return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
		2865	}
		2866
		2867	/**
		2868	* @brief Enable capture/compare 1 interrupt (CC1IE).
		2869	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
		2870	* @param TIMx Timer instance
		2871	* @retval None
		2872	*/
		2873	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
		2874	{
		2875	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		2876	}
		2877
		2878	/**
		2879	* @brief Disable capture/compare 1 interrupt (CC1IE).
		2880	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
		2881	* @param TIMx Timer instance
		2882	* @retval None
		2883	*/
		2884	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
		2885	{
		2886	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		2887	}
		2888
		2889	/**
		2890	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
		2891	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
		2892	* @param TIMx Timer instance
		2893	* @retval State of bit (1 or 0).
		2894	*/
		2895	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
		2896	{
		2897	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
		2898	}
		2899
		2900	/**
		2901	* @brief Enable capture/compare 2 interrupt (CC2IE).
		2902	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
		2903	* @param TIMx Timer instance
		2904	* @retval None
		2905	*/
		2906	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
		2907	{
		2908	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		2909	}
		2910
		2911	/**
		2912	* @brief Disable capture/compare 2 interrupt (CC2IE).
		2913	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
		2914	* @param TIMx Timer instance
		2915	* @retval None
		2916	*/
		2917	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
		2918	{
		2919	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		2920	}
		2921
		2922	/**
		2923	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
		2924	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
		2925	* @param TIMx Timer instance
		2926	* @retval State of bit (1 or 0).
		2927	*/
		2928	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
		2929	{
		2930	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
		2931	}
		2932
		2933	/**
		2934	* @brief Enable capture/compare 3 interrupt (CC3IE).
		2935	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
		2936	* @param TIMx Timer instance
		2937	* @retval None
		2938	*/
		2939	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
		2940	{
		2941	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		2942	}
		2943
		2944	/**
		2945	* @brief Disable capture/compare 3 interrupt (CC3IE).
		2946	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
		2947	* @param TIMx Timer instance
		2948	* @retval None
		2949	*/
		2950	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
		2951	{
		2952	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		2953	}
		2954
		2955	/**
		2956	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
		2957	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
		2958	* @param TIMx Timer instance
		2959	* @retval State of bit (1 or 0).
		2960	*/
		2961	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
		2962	{
		2963	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
		2964	}
		2965
		2966	/**
		2967	* @brief Enable capture/compare 4 interrupt (CC4IE).
		2968	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
		2969	* @param TIMx Timer instance
		2970	* @retval None
		2971	*/
		2972	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
		2973	{
		2974	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		2975	}
		2976
		2977	/**
		2978	* @brief Disable capture/compare 4 interrupt (CC4IE).
		2979	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
		2980	* @param TIMx Timer instance
		2981	* @retval None
		2982	*/
		2983	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
		2984	{
		2985	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		2986	}
		2987
		2988	/**
		2989	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
		2990	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
		2991	* @param TIMx Timer instance
		2992	* @retval State of bit (1 or 0).
		2993	*/
		2994	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
		2995	{
		2996	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
		2997	}
		2998
		2999	/**
		3000	* @brief Enable trigger interrupt (TIE).
		3001	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
		3002	* @param TIMx Timer instance
		3003	* @retval None
		3004	*/
		3005	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
		3006	{
		3007	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
		3008	}
		3009
		3010	/**
		3011	* @brief Disable trigger interrupt (TIE).
		3012	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
		3013	* @param TIMx Timer instance
		3014	* @retval None
		3015	*/
		3016	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
		3017	{
		3018	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
		3019	}
		3020
		3021	/**
		3022	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
		3023	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
		3024	* @param TIMx Timer instance
		3025	* @retval State of bit (1 or 0).
		3026	*/
		3027	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
		3028	{
		3029	return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
		3030	}
		3031
		3032	/**
		3033	* @}
		3034	*/
		3035
		3036	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
		3037	* @{
		3038	*/
		3039	/**
		3040	* @brief Enable update DMA request (UDE).
		3041	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
		3042	* @param TIMx Timer instance
		3043	* @retval None
		3044	*/
		3045	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3046	{
		3047	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
		3048	}
		3049
		3050	/**
		3051	* @brief Disable update DMA request (UDE).
		3052	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
		3053	* @param TIMx Timer instance
		3054	* @retval None
		3055	*/
		3056	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3057	{
		3058	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
		3059	}
		3060
		3061	/**
		3062	* @brief Indicates whether the update DMA request (UDE) is enabled.
		3063	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
		3064	* @param TIMx Timer instance
		3065	* @retval State of bit (1 or 0).
		3066	*/
		3067	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3068	{
		3069	return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
		3070	}
		3071
		3072	/**
		3073	* @brief Enable capture/compare 1 DMA request (CC1DE).
		3074	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
		3075	* @param TIMx Timer instance
		3076	* @retval None
		3077	*/
		3078	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
		3079	{
		3080	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3081	}
		3082
		3083	/**
		3084	* @brief Disable capture/compare 1 DMA request (CC1DE).
		3085	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
		3086	* @param TIMx Timer instance
		3087	* @retval None
		3088	*/
		3089	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
		3090	{
		3091	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3092	}
		3093
		3094	/**
		3095	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
		3096	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
		3097	* @param TIMx Timer instance
		3098	* @retval State of bit (1 or 0).
		3099	*/
		3100	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
		3101	{
		3102	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
		3103	}
		3104
		3105	/**
		3106	* @brief Enable capture/compare 2 DMA request (CC2DE).
		3107	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
		3108	* @param TIMx Timer instance
		3109	* @retval None
		3110	*/
		3111	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
		3112	{
		3113	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3114	}
		3115
		3116	/**
		3117	* @brief Disable capture/compare 2 DMA request (CC2DE).
		3118	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
		3119	* @param TIMx Timer instance
		3120	* @retval None
		3121	*/
		3122	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
		3123	{
		3124	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3125	}
		3126
		3127	/**
		3128	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
		3129	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
		3130	* @param TIMx Timer instance
		3131	* @retval State of bit (1 or 0).
		3132	*/
		3133	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
		3134	{
		3135	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
		3136	}
		3137
		3138	/**
		3139	* @brief Enable capture/compare 3 DMA request (CC3DE).
		3140	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
		3141	* @param TIMx Timer instance
		3142	* @retval None
		3143	*/
		3144	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
		3145	{
		3146	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3147	}
		3148
		3149	/**
		3150	* @brief Disable capture/compare 3 DMA request (CC3DE).
		3151	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
		3152	* @param TIMx Timer instance
		3153	* @retval None
		3154	*/
		3155	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
		3156	{
		3157	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3158	}
		3159
		3160	/**
		3161	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
		3162	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
		3163	* @param TIMx Timer instance
		3164	* @retval State of bit (1 or 0).
		3165	*/
		3166	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
		3167	{
		3168	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
		3169	}
		3170
		3171	/**
		3172	* @brief Enable capture/compare 4 DMA request (CC4DE).
		3173	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
		3174	* @param TIMx Timer instance
		3175	* @retval None
		3176	*/
		3177	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
		3178	{
		3179	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3180	}
		3181
		3182	/**
		3183	* @brief Disable capture/compare 4 DMA request (CC4DE).
		3184	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
		3185	* @param TIMx Timer instance
		3186	* @retval None
		3187	*/
		3188	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
		3189	{
		3190	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3191	}
		3192
		3193	/**
		3194	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
		3195	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
		3196	* @param TIMx Timer instance
		3197	* @retval State of bit (1 or 0).
		3198	*/
		3199	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
		3200	{
		3201	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
		3202	}
		3203
		3204	/**
		3205	* @brief Enable trigger interrupt (TDE).
		3206	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
		3207	* @param TIMx Timer instance
		3208	* @retval None
		3209	*/
		3210	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3211	{
		3212	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
		3213	}
		3214
		3215	/**
		3216	* @brief Disable trigger interrupt (TDE).
		3217	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
		3218	* @param TIMx Timer instance
		3219	* @retval None
		3220	*/
		3221	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3222	{
		3223	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
		3224	}
		3225
		3226	/**
		3227	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
		3228	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
		3229	* @param TIMx Timer instance
		3230	* @retval State of bit (1 or 0).
		3231	*/
		3232	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
		3233	{
		3234	return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
		3235	}
		3236
		3237	/**
		3238	* @}
		3239	*/
		3240
		3241	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
		3242	* @{
		3243	*/
		3244	/**
		3245	* @brief Generate an update event.
		3246	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
		3247	* @param TIMx Timer instance
		3248	* @retval None
		3249	*/
		3250	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
		3251	{
		3252	SET_BIT(TIMx->EGR, TIM_EGR_UG);
		3253	}
		3254
		3255	/**
		3256	* @brief Generate Capture/Compare 1 event.
		3257	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
		3258	* @param TIMx Timer instance
		3259	* @retval None
		3260	*/
		3261	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
		3262	{
		3263	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
		3264	}
		3265
		3266	/**
		3267	* @brief Generate Capture/Compare 2 event.
		3268	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
		3269	* @param TIMx Timer instance
		3270	* @retval None
		3271	*/
		3272	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
		3273	{
		3274	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
		3275	}
		3276
		3277	/**
		3278	* @brief Generate Capture/Compare 3 event.
		3279	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
		3280	* @param TIMx Timer instance
		3281	* @retval None
		3282	*/
		3283	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
		3284	{
		3285	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
		3286	}
		3287
		3288	/**
		3289	* @brief Generate Capture/Compare 4 event.
		3290	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
		3291	* @param TIMx Timer instance
		3292	* @retval None
		3293	*/
		3294	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
		3295	{
		3296	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
		3297	}
		3298
		3299	/**
		3300	* @brief Generate trigger event.
		3301	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
		3302	* @param TIMx Timer instance
		3303	* @retval None
		3304	*/
		3305	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
		3306	{
		3307	SET_BIT(TIMx->EGR, TIM_EGR_TG);
		3308	}
		3309
		3310	/**
		3311	* @}
		3312	*/
		3313
		3314	#if defined(USE_FULL_LL_DRIVER)
		3315	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
		3316	* @{
		3317	*/
		3318
		3319	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
		3320	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
		3321	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
		3322	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
		3323	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
		3324	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
		3325	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
		3326	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
		3327	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
		3328	/**
		3329	* @}
		3330	*/
		3331	#endif /* USE_FULL_LL_DRIVER */
		3332
		3333	/**
		3334	* @}
		3335	*/
		3336
		3337	/**
		3338	* @}
		3339	*/
		3340
		3341	#endif /* TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM9 \|\| TIM10 \|\| TIM11 TIM6 \|\| TIM7 */
		3342
		3343	/**
		3344	* @}
		3345	*/
		3346
		3347	#ifdef __cplusplus
		3348	}
		3349	#endif
		3350
		3351	#endif /* __STM32L1xx_LL_TIM_H */
		3352	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/branches/Dashboard_L152_210623/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h – Rev 61