WebSVN – DashDisplay – Blame – /branches/Dashboard_L152_210623/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h

Rev	Author	Line No.	Line
56	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32l1xx_ll_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef __STM32L1xx_LL_TIM_H
		22	#define __STM32L1xx_LL_TIM_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32l1xx.h"
		30
		31	/** @addtogroup STM32L1xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM6) \|\| defined (TIM7)
		36
		37	/** @defgroup TIM_LL TIM
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
		44	* @{
		45	*/
		46	static const uint8_t OFFSET_TAB_CCMRx[] =
		47	{
		48	0x00U, /* 0: TIMx_CH1 */
		49	0x00U, /* 1: NA */
		50	0x00U, /* 2: TIMx_CH2 */
		51	0x00U, /* 3: NA */
		52	0x04U, /* 4: TIMx_CH3 */
		53	0x00U, /* 5: NA */
		54	0x04U /* 6: TIMx_CH4 */
		55	};
		56
		57	static const uint8_t SHIFT_TAB_OCxx[] =
		58	{
		59	0U, /* 0: OC1M, OC1FE, OC1PE */
		60	0U, /* 1: - NA */
		61	8U, /* 2: OC2M, OC2FE, OC2PE */
		62	0U, /* 3: - NA */
		63	0U, /* 4: OC3M, OC3FE, OC3PE */
		64	0U, /* 5: - NA */
		65	8U /* 6: OC4M, OC4FE, OC4PE */
		66	};
		67
		68	static const uint8_t SHIFT_TAB_ICxx[] =
		69	{
		70	0U, /* 0: CC1S, IC1PSC, IC1F */
		71	0U, /* 1: - NA */
		72	8U, /* 2: CC2S, IC2PSC, IC2F */
		73	0U, /* 3: - NA */
		74	0U, /* 4: CC3S, IC3PSC, IC3F */
		75	0U, /* 5: - NA */
		76	8U /* 6: CC4S, IC4PSC, IC4F */
		77	};
		78
		79	static const uint8_t SHIFT_TAB_CCxP[] =
		80	{
		81	0U, /* 0: CC1P */
		82	0U, /* 1: NA */
		83	4U, /* 2: CC2P */
		84	0U, /* 3: NA */
		85	8U, /* 4: CC3P */
		86	0U, /* 5: NA */
		87	12U /* 6: CC4P */
		88	};
		89
		90	/**
		91	* @}
		92	*/
		93
		94	/* Private constants ---------------------------------------------------------*/
		95	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
		96	* @{
		97	*/
		98
		99
		100	#define TIMx_OR_RMP_SHIFT 16U
		101	#define TIMx_OR_RMP_MASK 0x0000FFFFU
		102	#define TIM_OR_RMP_MASK ((TIM_OR_TI1RMP \| TIM_OR_ETR_RMP \| TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT)
		103	#define TIM9_OR_RMP_MASK ((TIM_OR_TI1RMP \| TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
		104	#define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
		105	#define TIM3_OR_RMP_MASK (TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT)
		106
		107
		108
		109	/**
		110	* @}
		111	*/
		112
		113	/* Private macros ------------------------------------------------------------*/
		114	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
		115	* @{
		116	*/
		117	/** @brief Convert channel id into channel index.
		118	* @param __CHANNEL__ This parameter can be one of the following values:
		119	* @arg @ref LL_TIM_CHANNEL_CH1
		120	* @arg @ref LL_TIM_CHANNEL_CH2
		121	* @arg @ref LL_TIM_CHANNEL_CH3
		122	* @arg @ref LL_TIM_CHANNEL_CH4
		123	* @retval none
		124	*/
		125	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
		126	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
		127	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
		128	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
		129
		130	/**
		131	* @}
		132	*/
		133
		134
		135	/* Exported types ------------------------------------------------------------*/
		136	#if defined(USE_FULL_LL_DRIVER)
		137	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
		138	* @{
		139	*/
		140
		141	/**
		142	* @brief TIM Time Base configuration structure definition.
		143	*/
		144	typedef struct
		145	{
		146	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		147	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		148
		149	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
		150
		151	uint32_t CounterMode; /*!< Specifies the counter mode.
		152	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
		153
		154	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
		155
		156	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
		157	Auto-Reload Register at the next update event.
		158	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		159	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
		160
		161	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
		162
		163	uint32_t ClockDivision; /*!< Specifies the clock division.
		164	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
		165
		166	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
		167	} LL_TIM_InitTypeDef;
		168
		169	/**
		170	* @brief TIM Output Compare configuration structure definition.
		171	*/
		172	typedef struct
		173	{
		174	uint32_t OCMode; /*!< Specifies the output mode.
		175	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
		176
		177	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
		178
		179	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
		180	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		181
		182	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
		183
		184	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
		185	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		186
		187	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
		188
		189	uint32_t OCPolarity; /*!< Specifies the output polarity.
		190	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		191
		192	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
		193
		194
		195	} LL_TIM_OC_InitTypeDef;
		196
		197	/**
		198	* @brief TIM Input Capture configuration structure definition.
		199	*/
		200
		201	typedef struct
		202	{
		203
		204	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		205	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		206
		207	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		208
		209	uint32_t ICActiveInput; /*!< Specifies the input.
		210	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		211
		212	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		213
		214	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		215	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		216
		217	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		218
		219	uint32_t ICFilter; /*!< Specifies the input capture filter.
		220	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		221
		222	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		223	} LL_TIM_IC_InitTypeDef;
		224
		225
		226	/**
		227	* @brief TIM Encoder interface configuration structure definition.
		228	*/
		229	typedef struct
		230	{
		231	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
		232	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
		233
		234	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
		235
		236	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		237	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		238
		239	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		240
		241	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
		242	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		243
		244	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		245
		246	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		247	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		248
		249	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		250
		251	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		252	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		253
		254	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		255
		256	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
		257	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		258
		259	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		260
		261	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
		262	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		263
		264	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		265
		266	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
		267	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		268
		269	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		270
		271	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
		272	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		273
		274	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		275
		276	} LL_TIM_ENCODER_InitTypeDef;
		277
		278
		279	/**
		280	* @}
		281	*/
		282	#endif /* USE_FULL_LL_DRIVER */
		283
		284	/* Exported constants --------------------------------------------------------*/
		285	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
		286	* @{
		287	*/
		288
		289	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
		290	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
		291	* @{
		292	*/
		293	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
		294	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
		295	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
		296	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
		297	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
		298	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
		299	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
		300	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
		301	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
		302	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
		303	/**
		304	* @}
		305	*/
		306
		307	/** @defgroup TIM_LL_EC_IT IT Defines
		308	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
		309	* @{
		310	*/
		311	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
		312	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
		313	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
		314	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
		315	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
		316	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
		317	/**
		318	* @}
		319	*/
		320
		321	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
		322	* @{
		323	*/
		324	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
		325	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
		326	/**
		327	* @}
		328	*/
		329
		330	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
		331	* @{
		332	*/
		333	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
		334	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
		335	/**
		336	* @}
		337	*/
		338
		339	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
		340	* @{
		341	*/
		342	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
		343	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
		344	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
		345	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
		346	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
		347	/**
		348	* @}
		349	*/
		350
		351	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
		352	* @{
		353	*/
		354	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
		355	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
		356	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
		357	/**
		358	* @}
		359	*/
		360
		361	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
		362	* @{
		363	*/
		364	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
		365	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
		366	/**
		367	* @}
		368	*/
		369
		370
		371	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
		372	* @{
		373	*/
		374	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
		375	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
		376	/**
		377	* @}
		378	*/
		379
		380
		381	/** @defgroup TIM_LL_EC_CHANNEL Channel
		382	* @{
		383	*/
		384	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
		385	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
		386	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
		387	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
		388	/**
		389	* @}
		390	*/
		391
		392	#if defined(USE_FULL_LL_DRIVER)
		393	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
		394	* @{
		395	*/
		396	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
		397	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
		398	/**
		399	* @}
		400	*/
		401	#endif /* USE_FULL_LL_DRIVER */
		402
		403	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
		404	* @{
		405	*/
		406	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
		407	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
		408	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
		409	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
		410	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
		411	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
		412	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
		413	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
		414	/**
		415	* @}
		416	*/
		417
		418	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
		419	* @{
		420	*/
		421	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
		422	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
		423	/**
		424	* @}
		425	*/
		426
		427
		428
		429	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
		430	* @{
		431	*/
		432	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
		433	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
		434	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
		435	/**
		436	* @}
		437	*/
		438
		439	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
		440	* @{
		441	*/
		442	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
		443	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
		444	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
		445	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
		446	/**
		447	* @}
		448	*/
		449
		450	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
		451	* @{
		452	*/
		453	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		454	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
		455	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
		456	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
		457	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
		458	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
		459	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
		460	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
		461	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
		462	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
		463	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
		464	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
		465	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
		466	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
		467	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
		468	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
		469	/**
		470	* @}
		471	*/
		472
		473	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
		474	* @{
		475	*/
		476	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
		477	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
		478	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
		479	/**
		480	* @}
		481	*/
		482
		483	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
		484	* @{
		485	*/
		486	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
		487	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
		488	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
		489	/**
		490	* @}
		491	*/
		492
		493	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
		494	* @{
		495	*/
		496	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
		497	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
		498	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
		499	/**
		500	* @}
		501	*/
		502
		503	/** @defgroup TIM_LL_EC_TRGO Trigger Output
		504	* @{
		505	*/
		506	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
		507	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
		508	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
		509	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
		510	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
		511	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
		512	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
		513	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
		514	/**
		515	* @}
		516	*/
		517
		518
		519	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
		520	* @{
		521	*/
		522	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
		523	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
		524	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
		525	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
		526	/**
		527	* @}
		528	*/
		529
		530	/** @defgroup TIM_LL_EC_TS Trigger Selection
		531	* @{
		532	*/
		533	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
		534	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
		535	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
		536	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
		537	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
		538	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
		539	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
		540	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
		541	/**
		542	* @}
		543	*/
		544
		545	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
		546	* @{
		547	*/
		548	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
		549	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
		550	/**
		551	* @}
		552	*/
		553
		554	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
		555	* @{
		556	*/
		557	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
		558	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
		559	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
		560	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
		561	/**
		562	* @}
		563	*/
		564
		565	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
		566	* @{
		567	*/
		568	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		569	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
		570	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
		571	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
		572	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
		573	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
		574	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
		575	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
		576	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
		577	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
		578	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
		579	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
		580	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
		581	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
		582	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
		583	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
		584	/**
		585	* @}
		586	*/
		587
		588
		589
		590
		591
		592
		593
		594	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
		595	* @{
		596	*/
		597	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
		598	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
		599	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
		600	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
		601	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
		602	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
		603	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
		604	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
		605	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
		606	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
		607	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
		608	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
		609	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
		610	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
		611	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
		612	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
		613	#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_OR register is the DMA base address for DMA burst /
		614	/**
		615	* @}
		616	*/
		617
		618	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
		619	* @{
		620	*/
		621	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
		622	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
		623	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
		624	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
		625	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
		626	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
		627	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
		628	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
		629	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
		630	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
		631	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
		632	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
		633	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
		634	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
		635	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
		636	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
		637	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
		638	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
		639	/**
		640	* @}
		641	*/
		642
		643	/** @defgroup TIM_LL_EC_TIM10_TI1_RMP TIM10 input 1 remapping capability
		644	* @{
		645	*/
		646	#define LL_TIM_TIM10_TI1_RMP_GPIO TIM_OR_RMP_MASK /!< TIM10 channel1 is connected to GPIO /
		647	#define LL_TIM_TIM10_TI1_RMP_LSI (TIM_OR_TI1RMP_0 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to LSI internal clock /
		648	#define LL_TIM_TIM10_TI1_RMP_LSE (TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to LSE internal clock /
		649	#define LL_TIM_TIM10_TI1_RMP_RTC (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to RTC wakeup interrupt signal /
		650	/**
		651	* @}
		652	*/
		653
		654	/** @defgroup TIM_LL_EC_TIM10_ETR_RMP TIM10 ETR remap
		655	* @{
		656	*/
		657	#define LL_TIM_TIM10_ETR_RMP_LSE TIM_OR_RMP_MASK /!< TIM10 ETR input is connected to LSE /
		658	#define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP \| TIM_OR_RMP_MASK) /!< TIM10 ETR input is connected to TIM9 TGO /
		659	/**
		660	* @}
		661	*/
		662
		663	/** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI)
		664	* @{
		665	*/
		666	#define LL_TIM_TIM10_TI1_RMP TIM_OR_RMP_MASK /!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values /
		667	#define LL_TIM_TIM10_TI1_RMP_RI (TIM_OR_TI1_RMP_RI \| TIM_OR_RMP_MASK) /!< TIM10 channel1 is connected to RI /
		668	/**
		669	* @}
		670	*/
		671
		672	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 input 1 remapping capability
		673	* @{
		674	*/
		675	#define LL_TIM_TIM11_TI1_RMP_GPIO TIM_OR_RMP_MASK /!< TIM11 channel1 is connected to GPIO /
		676	#define LL_TIM_TIM11_TI1_RMP_MSI (TIM_OR_TI1RMP_0 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to MSI internal clock /
		677	#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to HSE RTC clock /
		678	#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to GPIO /
		679	/**
		680	* @}
		681	*/
		682
		683	/** @defgroup TIM_LL_EC_TIM11_ETR_RMP TIM11 ETR remap
		684	* @{
		685	*/
		686	#define LL_TIM_TIM11_ETR_RMP_LSE TIM_OR_RMP_MASK /!< TIM11 ETR input is connected to LSE /
		687	#define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP \| TIM_OR_RMP_MASK) /!< TIM11 ETR input is connected to TIM9 TGO clock /
		688	/**
		689	* @}
		690	*/
		691
		692	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI)
		693	* @{
		694	*/
		695	#define LL_TIM_TIM11_TI1_RMP TIM_OR_RMP_MASK /!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values /
		696	#define LL_TIM_TIM11_TI1_RMP_RI (TIM_OR_TI1_RMP_RI \| TIM_OR_RMP_MASK) /!< TIM11 channel1 is connected to RI /
		697	/**
		698	* @}
		699	*/
		700
		701	/** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap
		702	* @{
		703	*/
		704	#define LL_TIM_TIM9_TI1_RMP_GPIO TIM9_OR_RMP_MASK /!< TIM9 channel1 is connected to GPIO /
		705	#define LL_TIM_TIM9_TI1_RMP_LSE (TIM_OR_TI1RMP_0 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to LSE internal clock /
		706	#define LL_TIM_TIM9_TI1_RMP_GPIO1 (TIM_OR_TI1RMP_1 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to GPIO /
		707	#define LL_TIM_TIM9_TI1_RMP_GPIO2 (TIM_OR_TI1RMP_0 \| TIM_OR_TI1RMP_1 \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to GPIO /
		708	/**
		709	* @}
		710	*/
		711
		712	/** @defgroup TIM_LL_EC_TIM9_ITR1_RMP TIM9 ITR1 remap
		713	* @{
		714	*/
		715	#define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO TIM9_OR_RMP_MASK /!< TIM9 channel1 is connected to TIM3 TGO signal /
		716	#define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (TIM9_OR_ITR1_RMP \| TIM9_OR_RMP_MASK) /!< TIM9 channel1 is connected to touch sensing I/O /
		717	/**
		718	* @}
		719	*/
		720
		721	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 internal trigger 1 remap
		722	* @{
		723	*/
		724	#define LL_TIM_TIM2_TIR1_RMP_TIM10_OC TIM9_OR_RMP_MASK /!< TIM2 ITR1 input is connected to TIM10 OC/
		725	#define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (TIM2_OR_ITR1_RMP \| TIM9_OR_RMP_MASK) /!< TIM2 ITR1 input is connected to TIM5 TGO /
		726	/**
		727	* @}
		728	*/
		729
		730	/** @defgroup TIM_LL_EC_TIM3_ITR2_RMP TIM3 internal trigger 2 remap
		731	* @{
		732	*/
		733	#define LL_TIM_TIM3_TIR2_RMP_TIM11_OC TIM9_OR_RMP_MASK /!< TIM3 ITR2 input is connected to TIM11 OC /
		734	#define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (TIM3_OR_ITR2_RMP \| TIM9_OR_RMP_MASK) /!< TIM3 ITR2 input is connected to TIM5 TGO /
		735	/**
		736	* @}
		737	*/
		738
		739
		740	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
		741	* @{
		742	*/
		743	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
		744	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
		745	/**
		746	* @}
		747	*/
		748
		749	/**
		750	* @}
		751	*/
		752
		753	/* Exported macro ------------------------------------------------------------*/
		754	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
		755	* @{
		756	*/
		757
		758	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
		759	* @{
		760	*/
		761	/**
		762	* @brief Write a value in TIM register.
		763	* @param __INSTANCE__ TIM Instance
		764	* @param __REG__ Register to be written
		765	* @param __VALUE__ Value to be written in the register
		766	* @retval None
		767	*/
		768	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
		769
		770	/**
		771	* @brief Read a value in TIM register.
		772	* @param __INSTANCE__ TIM Instance
		773	* @param __REG__ Register to be read
		774	* @retval Register value
		775	*/
		776	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
		777	/**
		778	* @}
		779	*/
		780
		781	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
		782	* @{
		783	*/
		784
		785	/**
		786	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
		787	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
		788	* @param __TIMCLK__ timer input clock frequency (in Hz)
		789	* @param __CNTCLK__ counter clock frequency (in Hz)
		790	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
		791	*/
		792	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
		793	(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
		794
		795	/**
		796	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
		797	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
		798	* @param __TIMCLK__ timer input clock frequency (in Hz)
		799	* @param __PSC__ prescaler
		800	* @param __FREQ__ output signal frequency (in Hz)
		801	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		802	*/
		803	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
		804	((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
		805
		806	/**
		807	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
		808	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
		809	* @param __TIMCLK__ timer input clock frequency (in Hz)
		810	* @param __PSC__ prescaler
		811	* @param __DELAY__ timer output compare active/inactive delay (in us)
		812	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
		813	*/
		814	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
		815	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
		816	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
		817
		818	/**
		819	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
		820	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
		821	* @param __TIMCLK__ timer input clock frequency (in Hz)
		822	* @param __PSC__ prescaler
		823	* @param __DELAY__ timer output compare active/inactive delay (in us)
		824	* @param __PULSE__ pulse duration (in us)
		825	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		826	*/
		827	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
		828	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
		829	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
		830
		831	/**
		832	* @brief HELPER macro retrieving the ratio of the input capture prescaler
		833	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
		834	* @param __ICPSC__ This parameter can be one of the following values:
		835	* @arg @ref LL_TIM_ICPSC_DIV1
		836	* @arg @ref LL_TIM_ICPSC_DIV2
		837	* @arg @ref LL_TIM_ICPSC_DIV4
		838	* @arg @ref LL_TIM_ICPSC_DIV8
		839	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
		840	*/
		841	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
		842	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
		843
		844
		845	/**
		846	* @}
		847	*/
		848
		849
		850	/**
		851	* @}
		852	*/
		853
		854	/* Exported functions --------------------------------------------------------*/
		855	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
		856	* @{
		857	*/
		858
		859	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
		860	* @{
		861	*/
		862	/**
		863	* @brief Enable timer counter.
		864	* @rmtoll CR1 CEN LL_TIM_EnableCounter
		865	* @param TIMx Timer instance
		866	* @retval None
		867	*/
		868	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
		869	{
		870	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
		871	}
		872
		873	/**
		874	* @brief Disable timer counter.
		875	* @rmtoll CR1 CEN LL_TIM_DisableCounter
		876	* @param TIMx Timer instance
		877	* @retval None
		878	*/
		879	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
		880	{
		881	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
		882	}
		883
		884	/**
		885	* @brief Indicates whether the timer counter is enabled.
		886	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
		887	* @param TIMx Timer instance
		888	* @retval State of bit (1 or 0).
		889	*/
		890	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
		891	{
		892	return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
		893	}
		894
		895	/**
		896	* @brief Enable update event generation.
		897	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
		898	* @param TIMx Timer instance
		899	* @retval None
		900	*/
		901	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
		902	{
		903	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
		904	}
		905
		906	/**
		907	* @brief Disable update event generation.
		908	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
		909	* @param TIMx Timer instance
		910	* @retval None
		911	*/
		912	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
		913	{
		914	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
		915	}
		916
		917	/**
		918	* @brief Indicates whether update event generation is enabled.
		919	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
		920	* @param TIMx Timer instance
		921	* @retval Inverted state of bit (0 or 1).
		922	*/
		923	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
		924	{
		925	return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
		926	}
		927
		928	/**
		929	* @brief Set update event source
		930	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
		931	* generate an update interrupt or DMA request if enabled:
		932	* - Counter overflow/underflow
		933	* - Setting the UG bit
		934	* - Update generation through the slave mode controller
		935	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
		936	* overflow/underflow generates an update interrupt or DMA request if enabled.
		937	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
		938	* @param TIMx Timer instance
		939	* @param UpdateSource This parameter can be one of the following values:
		940	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		941	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		942	* @retval None
		943	*/
		944	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
		945	{
		946	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
		947	}
		948
		949	/**
		950	* @brief Get actual event update source
		951	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
		952	* @param TIMx Timer instance
		953	* @retval Returned value can be one of the following values:
		954	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		955	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		956	*/
		957	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
		958	{
		959	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
		960	}
		961
		962	/**
		963	* @brief Set one pulse mode (one shot v.s. repetitive).
		964	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
		965	* @param TIMx Timer instance
		966	* @param OnePulseMode This parameter can be one of the following values:
		967	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		968	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		969	* @retval None
		970	*/
		971	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
		972	{
		973	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
		974	}
		975
		976	/**
		977	* @brief Get actual one pulse mode.
		978	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
		979	* @param TIMx Timer instance
		980	* @retval Returned value can be one of the following values:
		981	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		982	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		983	*/
		984	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
		985	{
		986	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
		987	}
		988
		989	/**
		990	* @brief Set the timer counter counting mode.
		991	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		992	* check whether or not the counter mode selection feature is supported
		993	* by a timer instance.
		994	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		995	* requires a timer reset to avoid unexpected direction
		996	* due to DIR bit readonly in center aligned mode.
		997	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
		998	* CR1 CMS LL_TIM_SetCounterMode
		999	* @param TIMx Timer instance
		1000	* @param CounterMode This parameter can be one of the following values:
		1001	* @arg @ref LL_TIM_COUNTERMODE_UP
		1002	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1003	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1004	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1005	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1006	* @retval None
		1007	*/
		1008	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
		1009	{
		1010	MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR \| TIM_CR1_CMS), CounterMode);
		1011	}
		1012
		1013	/**
		1014	* @brief Get actual counter mode.
		1015	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1016	* check whether or not the counter mode selection feature is supported
		1017	* by a timer instance.
		1018	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
		1019	* CR1 CMS LL_TIM_GetCounterMode
		1020	* @param TIMx Timer instance
		1021	* @retval Returned value can be one of the following values:
		1022	* @arg @ref LL_TIM_COUNTERMODE_UP
		1023	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1024	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1025	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1026	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1027	*/
		1028	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
		1029	{
		1030	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
		1031	}
		1032
		1033	/**
		1034	* @brief Enable auto-reload (ARR) preload.
		1035	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
		1036	* @param TIMx Timer instance
		1037	* @retval None
		1038	*/
		1039	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
		1040	{
		1041	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1042	}
		1043
		1044	/**
		1045	* @brief Disable auto-reload (ARR) preload.
		1046	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
		1047	* @param TIMx Timer instance
		1048	* @retval None
		1049	*/
		1050	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
		1051	{
		1052	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1053	}
		1054
		1055	/**
		1056	* @brief Indicates whether auto-reload (ARR) preload is enabled.
		1057	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
		1058	* @param TIMx Timer instance
		1059	* @retval State of bit (1 or 0).
		1060	*/
		1061	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
		1062	{
		1063	return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
		1064	}
		1065
		1066	/**
		1067	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
		1068	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1069	* whether or not the clock division feature is supported by the timer
		1070	* instance.
		1071	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
		1072	* @param TIMx Timer instance
		1073	* @param ClockDivision This parameter can be one of the following values:
		1074	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1075	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1076	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1077	* @retval None
		1078	*/
		1079	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
		1080	{
		1081	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
		1082	}
		1083
		1084	/**
		1085	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
		1086	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1087	* whether or not the clock division feature is supported by the timer
		1088	* instance.
		1089	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
		1090	* @param TIMx Timer instance
		1091	* @retval Returned value can be one of the following values:
		1092	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1093	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1094	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1095	*/
		1096	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
		1097	{
		1098	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
		1099	}
		1100
		1101	/**
		1102	* @brief Set the counter value.
		1103	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1104	* whether or not a timer instance supports a 32 bits counter.
		1105	* @rmtoll CNT CNT LL_TIM_SetCounter
		1106	* @param TIMx Timer instance
		1107	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
		1108	* @retval None
		1109	*/
		1110	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
		1111	{
		1112	WRITE_REG(TIMx->CNT, Counter);
		1113	}
		1114
		1115	/**
		1116	* @brief Get the counter value.
		1117	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1118	* whether or not a timer instance supports a 32 bits counter.
		1119	* @rmtoll CNT CNT LL_TIM_GetCounter
		1120	* @param TIMx Timer instance
		1121	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
		1122	*/
		1123	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
		1124	{
		1125	return (uint32_t)(READ_REG(TIMx->CNT));
		1126	}
		1127
		1128	/**
		1129	* @brief Get the current direction of the counter
		1130	* @rmtoll CR1 DIR LL_TIM_GetDirection
		1131	* @param TIMx Timer instance
		1132	* @retval Returned value can be one of the following values:
		1133	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
		1134	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
		1135	*/
		1136	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
		1137	{
		1138	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
		1139	}
		1140
		1141	/**
		1142	* @brief Set the prescaler value.
		1143	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
		1144	* @note The prescaler can be changed on the fly as this control register is buffered. The new
		1145	* prescaler ratio is taken into account at the next update event.
		1146	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
		1147	* @rmtoll PSC PSC LL_TIM_SetPrescaler
		1148	* @param TIMx Timer instance
		1149	* @param Prescaler between Min_Data=0 and Max_Data=65535
		1150	* @retval None
		1151	*/
		1152	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
		1153	{
		1154	WRITE_REG(TIMx->PSC, Prescaler);
		1155	}
		1156
		1157	/**
		1158	* @brief Get the prescaler value.
		1159	* @rmtoll PSC PSC LL_TIM_GetPrescaler
		1160	* @param TIMx Timer instance
		1161	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
		1162	*/
		1163	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
		1164	{
		1165	return (uint32_t)(READ_REG(TIMx->PSC));
		1166	}
		1167
		1168	/**
		1169	* @brief Set the auto-reload value.
		1170	* @note The counter is blocked while the auto-reload value is null.
		1171	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1172	* whether or not a timer instance supports a 32 bits counter.
		1173	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
		1174	* @rmtoll ARR ARR LL_TIM_SetAutoReload
		1175	* @param TIMx Timer instance
		1176	* @param AutoReload between Min_Data=0 and Max_Data=65535
		1177	* @retval None
		1178	*/
		1179	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
		1180	{
		1181	WRITE_REG(TIMx->ARR, AutoReload);
		1182	}
		1183
		1184	/**
		1185	* @brief Get the auto-reload value.
		1186	* @rmtoll ARR ARR LL_TIM_GetAutoReload
		1187	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1188	* whether or not a timer instance supports a 32 bits counter.
		1189	* @param TIMx Timer instance
		1190	* @retval Auto-reload value
		1191	*/
		1192	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
		1193	{
		1194	return (uint32_t)(READ_REG(TIMx->ARR));
		1195	}
		1196
		1197	/**
		1198	* @}
		1199	*/
		1200
		1201	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
		1202	* @{
		1203	*/
		1204	/**
		1205	* @brief Set the trigger of the capture/compare DMA request.
		1206	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
		1207	* @param TIMx Timer instance
		1208	* @param DMAReqTrigger This parameter can be one of the following values:
		1209	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1210	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1211	* @retval None
		1212	*/
		1213	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
		1214	{
		1215	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
		1216	}
		1217
		1218	/**
		1219	* @brief Get actual trigger of the capture/compare DMA request.
		1220	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
		1221	* @param TIMx Timer instance
		1222	* @retval Returned value can be one of the following values:
		1223	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1224	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1225	*/
		1226	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
		1227	{
		1228	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
		1229	}
		1230
		1231	/**
		1232	* @brief Enable capture/compare channels.
		1233	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
		1234	* CCER CC2E LL_TIM_CC_EnableChannel\n
		1235	* CCER CC3E LL_TIM_CC_EnableChannel\n
		1236	* CCER CC4E LL_TIM_CC_EnableChannel
		1237	* @param TIMx Timer instance
		1238	* @param Channels This parameter can be a combination of the following values:
		1239	* @arg @ref LL_TIM_CHANNEL_CH1
		1240	* @arg @ref LL_TIM_CHANNEL_CH2
		1241	* @arg @ref LL_TIM_CHANNEL_CH3
		1242	* @arg @ref LL_TIM_CHANNEL_CH4
		1243	* @retval None
		1244	*/
		1245	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1246	{
		1247	SET_BIT(TIMx->CCER, Channels);
		1248	}
		1249
		1250	/**
		1251	* @brief Disable capture/compare channels.
		1252	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
		1253	* CCER CC2E LL_TIM_CC_DisableChannel\n
		1254	* CCER CC3E LL_TIM_CC_DisableChannel\n
		1255	* CCER CC4E LL_TIM_CC_DisableChannel
		1256	* @param TIMx Timer instance
		1257	* @param Channels This parameter can be a combination of the following values:
		1258	* @arg @ref LL_TIM_CHANNEL_CH1
		1259	* @arg @ref LL_TIM_CHANNEL_CH2
		1260	* @arg @ref LL_TIM_CHANNEL_CH3
		1261	* @arg @ref LL_TIM_CHANNEL_CH4
		1262	* @retval None
		1263	*/
		1264	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1265	{
		1266	CLEAR_BIT(TIMx->CCER, Channels);
		1267	}
		1268
		1269	/**
		1270	* @brief Indicate whether channel(s) is(are) enabled.
		1271	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
		1272	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
		1273	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
		1274	* CCER CC4E LL_TIM_CC_IsEnabledChannel
		1275	* @param TIMx Timer instance
		1276	* @param Channels This parameter can be a combination of the following values:
		1277	* @arg @ref LL_TIM_CHANNEL_CH1
		1278	* @arg @ref LL_TIM_CHANNEL_CH2
		1279	* @arg @ref LL_TIM_CHANNEL_CH3
		1280	* @arg @ref LL_TIM_CHANNEL_CH4
		1281	* @retval State of bit (1 or 0).
		1282	*/
		1283	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1284	{
		1285	return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
		1286	}
		1287
		1288	/**
		1289	* @}
		1290	*/
		1291
		1292	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
		1293	* @{
		1294	*/
		1295	/**
		1296	* @brief Configure an output channel.
		1297	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
		1298	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
		1299	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
		1300	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
		1301	* CCER CC1P LL_TIM_OC_ConfigOutput\n
		1302	* CCER CC2P LL_TIM_OC_ConfigOutput\n
		1303	* CCER CC3P LL_TIM_OC_ConfigOutput\n
		1304	* CCER CC4P LL_TIM_OC_ConfigOutput\n
		1305	* @param TIMx Timer instance
		1306	* @param Channel This parameter can be one of the following values:
		1307	* @arg @ref LL_TIM_CHANNEL_CH1
		1308	* @arg @ref LL_TIM_CHANNEL_CH2
		1309	* @arg @ref LL_TIM_CHANNEL_CH3
		1310	* @arg @ref LL_TIM_CHANNEL_CH4
		1311	* @param Configuration This parameter must be a combination of all the following values:
		1312	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
		1313	* @retval None
		1314	*/
		1315	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		1316	{
		1317	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1318	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1319	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
		1320	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
		1321	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
		1322	}
		1323
		1324	/**
		1325	* @brief Define the behavior of the output reference signal OCxREF from which
		1326	* OCx and OCxN (when relevant) are derived.
		1327	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
		1328	* CCMR1 OC2M LL_TIM_OC_SetMode\n
		1329	* CCMR2 OC3M LL_TIM_OC_SetMode\n
		1330	* CCMR2 OC4M LL_TIM_OC_SetMode
		1331	* @param TIMx Timer instance
		1332	* @param Channel This parameter can be one of the following values:
		1333	* @arg @ref LL_TIM_CHANNEL_CH1
		1334	* @arg @ref LL_TIM_CHANNEL_CH2
		1335	* @arg @ref LL_TIM_CHANNEL_CH3
		1336	* @arg @ref LL_TIM_CHANNEL_CH4
		1337	* @param Mode This parameter can be one of the following values:
		1338	* @arg @ref LL_TIM_OCMODE_FROZEN
		1339	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1340	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1341	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1342	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1343	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1344	* @arg @ref LL_TIM_OCMODE_PWM1
		1345	* @arg @ref LL_TIM_OCMODE_PWM2
		1346	* @retval None
		1347	*/
		1348	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
		1349	{
		1350	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1351	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1352	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
		1353	}
		1354
		1355	/**
		1356	* @brief Get the output compare mode of an output channel.
		1357	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
		1358	* CCMR1 OC2M LL_TIM_OC_GetMode\n
		1359	* CCMR2 OC3M LL_TIM_OC_GetMode\n
		1360	* CCMR2 OC4M LL_TIM_OC_GetMode
		1361	* @param TIMx Timer instance
		1362	* @param Channel This parameter can be one of the following values:
		1363	* @arg @ref LL_TIM_CHANNEL_CH1
		1364	* @arg @ref LL_TIM_CHANNEL_CH2
		1365	* @arg @ref LL_TIM_CHANNEL_CH3
		1366	* @arg @ref LL_TIM_CHANNEL_CH4
		1367	* @retval Returned value can be one of the following values:
		1368	* @arg @ref LL_TIM_OCMODE_FROZEN
		1369	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1370	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1371	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1372	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1373	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1374	* @arg @ref LL_TIM_OCMODE_PWM1
		1375	* @arg @ref LL_TIM_OCMODE_PWM2
		1376	*/
		1377	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
		1378	{
		1379	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1380	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1381	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
		1382	}
		1383
		1384	/**
		1385	* @brief Set the polarity of an output channel.
		1386	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
		1387	* CCER CC2P LL_TIM_OC_SetPolarity\n
		1388	* CCER CC3P LL_TIM_OC_SetPolarity\n
		1389	* CCER CC4P LL_TIM_OC_SetPolarity
		1390	* @param TIMx Timer instance
		1391	* @param Channel This parameter can be one of the following values:
		1392	* @arg @ref LL_TIM_CHANNEL_CH1
		1393	* @arg @ref LL_TIM_CHANNEL_CH2
		1394	* @arg @ref LL_TIM_CHANNEL_CH3
		1395	* @arg @ref LL_TIM_CHANNEL_CH4
		1396	* @param Polarity This parameter can be one of the following values:
		1397	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1398	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1399	* @retval None
		1400	*/
		1401	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
		1402	{
		1403	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1404	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
		1405	}
		1406
		1407	/**
		1408	* @brief Get the polarity of an output channel.
		1409	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
		1410	* CCER CC2P LL_TIM_OC_GetPolarity\n
		1411	* CCER CC3P LL_TIM_OC_GetPolarity\n
		1412	* CCER CC4P LL_TIM_OC_GetPolarity
		1413	* @param TIMx Timer instance
		1414	* @param Channel This parameter can be one of the following values:
		1415	* @arg @ref LL_TIM_CHANNEL_CH1
		1416	* @arg @ref LL_TIM_CHANNEL_CH2
		1417	* @arg @ref LL_TIM_CHANNEL_CH3
		1418	* @arg @ref LL_TIM_CHANNEL_CH4
		1419	* @retval Returned value can be one of the following values:
		1420	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1421	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1422	*/
		1423	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		1424	{
		1425	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1426	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
		1427	}
		1428
		1429	/**
		1430	* @brief Enable fast mode for the output channel.
		1431	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
		1432	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
		1433	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
		1434	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
		1435	* CCMR2 OC4FE LL_TIM_OC_EnableFast
		1436	* @param TIMx Timer instance
		1437	* @param Channel This parameter can be one of the following values:
		1438	* @arg @ref LL_TIM_CHANNEL_CH1
		1439	* @arg @ref LL_TIM_CHANNEL_CH2
		1440	* @arg @ref LL_TIM_CHANNEL_CH3
		1441	* @arg @ref LL_TIM_CHANNEL_CH4
		1442	* @retval None
		1443	*/
		1444	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1445	{
		1446	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1447	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1448	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1449
		1450	}
		1451
		1452	/**
		1453	* @brief Disable fast mode for the output channel.
		1454	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
		1455	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
		1456	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
		1457	* CCMR2 OC4FE LL_TIM_OC_DisableFast
		1458	* @param TIMx Timer instance
		1459	* @param Channel This parameter can be one of the following values:
		1460	* @arg @ref LL_TIM_CHANNEL_CH1
		1461	* @arg @ref LL_TIM_CHANNEL_CH2
		1462	* @arg @ref LL_TIM_CHANNEL_CH3
		1463	* @arg @ref LL_TIM_CHANNEL_CH4
		1464	* @retval None
		1465	*/
		1466	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1467	{
		1468	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1469	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1470	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1471
		1472	}
		1473
		1474	/**
		1475	* @brief Indicates whether fast mode is enabled for the output channel.
		1476	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
		1477	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
		1478	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
		1479	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
		1480	* @param TIMx Timer instance
		1481	* @param Channel This parameter can be one of the following values:
		1482	* @arg @ref LL_TIM_CHANNEL_CH1
		1483	* @arg @ref LL_TIM_CHANNEL_CH2
		1484	* @arg @ref LL_TIM_CHANNEL_CH3
		1485	* @arg @ref LL_TIM_CHANNEL_CH4
		1486	* @retval State of bit (1 or 0).
		1487	*/
		1488	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1489	{
		1490	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1491	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1492	uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
		1493	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1494	}
		1495
		1496	/**
		1497	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
		1498	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
		1499	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
		1500	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
		1501	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
		1502	* @param TIMx Timer instance
		1503	* @param Channel This parameter can be one of the following values:
		1504	* @arg @ref LL_TIM_CHANNEL_CH1
		1505	* @arg @ref LL_TIM_CHANNEL_CH2
		1506	* @arg @ref LL_TIM_CHANNEL_CH3
		1507	* @arg @ref LL_TIM_CHANNEL_CH4
		1508	* @retval None
		1509	*/
		1510	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1511	{
		1512	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1513	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1514	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1515	}
		1516
		1517	/**
		1518	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
		1519	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
		1520	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
		1521	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
		1522	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
		1523	* @param TIMx Timer instance
		1524	* @param Channel This parameter can be one of the following values:
		1525	* @arg @ref LL_TIM_CHANNEL_CH1
		1526	* @arg @ref LL_TIM_CHANNEL_CH2
		1527	* @arg @ref LL_TIM_CHANNEL_CH3
		1528	* @arg @ref LL_TIM_CHANNEL_CH4
		1529	* @retval None
		1530	*/
		1531	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1532	{
		1533	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1534	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1535	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1536	}
		1537
		1538	/**
		1539	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
		1540	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
		1541	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
		1542	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
		1543	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
		1544	* @param TIMx Timer instance
		1545	* @param Channel This parameter can be one of the following values:
		1546	* @arg @ref LL_TIM_CHANNEL_CH1
		1547	* @arg @ref LL_TIM_CHANNEL_CH2
		1548	* @arg @ref LL_TIM_CHANNEL_CH3
		1549	* @arg @ref LL_TIM_CHANNEL_CH4
		1550	* @retval State of bit (1 or 0).
		1551	*/
		1552	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1553	{
		1554	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1555	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1556	uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
		1557	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1558	}
		1559
		1560	/**
		1561	* @brief Enable clearing the output channel on an external event.
		1562	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1563	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1564	* or not a timer instance can clear the OCxREF signal on an external event.
		1565	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
		1566	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
		1567	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
		1568	* CCMR2 OC4CE LL_TIM_OC_EnableClear
		1569	* @param TIMx Timer instance
		1570	* @param Channel This parameter can be one of the following values:
		1571	* @arg @ref LL_TIM_CHANNEL_CH1
		1572	* @arg @ref LL_TIM_CHANNEL_CH2
		1573	* @arg @ref LL_TIM_CHANNEL_CH3
		1574	* @arg @ref LL_TIM_CHANNEL_CH4
		1575	* @retval None
		1576	*/
		1577	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1578	{
		1579	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1580	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1581	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1582	}
		1583
		1584	/**
		1585	* @brief Disable clearing the output channel on an external event.
		1586	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1587	* or not a timer instance can clear the OCxREF signal on an external event.
		1588	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
		1589	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
		1590	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
		1591	* CCMR2 OC4CE LL_TIM_OC_DisableClear
		1592	* @param TIMx Timer instance
		1593	* @param Channel This parameter can be one of the following values:
		1594	* @arg @ref LL_TIM_CHANNEL_CH1
		1595	* @arg @ref LL_TIM_CHANNEL_CH2
		1596	* @arg @ref LL_TIM_CHANNEL_CH3
		1597	* @arg @ref LL_TIM_CHANNEL_CH4
		1598	* @retval None
		1599	*/
		1600	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1601	{
		1602	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1603	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1604	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1605	}
		1606
		1607	/**
		1608	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
		1609	* @note This function enables clearing the output channel on an external event.
		1610	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1611	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1612	* or not a timer instance can clear the OCxREF signal on an external event.
		1613	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
		1614	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
		1615	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
		1616	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
		1617	* @param TIMx Timer instance
		1618	* @param Channel This parameter can be one of the following values:
		1619	* @arg @ref LL_TIM_CHANNEL_CH1
		1620	* @arg @ref LL_TIM_CHANNEL_CH2
		1621	* @arg @ref LL_TIM_CHANNEL_CH3
		1622	* @arg @ref LL_TIM_CHANNEL_CH4
		1623	* @retval State of bit (1 or 0).
		1624	*/
		1625	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1626	{
		1627	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1628	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1629	uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
		1630	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1631	}
		1632
		1633	/**
		1634	* @brief Set compare value for output channel 1 (TIMx_CCR1).
		1635	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		1636	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1637	* whether or not a timer instance supports a 32 bits counter.
		1638	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		1639	* output channel 1 is supported by a timer instance.
		1640	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
		1641	* @param TIMx Timer instance
		1642	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1643	* @retval None
		1644	*/
		1645	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1646	{
		1647	WRITE_REG(TIMx->CCR1, CompareValue);
		1648	}
		1649
		1650	/**
		1651	* @brief Set compare value for output channel 2 (TIMx_CCR2).
		1652	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		1653	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1654	* whether or not a timer instance supports a 32 bits counter.
		1655	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		1656	* output channel 2 is supported by a timer instance.
		1657	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
		1658	* @param TIMx Timer instance
		1659	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1660	* @retval None
		1661	*/
		1662	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1663	{
		1664	WRITE_REG(TIMx->CCR2, CompareValue);
		1665	}
		1666
		1667	/**
		1668	* @brief Set compare value for output channel 3 (TIMx_CCR3).
		1669	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		1670	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1671	* whether or not a timer instance supports a 32 bits counter.
		1672	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		1673	* output channel is supported by a timer instance.
		1674	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
		1675	* @param TIMx Timer instance
		1676	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1677	* @retval None
		1678	*/
		1679	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1680	{
		1681	WRITE_REG(TIMx->CCR3, CompareValue);
		1682	}
		1683
		1684	/**
		1685	* @brief Set compare value for output channel 4 (TIMx_CCR4).
		1686	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		1687	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1688	* whether or not a timer instance supports a 32 bits counter.
		1689	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		1690	* output channel 4 is supported by a timer instance.
		1691	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
		1692	* @param TIMx Timer instance
		1693	* @param CompareValue between Min_Data=0 and Max_Data=65535
		1694	* @retval None
		1695	*/
		1696	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
		1697	{
		1698	WRITE_REG(TIMx->CCR4, CompareValue);
		1699	}
		1700
		1701	/**
		1702	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
		1703	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		1704	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1705	* whether or not a timer instance supports a 32 bits counter.
		1706	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		1707	* output channel 1 is supported by a timer instance.
		1708	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
		1709	* @param TIMx Timer instance
		1710	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		1711	*/
		1712	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
		1713	{
		1714	return (uint32_t)(READ_REG(TIMx->CCR1));
		1715	}
		1716
		1717	/**
		1718	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
		1719	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		1720	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1721	* whether or not a timer instance supports a 32 bits counter.
		1722	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		1723	* output channel 2 is supported by a timer instance.
		1724	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
		1725	* @param TIMx Timer instance
		1726	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		1727	*/
		1728	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
		1729	{
		1730	return (uint32_t)(READ_REG(TIMx->CCR2));
		1731	}
		1732
		1733	/**
		1734	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
		1735	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		1736	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1737	* whether or not a timer instance supports a 32 bits counter.
		1738	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		1739	* output channel 3 is supported by a timer instance.
		1740	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
		1741	* @param TIMx Timer instance
		1742	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		1743	*/
		1744	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
		1745	{
		1746	return (uint32_t)(READ_REG(TIMx->CCR3));
		1747	}
		1748
		1749	/**
		1750	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
		1751	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		1752	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1753	* whether or not a timer instance supports a 32 bits counter.
		1754	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		1755	* output channel 4 is supported by a timer instance.
		1756	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
		1757	* @param TIMx Timer instance
		1758	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		1759	*/
		1760	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
		1761	{
		1762	return (uint32_t)(READ_REG(TIMx->CCR4));
		1763	}
		1764
		1765	/**
		1766	* @}
		1767	*/
		1768
		1769	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
		1770	* @{
		1771	*/
		1772	/**
		1773	* @brief Configure input channel.
		1774	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
		1775	* CCMR1 IC1PSC LL_TIM_IC_Config\n
		1776	* CCMR1 IC1F LL_TIM_IC_Config\n
		1777	* CCMR1 CC2S LL_TIM_IC_Config\n
		1778	* CCMR1 IC2PSC LL_TIM_IC_Config\n
		1779	* CCMR1 IC2F LL_TIM_IC_Config\n
		1780	* CCMR2 CC3S LL_TIM_IC_Config\n
		1781	* CCMR2 IC3PSC LL_TIM_IC_Config\n
		1782	* CCMR2 IC3F LL_TIM_IC_Config\n
		1783	* CCMR2 CC4S LL_TIM_IC_Config\n
		1784	* CCMR2 IC4PSC LL_TIM_IC_Config\n
		1785	* CCMR2 IC4F LL_TIM_IC_Config\n
		1786	* CCER CC1P LL_TIM_IC_Config\n
		1787	* CCER CC1NP LL_TIM_IC_Config\n
		1788	* CCER CC2P LL_TIM_IC_Config\n
		1789	* CCER CC2NP LL_TIM_IC_Config\n
		1790	* CCER CC3P LL_TIM_IC_Config\n
		1791	* CCER CC3NP LL_TIM_IC_Config\n
		1792	* CCER CC4P LL_TIM_IC_Config\n
		1793	* CCER CC4NP LL_TIM_IC_Config
		1794	* @param TIMx Timer instance
		1795	* @param Channel This parameter can be one of the following values:
		1796	* @arg @ref LL_TIM_CHANNEL_CH1
		1797	* @arg @ref LL_TIM_CHANNEL_CH2
		1798	* @arg @ref LL_TIM_CHANNEL_CH3
		1799	* @arg @ref LL_TIM_CHANNEL_CH4
		1800	* @param Configuration This parameter must be a combination of all the following values:
		1801	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
		1802	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
		1803	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
		1804	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
		1805	* @retval None
		1806	*/
		1807	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		1808	{
		1809	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1810	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1811	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
		1812	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
		1813	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		1814	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
		1815	}
		1816
		1817	/**
		1818	* @brief Set the active input.
		1819	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
		1820	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
		1821	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
		1822	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
		1823	* @param TIMx Timer instance
		1824	* @param Channel This parameter can be one of the following values:
		1825	* @arg @ref LL_TIM_CHANNEL_CH1
		1826	* @arg @ref LL_TIM_CHANNEL_CH2
		1827	* @arg @ref LL_TIM_CHANNEL_CH3
		1828	* @arg @ref LL_TIM_CHANNEL_CH4
		1829	* @param ICActiveInput This parameter can be one of the following values:
		1830	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		1831	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		1832	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		1833	* @retval None
		1834	*/
		1835	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
		1836	{
		1837	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1838	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1839	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		1840	}
		1841
		1842	/**
		1843	* @brief Get the current active input.
		1844	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
		1845	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
		1846	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
		1847	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
		1848	* @param TIMx Timer instance
		1849	* @param Channel This parameter can be one of the following values:
		1850	* @arg @ref LL_TIM_CHANNEL_CH1
		1851	* @arg @ref LL_TIM_CHANNEL_CH2
		1852	* @arg @ref LL_TIM_CHANNEL_CH3
		1853	* @arg @ref LL_TIM_CHANNEL_CH4
		1854	* @retval Returned value can be one of the following values:
		1855	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		1856	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		1857	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		1858	*/
		1859	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
		1860	{
		1861	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1862	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1863	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		1864	}
		1865
		1866	/**
		1867	* @brief Set the prescaler of input channel.
		1868	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
		1869	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
		1870	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
		1871	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
		1872	* @param TIMx Timer instance
		1873	* @param Channel This parameter can be one of the following values:
		1874	* @arg @ref LL_TIM_CHANNEL_CH1
		1875	* @arg @ref LL_TIM_CHANNEL_CH2
		1876	* @arg @ref LL_TIM_CHANNEL_CH3
		1877	* @arg @ref LL_TIM_CHANNEL_CH4
		1878	* @param ICPrescaler This parameter can be one of the following values:
		1879	* @arg @ref LL_TIM_ICPSC_DIV1
		1880	* @arg @ref LL_TIM_ICPSC_DIV2
		1881	* @arg @ref LL_TIM_ICPSC_DIV4
		1882	* @arg @ref LL_TIM_ICPSC_DIV8
		1883	* @retval None
		1884	*/
		1885	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
		1886	{
		1887	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1888	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1889	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		1890	}
		1891
		1892	/**
		1893	* @brief Get the current prescaler value acting on an input channel.
		1894	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
		1895	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
		1896	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
		1897	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
		1898	* @param TIMx Timer instance
		1899	* @param Channel This parameter can be one of the following values:
		1900	* @arg @ref LL_TIM_CHANNEL_CH1
		1901	* @arg @ref LL_TIM_CHANNEL_CH2
		1902	* @arg @ref LL_TIM_CHANNEL_CH3
		1903	* @arg @ref LL_TIM_CHANNEL_CH4
		1904	* @retval Returned value can be one of the following values:
		1905	* @arg @ref LL_TIM_ICPSC_DIV1
		1906	* @arg @ref LL_TIM_ICPSC_DIV2
		1907	* @arg @ref LL_TIM_ICPSC_DIV4
		1908	* @arg @ref LL_TIM_ICPSC_DIV8
		1909	*/
		1910	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
		1911	{
		1912	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1913	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1914	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		1915	}
		1916
		1917	/**
		1918	* @brief Set the input filter duration.
		1919	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
		1920	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
		1921	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
		1922	* CCMR2 IC4F LL_TIM_IC_SetFilter
		1923	* @param TIMx Timer instance
		1924	* @param Channel This parameter can be one of the following values:
		1925	* @arg @ref LL_TIM_CHANNEL_CH1
		1926	* @arg @ref LL_TIM_CHANNEL_CH2
		1927	* @arg @ref LL_TIM_CHANNEL_CH3
		1928	* @arg @ref LL_TIM_CHANNEL_CH4
		1929	* @param ICFilter This parameter can be one of the following values:
		1930	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		1931	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		1932	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		1933	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		1934	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		1935	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		1936	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		1937	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		1938	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		1939	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		1940	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		1941	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		1942	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		1943	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		1944	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		1945	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		1946	* @retval None
		1947	*/
		1948	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
		1949	{
		1950	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1951	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1952	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		1953	}
		1954
		1955	/**
		1956	* @brief Get the input filter duration.
		1957	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
		1958	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
		1959	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
		1960	* CCMR2 IC4F LL_TIM_IC_GetFilter
		1961	* @param TIMx Timer instance
		1962	* @param Channel This parameter can be one of the following values:
		1963	* @arg @ref LL_TIM_CHANNEL_CH1
		1964	* @arg @ref LL_TIM_CHANNEL_CH2
		1965	* @arg @ref LL_TIM_CHANNEL_CH3
		1966	* @arg @ref LL_TIM_CHANNEL_CH4
		1967	* @retval Returned value can be one of the following values:
		1968	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		1969	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		1970	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		1971	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		1972	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		1973	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		1974	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		1975	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		1976	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		1977	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		1978	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		1979	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		1980	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		1981	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		1982	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		1983	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		1984	*/
		1985	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
		1986	{
		1987	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1988	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1989	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		1990	}
		1991
		1992	/**
		1993	* @brief Set the input channel polarity.
		1994	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
		1995	* CCER CC1NP LL_TIM_IC_SetPolarity\n
		1996	* CCER CC2P LL_TIM_IC_SetPolarity\n
		1997	* CCER CC2NP LL_TIM_IC_SetPolarity\n
		1998	* CCER CC3P LL_TIM_IC_SetPolarity\n
		1999	* CCER CC3NP LL_TIM_IC_SetPolarity\n
		2000	* CCER CC4P LL_TIM_IC_SetPolarity\n
		2001	* CCER CC4NP LL_TIM_IC_SetPolarity
		2002	* @param TIMx Timer instance
		2003	* @param Channel This parameter can be one of the following values:
		2004	* @arg @ref LL_TIM_CHANNEL_CH1
		2005	* @arg @ref LL_TIM_CHANNEL_CH2
		2006	* @arg @ref LL_TIM_CHANNEL_CH3
		2007	* @arg @ref LL_TIM_CHANNEL_CH4
		2008	* @param ICPolarity This parameter can be one of the following values:
		2009	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2010	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2011	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
		2012	* @retval None
		2013	*/
		2014	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
		2015	{
		2016	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2017	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2018	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
		2019	}
		2020
		2021	/**
		2022	* @brief Get the current input channel polarity.
		2023	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
		2024	* CCER CC1NP LL_TIM_IC_GetPolarity\n
		2025	* CCER CC2P LL_TIM_IC_GetPolarity\n
		2026	* CCER CC2NP LL_TIM_IC_GetPolarity\n
		2027	* CCER CC3P LL_TIM_IC_GetPolarity\n
		2028	* CCER CC3NP LL_TIM_IC_GetPolarity\n
		2029	* CCER CC4P LL_TIM_IC_GetPolarity\n
		2030	* CCER CC4NP LL_TIM_IC_GetPolarity
		2031	* @param TIMx Timer instance
		2032	* @param Channel This parameter can be one of the following values:
		2033	* @arg @ref LL_TIM_CHANNEL_CH1
		2034	* @arg @ref LL_TIM_CHANNEL_CH2
		2035	* @arg @ref LL_TIM_CHANNEL_CH3
		2036	* @arg @ref LL_TIM_CHANNEL_CH4
		2037	* @retval Returned value can be one of the following values:
		2038	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2039	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2040	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
		2041	*/
		2042	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		2043	{
		2044	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2045	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
		2046	SHIFT_TAB_CCxP[iChannel]);
		2047	}
		2048
		2049	/**
		2050	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
		2051	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2052	* a timer instance provides an XOR input.
		2053	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
		2054	* @param TIMx Timer instance
		2055	* @retval None
		2056	*/
		2057	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
		2058	{
		2059	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2060	}
		2061
		2062	/**
		2063	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
		2064	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2065	* a timer instance provides an XOR input.
		2066	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
		2067	* @param TIMx Timer instance
		2068	* @retval None
		2069	*/
		2070	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
		2071	{
		2072	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2073	}
		2074
		2075	/**
		2076	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
		2077	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2078	* a timer instance provides an XOR input.
		2079	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
		2080	* @param TIMx Timer instance
		2081	* @retval State of bit (1 or 0).
		2082	*/
		2083	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
		2084	{
		2085	return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
		2086	}
		2087
		2088	/**
		2089	* @brief Get captured value for input channel 1.
		2090	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2091	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2092	* whether or not a timer instance supports a 32 bits counter.
		2093	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2094	* input channel 1 is supported by a timer instance.
		2095	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
		2096	* @param TIMx Timer instance
		2097	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2098	*/
		2099	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
		2100	{
		2101	return (uint32_t)(READ_REG(TIMx->CCR1));
		2102	}
		2103
		2104	/**
		2105	* @brief Get captured value for input channel 2.
		2106	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2107	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2108	* whether or not a timer instance supports a 32 bits counter.
		2109	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2110	* input channel 2 is supported by a timer instance.
		2111	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
		2112	* @param TIMx Timer instance
		2113	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2114	*/
		2115	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
		2116	{
		2117	return (uint32_t)(READ_REG(TIMx->CCR2));
		2118	}
		2119
		2120	/**
		2121	* @brief Get captured value for input channel 3.
		2122	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2123	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2124	* whether or not a timer instance supports a 32 bits counter.
		2125	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2126	* input channel 3 is supported by a timer instance.
		2127	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
		2128	* @param TIMx Timer instance
		2129	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2130	*/
		2131	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
		2132	{
		2133	return (uint32_t)(READ_REG(TIMx->CCR3));
		2134	}
		2135
		2136	/**
		2137	* @brief Get captured value for input channel 4.
		2138	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2139	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2140	* whether or not a timer instance supports a 32 bits counter.
		2141	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2142	* input channel 4 is supported by a timer instance.
		2143	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
		2144	* @param TIMx Timer instance
		2145	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2146	*/
		2147	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
		2148	{
		2149	return (uint32_t)(READ_REG(TIMx->CCR4));
		2150	}
		2151
		2152	/**
		2153	* @}
		2154	*/
		2155
		2156	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
		2157	* @{
		2158	*/
		2159	/**
		2160	* @brief Enable external clock mode 2.
		2161	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
		2162	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2163	* whether or not a timer instance supports external clock mode2.
		2164	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
		2165	* @param TIMx Timer instance
		2166	* @retval None
		2167	*/
		2168	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
		2169	{
		2170	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2171	}
		2172
		2173	/**
		2174	* @brief Disable external clock mode 2.
		2175	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2176	* whether or not a timer instance supports external clock mode2.
		2177	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
		2178	* @param TIMx Timer instance
		2179	* @retval None
		2180	*/
		2181	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
		2182	{
		2183	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2184	}
		2185
		2186	/**
		2187	* @brief Indicate whether external clock mode 2 is enabled.
		2188	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2189	* whether or not a timer instance supports external clock mode2.
		2190	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
		2191	* @param TIMx Timer instance
		2192	* @retval State of bit (1 or 0).
		2193	*/
		2194	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
		2195	{
		2196	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
		2197	}
		2198
		2199	/**
		2200	* @brief Set the clock source of the counter clock.
		2201	* @note when selected clock source is external clock mode 1, the timer input
		2202	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
		2203	* function. This timer input must be configured by calling
		2204	* the @ref LL_TIM_IC_Config() function.
		2205	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
		2206	* whether or not a timer instance supports external clock mode1.
		2207	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2208	* whether or not a timer instance supports external clock mode2.
		2209	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
		2210	* SMCR ECE LL_TIM_SetClockSource
		2211	* @param TIMx Timer instance
		2212	* @param ClockSource This parameter can be one of the following values:
		2213	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
		2214	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
		2215	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
		2216	* @retval None
		2217	*/
		2218	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
		2219	{
		2220	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
		2221	}
		2222
		2223	/**
		2224	* @brief Set the encoder interface mode.
		2225	* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
		2226	* whether or not a timer instance supports the encoder mode.
		2227	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
		2228	* @param TIMx Timer instance
		2229	* @param EncoderMode This parameter can be one of the following values:
		2230	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
		2231	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
		2232	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
		2233	* @retval None
		2234	*/
		2235	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
		2236	{
		2237	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
		2238	}
		2239
		2240	/**
		2241	* @}
		2242	*/
		2243
		2244	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
		2245	* @{
		2246	*/
		2247	/**
		2248	* @brief Set the trigger output (TRGO) used for timer synchronization .
		2249	* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
		2250	* whether or not a timer instance can operate as a master timer.
		2251	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
		2252	* @param TIMx Timer instance
		2253	* @param TimerSynchronization This parameter can be one of the following values:
		2254	* @arg @ref LL_TIM_TRGO_RESET
		2255	* @arg @ref LL_TIM_TRGO_ENABLE
		2256	* @arg @ref LL_TIM_TRGO_UPDATE
		2257	* @arg @ref LL_TIM_TRGO_CC1IF
		2258	* @arg @ref LL_TIM_TRGO_OC1REF
		2259	* @arg @ref LL_TIM_TRGO_OC2REF
		2260	* @arg @ref LL_TIM_TRGO_OC3REF
		2261	* @arg @ref LL_TIM_TRGO_OC4REF
		2262	* @retval None
		2263	*/
		2264	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
		2265	{
		2266	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
		2267	}
		2268
		2269	/**
		2270	* @brief Set the synchronization mode of a slave timer.
		2271	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2272	* a timer instance can operate as a slave timer.
		2273	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
		2274	* @param TIMx Timer instance
		2275	* @param SlaveMode This parameter can be one of the following values:
		2276	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
		2277	* @arg @ref LL_TIM_SLAVEMODE_RESET
		2278	* @arg @ref LL_TIM_SLAVEMODE_GATED
		2279	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
		2280	* @retval None
		2281	*/
		2282	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
		2283	{
		2284	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
		2285	}
		2286
		2287	/**
		2288	* @brief Set the selects the trigger input to be used to synchronize the counter.
		2289	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2290	* a timer instance can operate as a slave timer.
		2291	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
		2292	* @param TIMx Timer instance
		2293	* @param TriggerInput This parameter can be one of the following values:
		2294	* @arg @ref LL_TIM_TS_ITR0
		2295	* @arg @ref LL_TIM_TS_ITR1
		2296	* @arg @ref LL_TIM_TS_ITR2
		2297	* @arg @ref LL_TIM_TS_ITR3
		2298	* @arg @ref LL_TIM_TS_TI1F_ED
		2299	* @arg @ref LL_TIM_TS_TI1FP1
		2300	* @arg @ref LL_TIM_TS_TI2FP2
		2301	* @arg @ref LL_TIM_TS_ETRF
		2302	* @retval None
		2303	*/
		2304	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
		2305	{
		2306	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
		2307	}
		2308
		2309	/**
		2310	* @brief Enable the Master/Slave mode.
		2311	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2312	* a timer instance can operate as a slave timer.
		2313	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
		2314	* @param TIMx Timer instance
		2315	* @retval None
		2316	*/
		2317	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
		2318	{
		2319	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2320	}
		2321
		2322	/**
		2323	* @brief Disable the Master/Slave mode.
		2324	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2325	* a timer instance can operate as a slave timer.
		2326	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
		2327	* @param TIMx Timer instance
		2328	* @retval None
		2329	*/
		2330	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
		2331	{
		2332	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2333	}
		2334
		2335	/**
		2336	* @brief Indicates whether the Master/Slave mode is enabled.
		2337	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2338	* a timer instance can operate as a slave timer.
		2339	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
		2340	* @param TIMx Timer instance
		2341	* @retval State of bit (1 or 0).
		2342	*/
		2343	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
		2344	{
		2345	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
		2346	}
		2347
		2348	/**
		2349	* @brief Configure the external trigger (ETR) input.
		2350	* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
		2351	* a timer instance provides an external trigger input.
		2352	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
		2353	* SMCR ETPS LL_TIM_ConfigETR\n
		2354	* SMCR ETF LL_TIM_ConfigETR
		2355	* @param TIMx Timer instance
		2356	* @param ETRPolarity This parameter can be one of the following values:
		2357	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
		2358	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
		2359	* @param ETRPrescaler This parameter can be one of the following values:
		2360	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
		2361	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
		2362	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
		2363	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
		2364	* @param ETRFilter This parameter can be one of the following values:
		2365	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
		2366	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
		2367	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
		2368	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
		2369	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
		2370	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
		2371	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
		2372	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
		2373	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
		2374	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
		2375	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
		2376	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
		2377	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
		2378	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
		2379	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
		2380	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
		2381	* @retval None
		2382	*/
		2383	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
		2384	uint32_t ETRFilter)
		2385	{
		2386	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
		2387	}
		2388
		2389	/**
		2390	* @}
		2391	*/
		2392
		2393	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
		2394	* @{
		2395	*/
		2396	/**
		2397	* @brief Configures the timer DMA burst feature.
		2398	* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
		2399	* not a timer instance supports the DMA burst mode.
		2400	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
		2401	* DCR DBA LL_TIM_ConfigDMABurst
		2402	* @param TIMx Timer instance
		2403	* @param DMABurstBaseAddress This parameter can be one of the following values:
		2404	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
		2405	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
		2406	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
		2407	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
		2408	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
		2409	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
		2410	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
		2411	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
		2412	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
		2413	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
		2414	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
		2415	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
		2416	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
		2417	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
		2418	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
		2419	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
		2420	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
		2421	* @param DMABurstLength This parameter can be one of the following values:
		2422	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
		2423	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
		2424	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
		2425	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
		2426	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
		2427	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
		2428	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
		2429	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
		2430	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
		2431	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
		2432	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
		2433	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
		2434	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
		2435	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
		2436	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
		2437	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
		2438	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
		2439	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
		2440	* @retval None
		2441	*/
		2442	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
		2443	{
		2444	MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL \| TIM_DCR_DBA), (DMABurstBaseAddress \| DMABurstLength));
		2445	}
		2446
		2447	/**
		2448	* @}
		2449	*/
		2450
		2451	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
		2452	* @{
		2453	*/
		2454	/**
		2455	* @brief Remap TIM inputs (input channel, internal/external triggers).
		2456	* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
		2457	* a some timer inputs can be remapped.
		2458	* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
		2459	* TIM3_OR ITR2_RMP LL_TIM_SetRemap\n
		2460	* TIM9_OR TI1_RMP LL_TIM_SetRemap\n
		2461	* TIM9_OR ITR1_RMP LL_TIM_SetRemap\n
		2462	* TIM10_OR TI1_RMP LL_TIM_SetRemap\n
		2463	* TIM10_OR ETR_RMP LL_TIM_SetRemap\n
		2464	* TIM10_OR TI1_RMP_RI LL_TIM_SetRemap\n
		2465	* TIM11_OR TI1_RMP LL_TIM_SetRemap\n
		2466	* TIM11_OR ETR_RMP LL_TIM_SetRemap\n
		2467	* TIM11_OR TI1_RMP_RI LL_TIM_SetRemap
		2468	* @param TIMx Timer instance
		2469	* @param Remap Remap params depends on the TIMx. Description available only
		2470	* in CHM version of the User Manual (not in .pdf).
		2471	* Otherwise see Reference Manual description of OR registers.
		2472	*
		2473	* Below description summarizes "Timer Instance" and "Remap" param combinations:
		2474	*
		2475	* TIM2: any combination of ITR1_RMP where
		2476	*
		2477	* . . ITR1_RMP can be one of the following values
		2478	* @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM10_OC (**)
		2479	* @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM5_TGO (**)
		2480	*
		2481	* TIM3: any combination of ITR2_RMP where
		2482	*
		2483	* . . ITR2_RMP can be one of the following values
		2484	* @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM11_OC (**)
		2485	* @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM5_TGO (**)
		2486	*
		2487	* TIM9: any combination of TI1_RMP, ITR1_RMP where
		2488	*
		2489	* . . TI1_RMP can be one of the following values
		2490	* @arg @ref LL_TIM_TIM9_TI1_RMP_LSE
		2491	* @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
		2492	*
		2493	* . . ITR1_RMP can be one of the following values
		2494	* @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TGO (*)
		2495	* @arg @ref LL_TIM_TIM9_ITR1_RMP_TOUCH_IO (*)
		2496	*
		2497	*
		2498	* TIM10: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
		2499	*
		2500	* . . TI1_RMP can be one of the following values
		2501	* @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO
		2502	* @arg @ref LL_TIM_TIM10_TI1_RMP_LSI
		2503	* @arg @ref LL_TIM_TIM10_TI1_RMP_LSE
		2504	* @arg @ref LL_TIM_TIM10_TI1_RMP_RTC
		2505	*
		2506	* . . ETR_RMP can be one of the following values
		2507	* @arg @ref LL_TIM_TIM10_ETR_RMP_TIM9_TGO (*)
		2508	*
		2509	* . . TI1_RMP_RI can be one of the following values
		2510	* @arg @ref LL_TIM_TIM10_TI1_RMP_RI (*)
		2511	*
		2512	*
		2513	* TIM11: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI where
		2514	*
		2515	* . . TI1_RMP can be one of the following values
		2516	* @arg @ref LL_TIM_TIM11_TI1_RMP_MSI
		2517	* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
		2518	* @arg @ref LL_TIM_TIM11_TI1_RMP
		2519	*
		2520	* . . ETR_RMP can be one of the following values
		2521	* @arg @ref LL_TIM_TIM11_ETR_RMP_TIM9_TGO (*)
		2522	*
		2523	* . . TI1_RMP_RI can be one of the following values
		2524	* @arg @ref LL_TIM_TIM11_TI1_RMP_RI (*)
		2525	*
		2526	* (*) value not available in all devices categories
		2527	* (**) register not available in all devices categories
		2528	*
		2529	* @note Option registers are available only for cat.3, cat.4 and cat.5 devices
		2530	* @retval None
		2531	*/
		2532	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
		2533	{
		2534	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
		2535	}
		2536
		2537	/**
		2538	* @}
		2539	*/
		2540
		2541	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
		2542	* @{
		2543	*/
		2544	/**
		2545	* @brief Set the OCREF clear input source
		2546	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
		2547	* @note This function can only be used in Output compare and PWM modes.
		2548	* @note the ETR signal can be connected to the output of a comparator to be used for current handling
		2549	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
		2550	* @param TIMx Timer instance
		2551	* @param OCRefClearInputSource This parameter can be one of the following values:
		2552	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
		2553	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
		2554	* @retval None
		2555	*/
		2556	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
		2557	{
		2558	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
		2559	}
		2560	/**
		2561	* @}
		2562	*/
		2563
		2564	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
		2565	* @{
		2566	*/
		2567	/**
		2568	* @brief Clear the update interrupt flag (UIF).
		2569	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
		2570	* @param TIMx Timer instance
		2571	* @retval None
		2572	*/
		2573	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
		2574	{
		2575	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
		2576	}
		2577
		2578	/**
		2579	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
		2580	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
		2581	* @param TIMx Timer instance
		2582	* @retval State of bit (1 or 0).
		2583	*/
		2584	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
		2585	{
		2586	return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
		2587	}
		2588
		2589	/**
		2590	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
		2591	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
		2592	* @param TIMx Timer instance
		2593	* @retval None
		2594	*/
		2595	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
		2596	{
		2597	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
		2598	}
		2599
		2600	/**
		2601	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
		2602	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
		2603	* @param TIMx Timer instance
		2604	* @retval State of bit (1 or 0).
		2605	*/
		2606	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
		2607	{
		2608	return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
		2609	}
		2610
		2611	/**
		2612	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
		2613	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
		2614	* @param TIMx Timer instance
		2615	* @retval None
		2616	*/
		2617	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
		2618	{
		2619	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
		2620	}
		2621
		2622	/**
		2623	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
		2624	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
		2625	* @param TIMx Timer instance
		2626	* @retval State of bit (1 or 0).
		2627	*/
		2628	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
		2629	{
		2630	return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
		2631	}
		2632
		2633	/**
		2634	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
		2635	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
		2636	* @param TIMx Timer instance
		2637	* @retval None
		2638	*/
		2639	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
		2640	{
		2641	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
		2642	}
		2643
		2644	/**
		2645	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
		2646	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
		2647	* @param TIMx Timer instance
		2648	* @retval State of bit (1 or 0).
		2649	*/
		2650	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
		2651	{
		2652	return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
		2653	}
		2654
		2655	/**
		2656	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
		2657	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
		2658	* @param TIMx Timer instance
		2659	* @retval None
		2660	*/
		2661	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
		2662	{
		2663	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
		2664	}
		2665
		2666	/**
		2667	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
		2668	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
		2669	* @param TIMx Timer instance
		2670	* @retval State of bit (1 or 0).
		2671	*/
		2672	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
		2673	{
		2674	return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
		2675	}
		2676
		2677	/**
		2678	* @brief Clear the trigger interrupt flag (TIF).
		2679	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
		2680	* @param TIMx Timer instance
		2681	* @retval None
		2682	*/
		2683	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
		2684	{
		2685	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
		2686	}
		2687
		2688	/**
		2689	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
		2690	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
		2691	* @param TIMx Timer instance
		2692	* @retval State of bit (1 or 0).
		2693	*/
		2694	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
		2695	{
		2696	return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
		2697	}
		2698
		2699	/**
		2700	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
		2701	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
		2702	* @param TIMx Timer instance
		2703	* @retval None
		2704	*/
		2705	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
		2706	{
		2707	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
		2708	}
		2709
		2710	/**
		2711	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
		2712	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
		2713	* @param TIMx Timer instance
		2714	* @retval State of bit (1 or 0).
		2715	*/
		2716	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
		2717	{
		2718	return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
		2719	}
		2720
		2721	/**
		2722	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
		2723	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
		2724	* @param TIMx Timer instance
		2725	* @retval None
		2726	*/
		2727	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
		2728	{
		2729	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
		2730	}
		2731
		2732	/**
		2733	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
		2734	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
		2735	* @param TIMx Timer instance
		2736	* @retval State of bit (1 or 0).
		2737	*/
		2738	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
		2739	{
		2740	return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
		2741	}
		2742
		2743	/**
		2744	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
		2745	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
		2746	* @param TIMx Timer instance
		2747	* @retval None
		2748	*/
		2749	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
		2750	{
		2751	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
		2752	}
		2753
		2754	/**
		2755	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
		2756	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
		2757	* @param TIMx Timer instance
		2758	* @retval State of bit (1 or 0).
		2759	*/
		2760	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
		2761	{
		2762	return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
		2763	}
		2764
		2765	/**
		2766	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
		2767	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
		2768	* @param TIMx Timer instance
		2769	* @retval None
		2770	*/
		2771	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
		2772	{
		2773	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
		2774	}
		2775
		2776	/**
		2777	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
		2778	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
		2779	* @param TIMx Timer instance
		2780	* @retval State of bit (1 or 0).
		2781	*/
		2782	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
		2783	{
		2784	return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
		2785	}
		2786
		2787	/**
		2788	* @}
		2789	*/
		2790
		2791	/** @defgroup TIM_LL_EF_IT_Management IT-Management
		2792	* @{
		2793	*/
		2794	/**
		2795	* @brief Enable update interrupt (UIE).
		2796	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
		2797	* @param TIMx Timer instance
		2798	* @retval None
		2799	*/
		2800	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
		2801	{
		2802	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
		2803	}
		2804
		2805	/**
		2806	* @brief Disable update interrupt (UIE).
		2807	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
		2808	* @param TIMx Timer instance
		2809	* @retval None
		2810	*/
		2811	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
		2812	{
		2813	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
		2814	}
		2815
		2816	/**
		2817	* @brief Indicates whether the update interrupt (UIE) is enabled.
		2818	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
		2819	* @param TIMx Timer instance
		2820	* @retval State of bit (1 or 0).
		2821	*/
		2822	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
		2823	{
		2824	return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
		2825	}
		2826
		2827	/**
		2828	* @brief Enable capture/compare 1 interrupt (CC1IE).
		2829	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
		2830	* @param TIMx Timer instance
		2831	* @retval None
		2832	*/
		2833	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
		2834	{
		2835	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		2836	}
		2837
		2838	/**
		2839	* @brief Disable capture/compare 1 interrupt (CC1IE).
		2840	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
		2841	* @param TIMx Timer instance
		2842	* @retval None
		2843	*/
		2844	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
		2845	{
		2846	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		2847	}
		2848
		2849	/**
		2850	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
		2851	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
		2852	* @param TIMx Timer instance
		2853	* @retval State of bit (1 or 0).
		2854	*/
		2855	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
		2856	{
		2857	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
		2858	}
		2859
		2860	/**
		2861	* @brief Enable capture/compare 2 interrupt (CC2IE).
		2862	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
		2863	* @param TIMx Timer instance
		2864	* @retval None
		2865	*/
		2866	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
		2867	{
		2868	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		2869	}
		2870
		2871	/**
		2872	* @brief Disable capture/compare 2 interrupt (CC2IE).
		2873	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
		2874	* @param TIMx Timer instance
		2875	* @retval None
		2876	*/
		2877	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
		2878	{
		2879	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		2880	}
		2881
		2882	/**
		2883	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
		2884	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
		2885	* @param TIMx Timer instance
		2886	* @retval State of bit (1 or 0).
		2887	*/
		2888	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
		2889	{
		2890	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
		2891	}
		2892
		2893	/**
		2894	* @brief Enable capture/compare 3 interrupt (CC3IE).
		2895	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
		2896	* @param TIMx Timer instance
		2897	* @retval None
		2898	*/
		2899	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
		2900	{
		2901	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		2902	}
		2903
		2904	/**
		2905	* @brief Disable capture/compare 3 interrupt (CC3IE).
		2906	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
		2907	* @param TIMx Timer instance
		2908	* @retval None
		2909	*/
		2910	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
		2911	{
		2912	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		2913	}
		2914
		2915	/**
		2916	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
		2917	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
		2918	* @param TIMx Timer instance
		2919	* @retval State of bit (1 or 0).
		2920	*/
		2921	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
		2922	{
		2923	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
		2924	}
		2925
		2926	/**
		2927	* @brief Enable capture/compare 4 interrupt (CC4IE).
		2928	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
		2929	* @param TIMx Timer instance
		2930	* @retval None
		2931	*/
		2932	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
		2933	{
		2934	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		2935	}
		2936
		2937	/**
		2938	* @brief Disable capture/compare 4 interrupt (CC4IE).
		2939	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
		2940	* @param TIMx Timer instance
		2941	* @retval None
		2942	*/
		2943	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
		2944	{
		2945	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		2946	}
		2947
		2948	/**
		2949	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
		2950	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
		2951	* @param TIMx Timer instance
		2952	* @retval State of bit (1 or 0).
		2953	*/
		2954	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
		2955	{
		2956	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
		2957	}
		2958
		2959	/**
		2960	* @brief Enable trigger interrupt (TIE).
		2961	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
		2962	* @param TIMx Timer instance
		2963	* @retval None
		2964	*/
		2965	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
		2966	{
		2967	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
		2968	}
		2969
		2970	/**
		2971	* @brief Disable trigger interrupt (TIE).
		2972	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
		2973	* @param TIMx Timer instance
		2974	* @retval None
		2975	*/
		2976	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
		2977	{
		2978	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
		2979	}
		2980
		2981	/**
		2982	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
		2983	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
		2984	* @param TIMx Timer instance
		2985	* @retval State of bit (1 or 0).
		2986	*/
		2987	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
		2988	{
		2989	return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
		2990	}
		2991
		2992	/**
		2993	* @}
		2994	*/
		2995
		2996	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
		2997	* @{
		2998	*/
		2999	/**
		3000	* @brief Enable update DMA request (UDE).
		3001	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
		3002	* @param TIMx Timer instance
		3003	* @retval None
		3004	*/
		3005	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3006	{
		3007	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
		3008	}
		3009
		3010	/**
		3011	* @brief Disable update DMA request (UDE).
		3012	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
		3013	* @param TIMx Timer instance
		3014	* @retval None
		3015	*/
		3016	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3017	{
		3018	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
		3019	}
		3020
		3021	/**
		3022	* @brief Indicates whether the update DMA request (UDE) is enabled.
		3023	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
		3024	* @param TIMx Timer instance
		3025	* @retval State of bit (1 or 0).
		3026	*/
		3027	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3028	{
		3029	return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
		3030	}
		3031
		3032	/**
		3033	* @brief Enable capture/compare 1 DMA request (CC1DE).
		3034	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
		3035	* @param TIMx Timer instance
		3036	* @retval None
		3037	*/
		3038	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
		3039	{
		3040	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3041	}
		3042
		3043	/**
		3044	* @brief Disable capture/compare 1 DMA request (CC1DE).
		3045	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
		3046	* @param TIMx Timer instance
		3047	* @retval None
		3048	*/
		3049	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
		3050	{
		3051	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3052	}
		3053
		3054	/**
		3055	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
		3056	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
		3057	* @param TIMx Timer instance
		3058	* @retval State of bit (1 or 0).
		3059	*/
		3060	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
		3061	{
		3062	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
		3063	}
		3064
		3065	/**
		3066	* @brief Enable capture/compare 2 DMA request (CC2DE).
		3067	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
		3068	* @param TIMx Timer instance
		3069	* @retval None
		3070	*/
		3071	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
		3072	{
		3073	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3074	}
		3075
		3076	/**
		3077	* @brief Disable capture/compare 2 DMA request (CC2DE).
		3078	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
		3079	* @param TIMx Timer instance
		3080	* @retval None
		3081	*/
		3082	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
		3083	{
		3084	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3085	}
		3086
		3087	/**
		3088	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
		3089	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
		3090	* @param TIMx Timer instance
		3091	* @retval State of bit (1 or 0).
		3092	*/
		3093	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
		3094	{
		3095	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
		3096	}
		3097
		3098	/**
		3099	* @brief Enable capture/compare 3 DMA request (CC3DE).
		3100	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
		3101	* @param TIMx Timer instance
		3102	* @retval None
		3103	*/
		3104	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
		3105	{
		3106	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3107	}
		3108
		3109	/**
		3110	* @brief Disable capture/compare 3 DMA request (CC3DE).
		3111	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
		3112	* @param TIMx Timer instance
		3113	* @retval None
		3114	*/
		3115	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
		3116	{
		3117	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3118	}
		3119
		3120	/**
		3121	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
		3122	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
		3123	* @param TIMx Timer instance
		3124	* @retval State of bit (1 or 0).
		3125	*/
		3126	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
		3127	{
		3128	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
		3129	}
		3130
		3131	/**
		3132	* @brief Enable capture/compare 4 DMA request (CC4DE).
		3133	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
		3134	* @param TIMx Timer instance
		3135	* @retval None
		3136	*/
		3137	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
		3138	{
		3139	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3140	}
		3141
		3142	/**
		3143	* @brief Disable capture/compare 4 DMA request (CC4DE).
		3144	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
		3145	* @param TIMx Timer instance
		3146	* @retval None
		3147	*/
		3148	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
		3149	{
		3150	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3151	}
		3152
		3153	/**
		3154	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
		3155	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
		3156	* @param TIMx Timer instance
		3157	* @retval State of bit (1 or 0).
		3158	*/
		3159	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
		3160	{
		3161	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
		3162	}
		3163
		3164	/**
		3165	* @brief Enable trigger interrupt (TDE).
		3166	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
		3167	* @param TIMx Timer instance
		3168	* @retval None
		3169	*/
		3170	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3171	{
		3172	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
		3173	}
		3174
		3175	/**
		3176	* @brief Disable trigger interrupt (TDE).
		3177	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
		3178	* @param TIMx Timer instance
		3179	* @retval None
		3180	*/
		3181	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3182	{
		3183	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
		3184	}
		3185
		3186	/**
		3187	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
		3188	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
		3189	* @param TIMx Timer instance
		3190	* @retval State of bit (1 or 0).
		3191	*/
		3192	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
		3193	{
		3194	return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
		3195	}
		3196
		3197	/**
		3198	* @}
		3199	*/
		3200
		3201	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
		3202	* @{
		3203	*/
		3204	/**
		3205	* @brief Generate an update event.
		3206	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
		3207	* @param TIMx Timer instance
		3208	* @retval None
		3209	*/
		3210	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
		3211	{
		3212	SET_BIT(TIMx->EGR, TIM_EGR_UG);
		3213	}
		3214
		3215	/**
		3216	* @brief Generate Capture/Compare 1 event.
		3217	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
		3218	* @param TIMx Timer instance
		3219	* @retval None
		3220	*/
		3221	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
		3222	{
		3223	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
		3224	}
		3225
		3226	/**
		3227	* @brief Generate Capture/Compare 2 event.
		3228	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
		3229	* @param TIMx Timer instance
		3230	* @retval None
		3231	*/
		3232	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
		3233	{
		3234	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
		3235	}
		3236
		3237	/**
		3238	* @brief Generate Capture/Compare 3 event.
		3239	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
		3240	* @param TIMx Timer instance
		3241	* @retval None
		3242	*/
		3243	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
		3244	{
		3245	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
		3246	}
		3247
		3248	/**
		3249	* @brief Generate Capture/Compare 4 event.
		3250	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
		3251	* @param TIMx Timer instance
		3252	* @retval None
		3253	*/
		3254	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
		3255	{
		3256	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
		3257	}
		3258
		3259	/**
		3260	* @brief Generate trigger event.
		3261	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
		3262	* @param TIMx Timer instance
		3263	* @retval None
		3264	*/
		3265	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
		3266	{
		3267	SET_BIT(TIMx->EGR, TIM_EGR_TG);
		3268	}
		3269
		3270	/**
		3271	* @}
		3272	*/
		3273
		3274	#if defined(USE_FULL_LL_DRIVER)
		3275	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
		3276	* @{
		3277	*/
		3278
		3279	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
		3280	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
		3281	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
		3282	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
		3283	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
		3284	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
		3285	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
		3286	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
		3287	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
		3288	/**
		3289	* @}
		3290	*/
		3291	#endif /* USE_FULL_LL_DRIVER */
		3292
		3293	/**
		3294	* @}
		3295	*/
		3296
		3297	/**
		3298	* @}
		3299	*/
		3300
		3301	#endif /* TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM9 \|\| TIM10 \|\| TIM11 TIM6 \|\| TIM7 */
		3302
		3303	/**
		3304	* @}
		3305	*/
		3306
		3307	#ifdef __cplusplus
		3308	}
		3309	#endif
		3310
		3311	#endif /* __STM32L1xx_LL_TIM_H */
		3312	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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