WebSVN – DashDisplay – Blame – /branches/Dashboard_L152_210623/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h

Rev	Author	Line No.	Line
30	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32l1xx_hal_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM HAL module.
		6	******************************************************************************
		7	* @attention
		8	*
50	mjames	9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
30	mjames	11	*
50	mjames	12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
30	mjames	16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
50	mjames	21	#ifndef STM32L1xx_HAL_TIM_H
		22	#define STM32L1xx_HAL_TIM_H
30	mjames	23
		24	#ifdef __cplusplus
50	mjames	25	extern "C" {
30	mjames	26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32l1xx_hal_def.h"
		30
		31	/** @addtogroup STM32L1xx_HAL_Driver
		32	* @{
		33	*/
		34
		35	/** @addtogroup TIM
		36	* @{
		37	*/
		38
		39	/* Exported types ------------------------------------------------------------*/
		40	/** @defgroup TIM_Exported_Types TIM Exported Types
		41	* @{
		42	*/
50	mjames	43
30	mjames	44	/**
		45	* @brief TIM Time base Configuration Structure definition
		46	*/
		47	typedef struct
		48	{
		49	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		50	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		51
		52	uint32_t CounterMode; /*!< Specifies the counter mode.
		53	This parameter can be a value of @ref TIM_Counter_Mode */
		54
		55	uint32_t Period; /*!< Specifies the period value to be loaded into the active
		56	Auto-Reload Register at the next update event.
		57	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
		58
		59	uint32_t ClockDivision; /*!< Specifies the clock division.
		60	This parameter can be a value of @ref TIM_ClockDivision */
		61
50	mjames	62	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
		63	This parameter can be a value of @ref TIM_AutoReloadPreload */
30	mjames	64	} TIM_Base_InitTypeDef;
		65
		66	/**
		67	* @brief TIM Output Compare Configuration Structure definition
		68	*/
		69	typedef struct
		70	{
		71	uint32_t OCMode; /*!< Specifies the TIM mode.
		72	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
		73
		74	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
		75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		76
		77	uint32_t OCPolarity; /*!< Specifies the output polarity.
		78	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
		79
50	mjames	80	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
30	mjames	81	This parameter can be a value of @ref TIM_Output_Fast_State
		82	@note This parameter is valid only in PWM1 and PWM2 mode. */
		83	} TIM_OC_InitTypeDef;
		84
		85	/**
		86	* @brief TIM One Pulse Mode Configuration Structure definition
		87	*/
		88	typedef struct
		89	{
		90	uint32_t OCMode; /*!< Specifies the TIM mode.
		91	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
		92
		93	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
		94	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		95
		96	uint32_t OCPolarity; /*!< Specifies the output polarity.
		97	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
		98
		99	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		100	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
		101
		102	uint32_t ICSelection; /*!< Specifies the input.
		103	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		104
		105	uint32_t ICFilter; /*!< Specifies the input capture filter.
		106	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		107	} TIM_OnePulse_InitTypeDef;
		108
		109	/**
		110	* @brief TIM Input Capture Configuration Structure definition
		111	*/
		112	typedef struct
		113	{
		114	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
50	mjames	115	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
30	mjames	116
		117	uint32_t ICSelection; /*!< Specifies the input.
		118	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		119
		120	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		121	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		122
		123	uint32_t ICFilter; /*!< Specifies the input capture filter.
		124	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		125	} TIM_IC_InitTypeDef;
		126
		127	/**
		128	* @brief TIM Encoder Configuration Structure definition
		129	*/
		130	typedef struct
		131	{
		132	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
		133	This parameter can be a value of @ref TIM_Encoder_Mode */
		134
		135	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
50	mjames	136	This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
30	mjames	137
		138	uint32_t IC1Selection; /*!< Specifies the input.
		139	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		140
		141	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
		142	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		143
		144	uint32_t IC1Filter; /*!< Specifies the input capture filter.
		145	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		146
		147	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
50	mjames	148	This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
30	mjames	149
		150	uint32_t IC2Selection; /*!< Specifies the input.
		151	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		152
		153	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
		154	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		155
		156	uint32_t IC2Filter; /*!< Specifies the input capture filter.
		157	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		158	} TIM_Encoder_InitTypeDef;
		159
		160	/**
50	mjames	161	* @brief Clock Configuration Handle Structure definition
30	mjames	162	*/
		163	typedef struct
		164	{
		165	uint32_t ClockSource; /*!< TIM clock sources
		166	This parameter can be a value of @ref TIM_Clock_Source */
		167	uint32_t ClockPolarity; /*!< TIM clock polarity
		168	This parameter can be a value of @ref TIM_Clock_Polarity */
		169	uint32_t ClockPrescaler; /*!< TIM clock prescaler
		170	This parameter can be a value of @ref TIM_Clock_Prescaler */
		171	uint32_t ClockFilter; /*!< TIM clock filter
50	mjames	172	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		173	} TIM_ClockConfigTypeDef;
30	mjames	174
		175	/**
		176	* @brief TIM Clear Input Configuration Handle Structure definition
		177	*/
		178	typedef struct
		179	{
		180	uint32_t ClearInputState; /*!< TIM clear Input state
		181	This parameter can be ENABLE or DISABLE */
		182	uint32_t ClearInputSource; /*!< TIM clear Input sources
		183	This parameter can be a value of @ref TIM_ClearInput_Source */
		184	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
		185	This parameter can be a value of @ref TIM_ClearInput_Polarity */
		186	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
61	mjames	187	This parameter must be 0: When OCRef clear feature is used with ETR source,
		188	ETR prescaler must be off */
30	mjames	189	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
50	mjames	190	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		191	} TIM_ClearInputConfigTypeDef;
30	mjames	192
		193	/**
50	mjames	194	* @brief TIM Master configuration Structure definition
		195	*/
		196	typedef struct
		197	{
		198	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
		199	This parameter can be a value of @ref TIM_Master_Mode_Selection */
		200	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
		201	This parameter can be a value of @ref TIM_Master_Slave_Mode
		202	@note When the Master/slave mode is enabled, the effect of
		203	an event on the trigger input (TRGI) is delayed to allow a
		204	perfect synchronization between the current timer and its
		205	slaves (through TRGO). It is not mandatory in case of timer
		206	synchronization mode. */
		207	} TIM_MasterConfigTypeDef;
		208
		209	/**
30	mjames	210	* @brief TIM Slave configuration Structure definition
		211	*/
50	mjames	212	typedef struct
		213	{
30	mjames	214	uint32_t SlaveMode; /*!< Slave mode selection
50	mjames	215	This parameter can be a value of @ref TIM_Slave_Mode */
30	mjames	216	uint32_t InputTrigger; /*!< Input Trigger source
50	mjames	217	This parameter can be a value of @ref TIM_Trigger_Selection */
30	mjames	218	uint32_t TriggerPolarity; /*!< Input Trigger polarity
50	mjames	219	This parameter can be a value of @ref TIM_Trigger_Polarity */
30	mjames	220	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
50	mjames	221	This parameter can be a value of @ref TIM_Trigger_Prescaler */
30	mjames	222	uint32_t TriggerFilter; /*!< Input trigger filter
50	mjames	223	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
30	mjames	224
50	mjames	225	} TIM_SlaveConfigTypeDef;
30	mjames	226
		227	/**
		228	* @brief HAL State structures definition
		229	*/
		230	typedef enum
		231	{
50	mjames	232	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
		233	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
		234	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
		235	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
		236	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
		237	} HAL_TIM_StateTypeDef;
30	mjames	238
		239	/**
50	mjames	240	* @brief TIM Channel States definition
		241	*/
		242	typedef enum
		243	{
		244	HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /!< TIM Channel initial state /
		245	HAL_TIM_CHANNEL_STATE_READY = 0x01U, /!< TIM Channel ready for use /
		246	HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /!< An internal process is ongoing on the TIM channel /
		247	} HAL_TIM_ChannelStateTypeDef;
		248
		249	/**
		250	* @brief DMA Burst States definition
		251	*/
		252	typedef enum
		253	{
		254	HAL_DMA_BURST_STATE_RESET = 0x00U, /!< DMA Burst initial state /
		255	HAL_DMA_BURST_STATE_READY = 0x01U, /!< DMA Burst ready for use /
		256	HAL_DMA_BURST_STATE_BUSY = 0x02U, /!< Ongoing DMA Burst /
		257	} HAL_TIM_DMABurstStateTypeDef;
		258
		259	/**
30	mjames	260	* @brief HAL Active channel structures definition
		261	*/
		262	typedef enum
		263	{
50	mjames	264	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
		265	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
		266	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
		267	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
		268	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
		269	} HAL_TIM_ActiveChannel;
30	mjames	270
		271	/**
		272	* @brief TIM Time Base Handle Structure definition
		273	*/
50	mjames	274	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		275	typedef struct __TIM_HandleTypeDef
		276	#else
30	mjames	277	typedef struct
50	mjames	278	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
30	mjames	279	{
50	mjames	280	TIM_TypeDef Instance; /!< Register base address */
		281	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
		282	HAL_TIM_ActiveChannel Channel; /!< Active channel /
		283	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
		284	This array is accessed by a @ref DMA_Handle_index */
		285	HAL_LockTypeDef Lock; /!< Locking object /
		286	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
		287	__IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /!< TIM channel operation state /
		288	__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /!< DMA burst operation state /
30	mjames	289
50	mjames	290	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		291	void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp Init Callback */
		292	void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp DeInit Callback */
		293	void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp Init Callback */
		294	void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp DeInit Callback */
		295	void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp Init Callback */
		296	void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp DeInit Callback */
		297	void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp Init Callback */
		298	void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp DeInit Callback */
		299	void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp Init Callback */
		300	void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp DeInit Callback */
		301	void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp Init Callback */
		302	void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp DeInit Callback */
		303	void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed Callback */
		304	void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed half complete Callback */
		305	void (* TriggerCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger Callback */
		306	void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger half complete Callback */
		307	void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture Callback */
		308	void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture half complete Callback */
		309	void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Output Compare Delay Elapsed Callback */
		310	void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished Callback */
		311	void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished half complete Callback */
		312	void (* ErrorCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Error Callback */
		313	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		314	} TIM_HandleTypeDef;
		315
		316	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
30	mjames	317	/**
50	mjames	318	* @brief HAL TIM Callback ID enumeration definition
		319	*/
		320	typedef enum
		321	{
		322	HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /!< TIM Base MspInit Callback ID /
		323	, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /!< TIM Base MspDeInit Callback ID /
		324	, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /!< TIM IC MspInit Callback ID /
		325	, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /!< TIM IC MspDeInit Callback ID /
		326	, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /!< TIM OC MspInit Callback ID /
		327	, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /!< TIM OC MspDeInit Callback ID /
		328	, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /!< TIM PWM MspInit Callback ID /
		329	, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /!< TIM PWM MspDeInit Callback ID /
		330	, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /!< TIM One Pulse MspInit Callback ID /
		331	, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /!< TIM One Pulse MspDeInit Callback ID /
		332	, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /!< TIM Encoder MspInit Callback ID /
		333	, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /!< TIM Encoder MspDeInit Callback ID /
		334	, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /!< TIM Period Elapsed Callback ID /
		335	, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /!< TIM Period Elapsed half complete Callback ID /
		336	, HAL_TIM_TRIGGER_CB_ID = 0x10U /!< TIM Trigger Callback ID /
		337	, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /!< TIM Trigger half complete Callback ID /
		338
		339	, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /!< TIM Input Capture Callback ID /
		340	, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /!< TIM Input Capture half complete Callback ID /
		341	, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /!< TIM Output Compare Delay Elapsed Callback ID /
		342	, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /!< TIM PWM Pulse Finished Callback ID /
		343	, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /!< TIM PWM Pulse Finished half complete Callback ID /
		344	, HAL_TIM_ERROR_CB_ID = 0x17U /!< TIM Error Callback ID /
		345	} HAL_TIM_CallbackIDTypeDef;
		346
		347	/**
		348	* @brief HAL TIM Callback pointer definition
		349	*/
		350	typedef void (pTIM_CallbackTypeDef)(TIM_HandleTypeDef htim); /!< pointer to the TIM callback function /
		351
		352	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		353
		354	/**
30	mjames	355	* @}
		356	*/
50	mjames	357	/* End of exported types -----------------------------------------------------*/
30	mjames	358
		359	/* Exported constants --------------------------------------------------------*/
		360	/** @defgroup TIM_Exported_Constants TIM Exported Constants
		361	* @{
		362	*/
		363
50	mjames	364	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
30	mjames	365	* @{
		366	*/
50	mjames	367	#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /!< OCREF_CLR is disabled /
		368	#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /!< OCREF_CLR is connected to ETRF input /
		369	#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /!< OCREF_CLR is connected to OCREF_CLR_INT /
30	mjames	370	/**
		371	* @}
		372	*/
		373
50	mjames	374	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
30	mjames	375	* @{
		376	*/
50	mjames	377	#define TIM_DMABASE_CR1 0x00000000U
		378	#define TIM_DMABASE_CR2 0x00000001U
		379	#define TIM_DMABASE_SMCR 0x00000002U
		380	#define TIM_DMABASE_DIER 0x00000003U
		381	#define TIM_DMABASE_SR 0x00000004U
		382	#define TIM_DMABASE_EGR 0x00000005U
		383	#define TIM_DMABASE_CCMR1 0x00000006U
		384	#define TIM_DMABASE_CCMR2 0x00000007U
		385	#define TIM_DMABASE_CCER 0x00000008U
		386	#define TIM_DMABASE_CNT 0x00000009U
		387	#define TIM_DMABASE_PSC 0x0000000AU
		388	#define TIM_DMABASE_ARR 0x0000000BU
		389	#define TIM_DMABASE_CCR1 0x0000000DU
		390	#define TIM_DMABASE_CCR2 0x0000000EU
		391	#define TIM_DMABASE_CCR3 0x0000000FU
		392	#define TIM_DMABASE_CCR4 0x00000010U
		393	#define TIM_DMABASE_DCR 0x00000012U
		394	#define TIM_DMABASE_DMAR 0x00000013U
		395	#define TIM_DMABASE_OR 0x00000014U
30	mjames	396	/**
		397	* @}
		398	*/
		399
50	mjames	400	/** @defgroup TIM_Event_Source TIM Event Source
30	mjames	401	* @{
		402	*/
50	mjames	403	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
		404	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1 /
		405	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2 /
		406	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3 /
		407	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4 /
		408	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /!< A trigger event is generated /
30	mjames	409	/**
		410	* @}
		411	*/
		412
50	mjames	413	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
30	mjames	414	* @{
		415	*/
50	mjames	416	#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /!< Polarity for TIx source /
		417	#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /!< Polarity for TIx source /
		418	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
30	mjames	419	/**
		420	* @}
		421	*/
		422
50	mjames	423	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
30	mjames	424	* @{
		425	*/
50	mjames	426	#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /!< Polarity for ETR source /
		427	#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /!< Polarity for ETR source /
30	mjames	428	/**
		429	* @}
		430	*/
		431
50	mjames	432	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
30	mjames	433	* @{
		434	*/
50	mjames	435	#define TIM_ETRPRESCALER_DIV1 0x00000000U /!< No prescaler is used /
		436	#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR input source is divided by 2 /
		437	#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR input source is divided by 4 /
		438	#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR input source is divided by 8 /
30	mjames	439	/**
		440	* @}
		441	*/
		442
50	mjames	443	/** @defgroup TIM_Counter_Mode TIM Counter Mode
30	mjames	444	* @{
		445	*/
50	mjames	446	#define TIM_COUNTERMODE_UP 0x00000000U /!< Counter used as up-counter /
		447	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as down-counter /
		448	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /!< Center-aligned mode 1 /
		449	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /!< Center-aligned mode 2 /
		450	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /!< Center-aligned mode 3 /
30	mjames	451	/**
		452	* @}
		453	*/
		454
50	mjames	455	/** @defgroup TIM_ClockDivision TIM Clock Division
30	mjames	456	* @{
		457	*/
50	mjames	458	#define TIM_CLOCKDIVISION_DIV1 0x00000000U /!< Clock division: tDTS=tCK_INT /
		459	#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< Clock division: tDTS=2tCK_INT */
		460	#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< Clock division: tDTS=4tCK_INT */
30	mjames	461	/**
		462	* @}
		463	*/
		464
50	mjames	465	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
30	mjames	466	* @{
		467	*/
50	mjames	468	#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /!< Capture/Compare 1 output disabled /
		469	#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /!< Capture/Compare 1 output enabled /
30	mjames	470	/**
		471	* @}
		472	*/
		473
50	mjames	474	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
30	mjames	475	* @{
		476	*/
50	mjames	477	#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /!< TIMx_ARR register is not buffered /
		478	#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /!< TIMx_ARR register is buffered /
		479
30	mjames	480	/**
		481	* @}
		482	*/
		483
50	mjames	484	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
30	mjames	485	* @{
		486	*/
50	mjames	487	#define TIM_OCFAST_DISABLE 0x00000000U /!< Output Compare fast disable /
		488	#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /!< Output Compare fast enable /
30	mjames	489	/**
		490	* @}
		491	*/
		492
50	mjames	493	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
30	mjames	494	* @{
		495	*/
50	mjames	496	#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /!< OCxN is disabled /
		497	#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /!< OCxN is enabled /
30	mjames	498	/**
		499	* @}
		500	*/
		501
50	mjames	502	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
30	mjames	503	* @{
		504	*/
50	mjames	505	#define TIM_OCPOLARITY_HIGH 0x00000000U /!< Capture/Compare output polarity /
		506	#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< Capture/Compare output polarity /
30	mjames	507	/**
		508	* @}
		509	*/
		510
50	mjames	511	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
30	mjames	512	* @{
		513	*/
50	mjames	514	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Capture triggered by rising edge on timer input /
		515	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Capture triggered by falling edge on timer input /
		516	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Capture triggered by both rising and falling edges on timer input/
30	mjames	517	/**
		518	* @}
		519	*/
		520
50	mjames	521	/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
30	mjames	522	* @{
		523	*/
50	mjames	524	#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Encoder input with rising edge polarity /
		525	#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Encoder input with falling edge polarity /
30	mjames	526	/**
		527	* @}
		528	*/
		529
50	mjames	530	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
30	mjames	531	* @{
		532	*/
61	mjames	533	#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively /
		534	#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively /
50	mjames	535	#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
30	mjames	536	/**
		537	* @}
		538	*/
		539
50	mjames	540	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
30	mjames	541	* @{
		542	*/
50	mjames	543	#define TIM_ICPSC_DIV1 0x00000000U /!< Capture performed each time an edge is detected on the capture input /
		544	#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /!< Capture performed once every 2 events /
		545	#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /!< Capture performed once every 4 events /
		546	#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /!< Capture performed once every 8 events /
30	mjames	547	/**
		548	* @}
		549	*/
		550
50	mjames	551	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
30	mjames	552	* @{
		553	*/
50	mjames	554	#define TIM_OPMODE_SINGLE TIM_CR1_OPM /!< Counter stops counting at the next update event /
		555	#define TIM_OPMODE_REPETITIVE 0x00000000U /!< Counter is not stopped at update event /
30	mjames	556	/**
		557	* @}
		558	*/
		559
50	mjames	560	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
30	mjames	561	* @{
		562	*/
50	mjames	563	#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level /
		564	#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. /
		565	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. /
30	mjames	566	/**
		567	* @}
		568	*/
		569
50	mjames	570	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
30	mjames	571	* @{
		572	*/
50	mjames	573	#define TIM_IT_UPDATE TIM_DIER_UIE /!< Update interrupt /
		574	#define TIM_IT_CC1 TIM_DIER_CC1IE /!< Capture/Compare 1 interrupt /
		575	#define TIM_IT_CC2 TIM_DIER_CC2IE /!< Capture/Compare 2 interrupt /
		576	#define TIM_IT_CC3 TIM_DIER_CC3IE /!< Capture/Compare 3 interrupt /
		577	#define TIM_IT_CC4 TIM_DIER_CC4IE /!< Capture/Compare 4 interrupt /
		578	#define TIM_IT_TRIGGER TIM_DIER_TIE /!< Trigger interrupt /
30	mjames	579	/**
		580	* @}
		581	*/
		582
50	mjames	583	/** @defgroup TIM_DMA_sources TIM DMA Sources
30	mjames	584	* @{
		585	*/
50	mjames	586	#define TIM_DMA_UPDATE TIM_DIER_UDE /!< DMA request is triggered by the update event /
		587	#define TIM_DMA_CC1 TIM_DIER_CC1DE /!< DMA request is triggered by the capture/compare macth 1 event /
		588	#define TIM_DMA_CC2 TIM_DIER_CC2DE /!< DMA request is triggered by the capture/compare macth 2 event event /
		589	#define TIM_DMA_CC3 TIM_DIER_CC3DE /!< DMA request is triggered by the capture/compare macth 3 event event /
		590	#define TIM_DMA_CC4 TIM_DIER_CC4DE /!< DMA request is triggered by the capture/compare macth 4 event event /
		591	#define TIM_DMA_TRIGGER TIM_DIER_TDE /!< DMA request is triggered by the trigger event /
30	mjames	592	/**
		593	* @}
		594	*/
		595
50	mjames	596	/** @defgroup TIM_Flag_definition TIM Flag Definition
30	mjames	597	* @{
		598	*/
50	mjames	599	#define TIM_FLAG_UPDATE TIM_SR_UIF /!< Update interrupt flag /
		600	#define TIM_FLAG_CC1 TIM_SR_CC1IF /!< Capture/Compare 1 interrupt flag /
		601	#define TIM_FLAG_CC2 TIM_SR_CC2IF /!< Capture/Compare 2 interrupt flag /
		602	#define TIM_FLAG_CC3 TIM_SR_CC3IF /!< Capture/Compare 3 interrupt flag /
		603	#define TIM_FLAG_CC4 TIM_SR_CC4IF /!< Capture/Compare 4 interrupt flag /
		604	#define TIM_FLAG_TRIGGER TIM_SR_TIF /!< Trigger interrupt flag /
		605	#define TIM_FLAG_CC1OF TIM_SR_CC1OF /!< Capture 1 overcapture flag /
		606	#define TIM_FLAG_CC2OF TIM_SR_CC2OF /!< Capture 2 overcapture flag /
		607	#define TIM_FLAG_CC3OF TIM_SR_CC3OF /!< Capture 3 overcapture flag /
		608	#define TIM_FLAG_CC4OF TIM_SR_CC4OF /!< Capture 4 overcapture flag /
30	mjames	609	/**
		610	* @}
		611	*/
		612
50	mjames	613	/** @defgroup TIM_Channel TIM Channel
30	mjames	614	* @{
		615	*/
50	mjames	616	#define TIM_CHANNEL_1 0x00000000U /!< Capture/compare channel 1 identifier /
		617	#define TIM_CHANNEL_2 0x00000004U /!< Capture/compare channel 2 identifier /
		618	#define TIM_CHANNEL_3 0x00000008U /!< Capture/compare channel 3 identifier /
		619	#define TIM_CHANNEL_4 0x0000000CU /!< Capture/compare channel 4 identifier /
		620	#define TIM_CHANNEL_ALL 0x0000003CU /!< Global Capture/compare channel identifier /
30	mjames	621	/**
		622	* @}
		623	*/
		624
50	mjames	625	/** @defgroup TIM_Clock_Source TIM Clock Source
30	mjames	626	* @{
		627	*/
50	mjames	628	#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /!< External clock source mode 2 /
		629	#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /!< Internal clock source /
		630	#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /!< External clock source mode 1 (ITR0) /
		631	#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /!< External clock source mode 1 (ITR1) /
		632	#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /!< External clock source mode 1 (ITR2) /
		633	#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /!< External clock source mode 1 (ITR3) /
		634	#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /!< External clock source mode 1 (TTI1FP1 + edge detect.) /
		635	#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /!< External clock source mode 1 (TTI1FP1) /
		636	#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /!< External clock source mode 1 (TTI2FP2) /
		637	#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /!< External clock source mode 1 (ETRF) /
30	mjames	638	/**
		639	* @}
		640	*/
		641
50	mjames	642	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
30	mjames	643	* @{
		644	*/
50	mjames	645	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
		646	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
		647	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
		648	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
		649	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
30	mjames	650	/**
		651	* @}
		652	*/
		653
50	mjames	654	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
30	mjames	655	* @{
		656	*/
50	mjames	657	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		658	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
		659	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
		660	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
30	mjames	661	/**
		662	* @}
		663	*/
		664
50	mjames	665	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
30	mjames	666	* @{
		667	*/
50	mjames	668	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
		669	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
30	mjames	670	/**
		671	* @}
		672	*/
		673
50	mjames	674	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
30	mjames	675	* @{
		676	*/
50	mjames	677	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		678	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
		679	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
		680	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
30	mjames	681	/**
		682	* @}
		683	*/
		684
50	mjames	685	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
30	mjames	686	* @{
		687	*/
50	mjames	688	#define TIM_TRGO_RESET 0x00000000U /!< TIMx_EGR.UG bit is used as trigger output (TRGO) /
		689	#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< TIMx_CR1.CEN bit is used as trigger output (TRGO) /
		690	#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output (TRGO) /
		691	#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< Capture or a compare match 1 is used as trigger output (TRGO) /
		692	#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output (TRGO) /
		693	#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output(TRGO) /
		694	#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output(TRGO) /
		695	#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output(TRGO) /
30	mjames	696	/**
		697	* @}
		698	*/
		699
50	mjames	700	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
30	mjames	701	* @{
		702	*/
50	mjames	703	#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /!< No action /
		704	#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /!< Master/slave mode is selected /
30	mjames	705	/**
		706	* @}
		707	*/
		708
50	mjames	709	/** @defgroup TIM_Slave_Mode TIM Slave mode
30	mjames	710	* @{
		711	*/
50	mjames	712	#define TIM_SLAVEMODE_DISABLE 0x00000000U /!< Slave mode disabled /
		713	#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode /
		714	#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode /
		715	#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode /
		716	#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< External Clock Mode 1 /
30	mjames	717	/**
		718	* @}
		719	*/
		720
50	mjames	721	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
30	mjames	722	* @{
		723	*/
50	mjames	724	#define TIM_OCMODE_TIMING 0x00000000U /!< Frozen /
		725	#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!< Set channel to active level on match /
		726	#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!< Set channel to inactive level on match /
		727	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< Toggle /
		728	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!< PWM mode 1 /
		729	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< PWM mode 2 /
		730	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!< Force active level /
		731	#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!< Force inactive level /
30	mjames	732	/**
		733	* @}
		734	*/
		735
		736	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
		737	* @{
		738	*/
50	mjames	739	#define TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) /
		740	#define TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) /
		741	#define TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) /
		742	#define TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) /
		743	#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) /
		744	#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 1 (TI1FP1) /
		745	#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 2 (TI2FP2) /
		746	#define TIM_TS_ETRF (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered External Trigger input (ETRF) /
		747	#define TIM_TS_NONE 0x0000FFFFU /!< No trigger selected /
30	mjames	748	/**
		749	* @}
		750	*/
		751
		752	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
		753	* @{
		754	*/
50	mjames	755	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
		756	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
		757	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
		758	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
		759	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
30	mjames	760	/**
		761	* @}
		762	*/
		763
		764	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
		765	* @{
		766	*/
50	mjames	767	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		768	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
		769	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
		770	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
30	mjames	771	/**
		772	* @}
		773	*/
		774
		775	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
		776	* @{
		777	*/
50	mjames	778	#define TIM_TI1SELECTION_CH1 0x00000000U /!< The TIMx_CH1 pin is connected to TI1 input /
		779	#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) /
30	mjames	780	/**
		781	* @}
		782	*/
		783
		784	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
		785	* @{
		786	*/
61	mjames	787	#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA /
		788	#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		789	#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		790	#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		791	#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		792	#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		793	#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		794	#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		795	#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		796	#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		797	#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		798	#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		799	#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		800	#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		801	#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		802	#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		803	#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
		804	#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA /
30	mjames	805	/**
		806	* @}
		807	*/
		808
50	mjames	809	/** @defgroup DMA_Handle_index TIM DMA Handle Index
30	mjames	810	* @{
		811	*/
50	mjames	812	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /!< Index of the DMA handle used for Update DMA requests /
		813	#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
		814	#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
		815	#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
		816	#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
		817	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /!< Index of the DMA handle used for Trigger DMA requests /
30	mjames	818	/**
		819	* @}
		820	*/
		821
50	mjames	822	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
30	mjames	823	* @{
		824	*/
50	mjames	825	#define TIM_CCx_ENABLE 0x00000001U /!< Input or output channel is enabled /
		826	#define TIM_CCx_DISABLE 0x00000000U /!< Input or output channel is disabled /
30	mjames	827	/**
		828	* @}
		829	*/
		830
		831	/**
		832	* @}
		833	*/
50	mjames	834	/* End of exported constants -------------------------------------------------*/
30	mjames	835
		836	/* Exported macros -----------------------------------------------------------*/
		837	/** @defgroup TIM_Exported_Macros TIM Exported Macros
		838	* @{
		839	*/
		840
50	mjames	841	/** @brief Reset TIM handle state.
		842	* @param __HANDLE__ TIM handle.
30	mjames	843	* @retval None
50	mjames	844	*/
		845	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		846	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
		847	(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
		848	(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
		849	(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
		850	(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
		851	(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
		852	(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
		853	(__HANDLE__)->Base_MspInitCallback = NULL; \
		854	(__HANDLE__)->Base_MspDeInitCallback = NULL; \
		855	(__HANDLE__)->IC_MspInitCallback = NULL; \
		856	(__HANDLE__)->IC_MspDeInitCallback = NULL; \
		857	(__HANDLE__)->OC_MspInitCallback = NULL; \
		858	(__HANDLE__)->OC_MspDeInitCallback = NULL; \
		859	(__HANDLE__)->PWM_MspInitCallback = NULL; \
		860	(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
		861	(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
		862	(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
		863	(__HANDLE__)->Encoder_MspInitCallback = NULL; \
		864	(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
		865	} while(0)
		866	#else
		867	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
		868	(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
		869	(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
		870	(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
		871	(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
		872	(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
		873	(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
		874	} while(0)
		875	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
30	mjames	876
		877	/**
		878	* @brief Enable the TIM peripheral.
50	mjames	879	* @param __HANDLE__ TIM handle
30	mjames	880	* @retval None
50	mjames	881	*/
30	mjames	882	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
		883
		884	/**
		885	* @brief Disable the TIM peripheral.
50	mjames	886	* @param __HANDLE__ TIM handle
30	mjames	887	* @retval None
		888	*/
		889	#define __HAL_TIM_DISABLE(__HANDLE__) \
50	mjames	890	do { \
		891	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
		892	{ \
		893	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
		894	} \
		895	} while(0)
30	mjames	896
50	mjames	897	/** @brief Enable the specified TIM interrupt.
		898	* @param __HANDLE__ specifies the TIM Handle.
		899	* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
30	mjames	900	* This parameter can be one of the following values:
		901	* @arg TIM_IT_UPDATE: Update interrupt
		902	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		903	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		904	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		905	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		906	* @arg TIM_IT_TRIGGER: Trigger interrupt
		907	* @retval None
		908	*/
		909	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
		910
50	mjames	911	/** @brief Disable the specified TIM interrupt.
		912	* @param __HANDLE__ specifies the TIM Handle.
		913	* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
30	mjames	914	* This parameter can be one of the following values:
		915	* @arg TIM_IT_UPDATE: Update interrupt
		916	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		917	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		918	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		919	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		920	* @arg TIM_IT_TRIGGER: Trigger interrupt
		921	* @retval None
		922	*/
		923	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
		924
50	mjames	925	/** @brief Enable the specified DMA request.
		926	* @param __HANDLE__ specifies the TIM Handle.
		927	* @param __DMA__ specifies the TIM DMA request to enable.
30	mjames	928	* This parameter can be one of the following values:
		929	* @arg TIM_DMA_UPDATE: Update DMA request
		930	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
		931	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
		932	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
		933	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
		934	* @arg TIM_DMA_TRIGGER: Trigger DMA request
		935	* @retval None
		936	*/
		937	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
		938
50	mjames	939	/** @brief Disable the specified DMA request.
		940	* @param __HANDLE__ specifies the TIM Handle.
		941	* @param __DMA__ specifies the TIM DMA request to disable.
30	mjames	942	* This parameter can be one of the following values:
		943	* @arg TIM_DMA_UPDATE: Update DMA request
		944	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
		945	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
		946	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
		947	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
		948	* @arg TIM_DMA_TRIGGER: Trigger DMA request
		949	* @retval None
		950	*/
		951	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
		952
50	mjames	953	/** @brief Check whether the specified TIM interrupt flag is set or not.
		954	* @param __HANDLE__ specifies the TIM Handle.
		955	* @param __FLAG__ specifies the TIM interrupt flag to check.
30	mjames	956	* This parameter can be one of the following values:
		957	* @arg TIM_FLAG_UPDATE: Update interrupt flag
		958	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
		959	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
		960	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
		961	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
		962	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
		963	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
		964	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
		965	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
		966	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
		967	* @retval The new state of __FLAG__ (TRUE or FALSE).
		968	*/
		969	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
		970
50	mjames	971	/** @brief Clear the specified TIM interrupt flag.
		972	* @param __HANDLE__ specifies the TIM Handle.
		973	* @param __FLAG__ specifies the TIM interrupt flag to clear.
30	mjames	974	* This parameter can be one of the following values:
		975	* @arg TIM_FLAG_UPDATE: Update interrupt flag
		976	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
		977	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
		978	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
		979	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
		980	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
		981	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
		982	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
		983	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
		984	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
		985	* @retval The new state of __FLAG__ (TRUE or FALSE).
		986	*/
		987	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
		988
		989	/**
50	mjames	990	* @brief Check whether the specified TIM interrupt source is enabled or not.
		991	* @param __HANDLE__ TIM handle
		992	* @param __INTERRUPT__ specifies the TIM interrupt source to check.
		993	* This parameter can be one of the following values:
		994	* @arg TIM_IT_UPDATE: Update interrupt
		995	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		996	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		997	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		998	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		999	* @arg TIM_IT_TRIGGER: Trigger interrupt
30	mjames	1000	* @retval The state of TIM_IT (SET or RESET).
		1001	*/
50	mjames	1002	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
		1003	== (__INTERRUPT__)) ? SET : RESET)
30	mjames	1004
50	mjames	1005	/** @brief Clear the TIM interrupt pending bits.
		1006	* @param __HANDLE__ TIM handle
		1007	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
		1008	* This parameter can be one of the following values:
		1009	* @arg TIM_IT_UPDATE: Update interrupt
		1010	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1011	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1012	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1013	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1014	* @arg TIM_IT_TRIGGER: Trigger interrupt
30	mjames	1015	* @retval None
		1016	*/
50	mjames	1017	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
30	mjames	1018
		1019	/**
50	mjames	1020	* @brief Indicates whether or not the TIM Counter is used as downcounter.
		1021	* @param __HANDLE__ TIM handle.
30	mjames	1022	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
61	mjames	1023	* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
		1024	* or Encoder mode.
30	mjames	1025	*/
50	mjames	1026	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
30	mjames	1027
		1028	/**
50	mjames	1029	* @brief Set the TIM Prescaler on runtime.
		1030	* @param __HANDLE__ TIM handle.
		1031	* @param __PRESC__ specifies the Prescaler new value.
30	mjames	1032	* @retval None
		1033	*/
50	mjames	1034	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
30	mjames	1035
		1036	/**
50	mjames	1037	* @brief Set the TIM Counter Register value on runtime.
		1038	* @param __HANDLE__ TIM handle.
		1039	* @param __COUNTER__ specifies the Counter register new value.
30	mjames	1040	* @retval None
		1041	*/
		1042	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
		1043
		1044	/**
50	mjames	1045	* @brief Get the TIM Counter Register value on runtime.
		1046	* @param __HANDLE__ TIM handle.
		1047	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
30	mjames	1048	*/
50	mjames	1049	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
30	mjames	1050
		1051	/**
50	mjames	1052	* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
		1053	* @param __HANDLE__ TIM handle.
		1054	* @param __AUTORELOAD__ specifies the Counter register new value.
30	mjames	1055	* @retval None
		1056	*/
		1057	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
50	mjames	1058	do{ \
		1059	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
		1060	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
		1061	} while(0)
30	mjames	1062
		1063	/**
50	mjames	1064	* @brief Get the TIM Autoreload Register value on runtime.
		1065	* @param __HANDLE__ TIM handle.
		1066	* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
30	mjames	1067	*/
50	mjames	1068	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
30	mjames	1069
		1070	/**
50	mjames	1071	* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
		1072	* @param __HANDLE__ TIM handle.
		1073	* @param __CKD__ specifies the clock division value.
30	mjames	1074	* This parameter can be one of the following value:
50	mjames	1075	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
		1076	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
		1077	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
30	mjames	1078	* @retval None
		1079	*/
		1080	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
50	mjames	1081	do{ \
		1082	(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
		1083	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
		1084	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
		1085	} while(0)
30	mjames	1086
		1087	/**
50	mjames	1088	* @brief Get the TIM Clock Division value on runtime.
		1089	* @param __HANDLE__ TIM handle.
		1090	* @retval The clock division can be one of the following values:
		1091	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
		1092	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
		1093	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
30	mjames	1094	*/
50	mjames	1095	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
30	mjames	1096
		1097	/**
61	mjames	1098	* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
		1099	* function.
50	mjames	1100	* @param __HANDLE__ TIM handle.
		1101	* @param __CHANNEL__ TIM Channels to be configured.
30	mjames	1102	* This parameter can be one of the following values:
		1103	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1104	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1105	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1106	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
50	mjames	1107	* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
30	mjames	1108	* This parameter can be one of the following values:
		1109	* @arg TIM_ICPSC_DIV1: no prescaler
		1110	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
		1111	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
		1112	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
		1113	* @retval None
		1114	*/
		1115	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
50	mjames	1116	do{ \
		1117	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
		1118	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
		1119	} while(0)
30	mjames	1120
		1121	/**
50	mjames	1122	* @brief Get the TIM Input Capture prescaler on runtime.
		1123	* @param __HANDLE__ TIM handle.
		1124	* @param __CHANNEL__ TIM Channels to be configured.
30	mjames	1125	* This parameter can be one of the following values:
		1126	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
		1127	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
		1128	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
		1129	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
50	mjames	1130	* @retval The input capture prescaler can be one of the following values:
		1131	* @arg TIM_ICPSC_DIV1: no prescaler
		1132	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
		1133	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
		1134	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
30	mjames	1135	*/
		1136	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
		1137	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
50	mjames	1138	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
30	mjames	1139	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
50	mjames	1140	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
30	mjames	1141
		1142	/**
50	mjames	1143	* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
		1144	* @param __HANDLE__ TIM handle.
		1145	* @param __CHANNEL__ TIM Channels to be configured.
		1146	* This parameter can be one of the following values:
		1147	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1148	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1149	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1150	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1151	* @param __COMPARE__ specifies the Capture Compare register new value.
		1152	* @retval None
		1153	*/
		1154	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
		1155	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
		1156	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
		1157	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
		1158	((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
		1159
		1160	/**
		1161	* @brief Get the TIM Capture Compare Register value on runtime.
		1162	* @param __HANDLE__ TIM handle.
		1163	* @param __CHANNEL__ TIM Channel associated with the capture compare register
		1164	* This parameter can be one of the following values:
		1165	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
		1166	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
		1167	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
		1168	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
		1169	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
		1170	*/
		1171	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
		1172	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
		1173	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
		1174	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
		1175	((__HANDLE__)->Instance->CCR4))
		1176
		1177	/**
		1178	* @brief Set the TIM Output compare preload.
		1179	* @param __HANDLE__ TIM handle.
		1180	* @param __CHANNEL__ TIM Channels to be configured.
		1181	* This parameter can be one of the following values:
		1182	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1183	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1184	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1185	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1186	* @retval None
		1187	*/
		1188	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
		1189	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
		1190	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
		1191	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
		1192	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE))
		1193
		1194	/**
		1195	* @brief Reset the TIM Output compare preload.
		1196	* @param __HANDLE__ TIM handle.
		1197	* @param __CHANNEL__ TIM Channels to be configured.
		1198	* This parameter can be one of the following values:
		1199	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1200	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1201	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1202	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1203	* @retval None
		1204	*/
		1205	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
		1206	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
		1207	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
		1208	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
		1209	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
		1210
		1211	/**
		1212	* @brief Enable fast mode for a given channel.
		1213	* @param __HANDLE__ TIM handle.
		1214	* @param __CHANNEL__ TIM Channels to be configured.
		1215	* This parameter can be one of the following values:
		1216	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1217	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1218	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1219	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1220	* @note When fast mode is enabled an active edge on the trigger input acts
		1221	* like a compare match on CCx output. Delay to sample the trigger
		1222	* input and to activate CCx output is reduced to 3 clock cycles.
		1223	* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
		1224	* @retval None
		1225	*/
		1226	#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
		1227	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1FE) :\
		1228	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2FE) :\
		1229	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3FE) :\
		1230	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4FE))
		1231
		1232	/**
		1233	* @brief Disable fast mode for a given channel.
		1234	* @param __HANDLE__ TIM handle.
		1235	* @param __CHANNEL__ TIM Channels to be configured.
		1236	* This parameter can be one of the following values:
		1237	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1238	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1239	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1240	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1241	* @note When fast mode is disabled CCx output behaves normally depending
		1242	* on counter and CCRx values even when the trigger is ON. The minimum
		1243	* delay to activate CCx output when an active edge occurs on the
		1244	* trigger input is 5 clock cycles.
		1245	* @retval None
		1246	*/
		1247	#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
		1248	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
		1249	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
		1250	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
		1251	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
		1252
		1253	/**
		1254	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
		1255	* @param __HANDLE__ TIM handle.
		1256	* @note When the URS bit of the TIMx_CR1 register is set, only counter
30	mjames	1257	* overflow/underflow generates an update interrupt or DMA request (if
		1258	* enabled)
		1259	* @retval None
		1260	*/
50	mjames	1261	#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|= TIM_CR1_URS)
30	mjames	1262
		1263	/**
50	mjames	1264	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
		1265	* @param __HANDLE__ TIM handle.
		1266	* @note When the URS bit of the TIMx_CR1 register is reset, any of the
		1267	* following events generate an update interrupt or DMA request (if
30	mjames	1268	* enabled):
50	mjames	1269	* _ Counter overflow underflow
		1270	* _ Setting the UG bit
		1271	* _ Update generation through the slave mode controller
30	mjames	1272	* @retval None
		1273	*/
50	mjames	1274	#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
30	mjames	1275
		1276	/**
50	mjames	1277	* @brief Set the TIM Capture x input polarity on runtime.
		1278	* @param __HANDLE__ TIM handle.
		1279	* @param __CHANNEL__ TIM Channels to be configured.
30	mjames	1280	* This parameter can be one of the following values:
		1281	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1282	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1283	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1284	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
50	mjames	1285	* @param __POLARITY__ Polarity for TIx source
30	mjames	1286	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
		1287	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
		1288	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
		1289	* @retval None
		1290	*/
50	mjames	1291	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
		1292	do{ \
		1293	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
		1294	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
		1295	}while(0)
30	mjames	1296
		1297	/**
		1298	* @}
		1299	*/
50	mjames	1300	/* End of exported macros ----------------------------------------------------*/
30	mjames	1301
50	mjames	1302	/* Private constants ---------------------------------------------------------*/
		1303	/** @defgroup TIM_Private_Constants TIM Private Constants
		1304	* @{
		1305	*/
		1306	/* The counter of a timer instance is disabled only if all the CCx and CCxN
		1307	channels have been disabled */
		1308	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
		1309	/**
		1310	* @}
		1311	*/
		1312	/* End of private constants --------------------------------------------------*/
		1313
		1314	/* Private macros ------------------------------------------------------------*/
		1315	/** @defgroup TIM_Private_Macros TIM Private Macros
		1316	* @{
		1317	*/
		1318	#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
		1319	((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
		1320	((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR))
		1321
		1322	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
		1323	((__BASE__) == TIM_DMABASE_CR2) \|\| \
		1324	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
		1325	((__BASE__) == TIM_DMABASE_DIER) \|\| \
		1326	((__BASE__) == TIM_DMABASE_SR) \|\| \
		1327	((__BASE__) == TIM_DMABASE_EGR) \|\| \
		1328	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
		1329	((__BASE__) == TIM_DMABASE_CCMR2) \|\| \
		1330	((__BASE__) == TIM_DMABASE_CCER) \|\| \
		1331	((__BASE__) == TIM_DMABASE_CNT) \|\| \
		1332	((__BASE__) == TIM_DMABASE_PSC) \|\| \
		1333	((__BASE__) == TIM_DMABASE_ARR) \|\| \
		1334	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
		1335	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
		1336	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
		1337	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
		1338	((__BASE__) == TIM_DMABASE_OR))
		1339
		1340	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
		1341
		1342	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
		1343	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
		1344	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
		1345	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
		1346	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
		1347
		1348	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
		1349	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
		1350	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
		1351
		1352	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
		1353	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
		1354
		1355	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
		1356	((__STATE__) == TIM_OCFAST_ENABLE))
		1357
		1358	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
		1359	((__POLARITY__) == TIM_OCPOLARITY_LOW))
		1360
		1361	#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) \|\| \
		1362	((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
		1363
		1364	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
		1365	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
		1366	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
		1367
		1368	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
		1369	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
		1370	((__SELECTION__) == TIM_ICSELECTION_TRC))
		1371
		1372	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
		1373	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
		1374	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
		1375	((__PRESCALER__) == TIM_ICPSC_DIV8))
		1376
		1377	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
		1378	((__MODE__) == TIM_OPMODE_REPETITIVE))
		1379
		1380	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
		1381	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
		1382	((__MODE__) == TIM_ENCODERMODE_TI12))
		1383
		1384	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
		1385
		1386	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1387	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
		1388	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
		1389	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
		1390	((__CHANNEL__) == TIM_CHANNEL_ALL))
		1391
		1392	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1393	((__CHANNEL__) == TIM_CHANNEL_2))
		1394
		1395	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
		1396	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
		1397	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
		1398	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
		1399	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
		1400	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
		1401	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
		1402	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
		1403	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
		1404	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
		1405
		1406	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
		1407	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
		1408	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
		1409	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
		1410	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
		1411
		1412	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
		1413	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
		1414	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
		1415	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
		1416
		1417	#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1418
		1419	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
		1420	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
		1421
		1422	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
		1423	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
		1424	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
		1425	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
		1426
		1427	#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1428
		1429	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
		1430	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
		1431	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
		1432	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
		1433	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
		1434	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
		1435	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
		1436	((__SOURCE__) == TIM_TRGO_OC4REF))
		1437
		1438	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
		1439	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
		1440
		1441	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
		1442	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
		1443	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
		1444	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
		1445	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
		1446
		1447	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
		1448	((__MODE__) == TIM_OCMODE_PWM2))
		1449
		1450	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
		1451	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
		1452	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
		1453	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
		1454	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
		1455	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
		1456
		1457	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
		1458	((__SELECTION__) == TIM_TS_ITR1) \|\| \
		1459	((__SELECTION__) == TIM_TS_ITR2) \|\| \
		1460	((__SELECTION__) == TIM_TS_ITR3) \|\| \
		1461	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
		1462	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
		1463	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
		1464	((__SELECTION__) == TIM_TS_ETRF))
		1465
		1466	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
		1467	((__SELECTION__) == TIM_TS_ITR1) \|\| \
		1468	((__SELECTION__) == TIM_TS_ITR2) \|\| \
		1469	((__SELECTION__) == TIM_TS_ITR3) \|\| \
		1470	((__SELECTION__) == TIM_TS_NONE))
		1471
		1472	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
		1473	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
		1474	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
		1475	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
		1476	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
		1477
		1478	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
		1479	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
		1480	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
		1481	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
		1482
		1483	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1484
		1485	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
		1486	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
		1487
		1488	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
		1489	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
		1490	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
		1491	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
		1492	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
		1493	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
		1494	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
		1495	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
		1496	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
		1497	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
		1498	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
		1499	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
		1500	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
		1501	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
		1502	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
		1503	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
		1504	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
		1505	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
		1506
		1507	#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
		1508
		1509	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1510
		1511	#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
		1512
		1513	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
		1514	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
		1515	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
		1516	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
		1517	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
		1518
		1519	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
		1520	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
		1521	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
		1522	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
		1523	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
		1524
		1525	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
		1526	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
		1527	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
		1528	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
		1529	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U))))
		1530
		1531	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
		1532	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
		1533	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
		1534	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
		1535	((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP)))
		1536
		1537	#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
		1538	(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
		1539	((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
		1540	((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
		1541	(__HANDLE__)->ChannelState[3])
61	mjames	1542
50	mjames	1543	#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
		1544	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
		1545	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
		1546	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
		1547	((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
		1548
		1549	#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
		1550	(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
		1551	(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
		1552	(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
		1553	(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
		1554	} while(0)
		1555
		1556	/**
		1557	* @}
		1558	*/
		1559	/* End of private macros -----------------------------------------------------*/
		1560
		1561	/* Include TIM HAL Extended module */
30	mjames	1562	#include "stm32l1xx_hal_tim_ex.h"
		1563
		1564	/* Exported functions --------------------------------------------------------*/
50	mjames	1565	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
30	mjames	1566	* @{
		1567	*/
		1568
50	mjames	1569	/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
		1570	* @brief Time Base functions
30	mjames	1571	* @{
		1572	*/
		1573	/* Time Base functions ********************************************************/
		1574	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
		1575	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
		1576	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
		1577	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
		1578	/* Blocking mode: Polling */
		1579	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
		1580	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
		1581	/* Non-Blocking mode: Interrupt */
		1582	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
		1583	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
		1584	/* Non-Blocking mode: DMA */
		1585	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
		1586	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
		1587	/**
		1588	* @}
		1589	*/
		1590
50	mjames	1591	/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
		1592	* @brief TIM Output Compare functions
30	mjames	1593	* @{
		1594	*/
50	mjames	1595	/* Timer Output Compare functions *********************************************/
30	mjames	1596	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
		1597	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
		1598	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
		1599	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
		1600	/* Blocking mode: Polling */
		1601	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1602	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1603	/* Non-Blocking mode: Interrupt */
		1604	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1605	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1606	/* Non-Blocking mode: DMA */
		1607	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1608	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1609	/**
		1610	* @}
		1611	*/
		1612
50	mjames	1613	/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
		1614	* @brief TIM PWM functions
30	mjames	1615	* @{
		1616	*/
50	mjames	1617	/* Timer PWM functions ********************************************************/
30	mjames	1618	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
		1619	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
		1620	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
		1621	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
		1622	/* Blocking mode: Polling */
		1623	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1624	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1625	/* Non-Blocking mode: Interrupt */
		1626	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1627	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1628	/* Non-Blocking mode: DMA */
		1629	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1630	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1631	/**
		1632	* @}
		1633	*/
		1634
50	mjames	1635	/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
		1636	* @brief TIM Input Capture functions
30	mjames	1637	* @{
		1638	*/
50	mjames	1639	/* Timer Input Capture functions **********************************************/
30	mjames	1640	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
		1641	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
		1642	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
		1643	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
		1644	/* Blocking mode: Polling */
		1645	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1646	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1647	/* Non-Blocking mode: Interrupt */
		1648	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1649	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1650	/* Non-Blocking mode: DMA */
		1651	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1652	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1653	/**
		1654	* @}
		1655	*/
		1656
50	mjames	1657	/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
		1658	* @brief TIM One Pulse functions
30	mjames	1659	* @{
		1660	*/
50	mjames	1661	/* Timer One Pulse functions **************************************************/
30	mjames	1662	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
		1663	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
		1664	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
		1665	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
		1666	/* Blocking mode: Polling */
		1667	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1668	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1669	/* Non-Blocking mode: Interrupt */
		1670	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1671	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1672	/**
		1673	* @}
		1674	*/
		1675
50	mjames	1676	/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
		1677	* @brief TIM Encoder functions
30	mjames	1678	* @{
		1679	*/
50	mjames	1680	/* Timer Encoder functions ****************************************************/
		1681	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
30	mjames	1682	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
		1683	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
		1684	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
50	mjames	1685	/* Blocking mode: Polling */
30	mjames	1686	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1687	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1688	/* Non-Blocking mode: Interrupt */
		1689	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1690	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1691	/* Non-Blocking mode: DMA */
50	mjames	1692	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1,
		1693	uint32_t *pData2, uint16_t Length);
30	mjames	1694	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1695	/**
		1696	* @}
		1697	*/
		1698
50	mjames	1699	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
		1700	* @brief IRQ handler management
30	mjames	1701	* @{
		1702	*/
50	mjames	1703	/* Interrupt Handler functions ***********************************************/
30	mjames	1704	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
		1705	/**
		1706	* @}
		1707	*/
		1708
50	mjames	1709	/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
		1710	* @brief Peripheral Control functions
30	mjames	1711	* @{
		1712	*/
		1713	/* Control functions *********************************************************/
50	mjames	1714	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
		1715	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
		1716	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
		1717	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig,
		1718	uint32_t OutputChannel, uint32_t InputChannel);
		1719	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig,
		1720	uint32_t Channel);
		1721	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
30	mjames	1722	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
50	mjames	1723	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
		1724	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
		1725	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		1726	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
		1727	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
61	mjames	1728	uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
		1729	uint32_t BurstLength, uint32_t DataLength);
30	mjames	1730	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
50	mjames	1731	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		1732	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
		1733	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
61	mjames	1734	uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
		1735	uint32_t BurstLength, uint32_t DataLength);
30	mjames	1736	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
		1737	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
		1738	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
		1739	/**
		1740	* @}
		1741	*/
		1742
50	mjames	1743	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
		1744	* @brief TIM Callbacks functions
30	mjames	1745	* @{
		1746	*/
		1747	/* Callback in non blocking modes (Interrupt and DMA) *************************/
		1748	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
50	mjames	1749	void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
30	mjames	1750	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
		1751	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
50	mjames	1752	void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
30	mjames	1753	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
50	mjames	1754	void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
30	mjames	1755	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
50	mjames	1756	void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
30	mjames	1757	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
50	mjames	1758
		1759	/* Callbacks Register/UnRegister functions ***********************************/
		1760	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1761	HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
		1762	pTIM_CallbackTypeDef pCallback);
		1763	HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
		1764	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1765
30	mjames	1766	/**
		1767	* @}
		1768	*/
		1769
50	mjames	1770	/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
		1771	* @brief Peripheral State functions
30	mjames	1772	* @{
		1773	*/
50	mjames	1774	/* Peripheral State functions ************************************************/
30	mjames	1775	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
		1776	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
		1777	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
		1778	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
		1779	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
		1780	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
		1781
50	mjames	1782	/* Peripheral Channel state functions ************************************************/
		1783	HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
		1784	HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
		1785	HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
		1786	/**
		1787	* @}
		1788	*/
30	mjames	1789
		1790	/**
		1791	* @}
		1792	*/
50	mjames	1793	/* End of exported functions -------------------------------------------------*/
30	mjames	1794
50	mjames	1795	/* Private functions----------------------------------------------------------*/
		1796	/** @defgroup TIM_Private_Functions TIM Private Functions
		1797	* @{
		1798	*/
		1799	void TIM_DMAError(DMA_HandleTypeDef *hdma);
		1800	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
		1801	void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
		1802
		1803	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1804	void TIM_ResetCallback(TIM_HandleTypeDef *htim);
		1805	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1806
30	mjames	1807	/**
		1808	* @}
		1809	*/
50	mjames	1810	/* End of private functions --------------------------------------------------*/
30	mjames	1811
		1812	/**
		1813	* @}
		1814	*/
		1815
		1816	/**
		1817	* @}
		1818	*/
		1819
		1820	#ifdef __cplusplus
		1821	}
		1822	#endif
		1823
50	mjames	1824	#endif /* STM32L1xx_HAL_TIM_H */
30	mjames	1825
		1826	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/branches/Dashboard_L152_210623/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h – Rev 69