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| 56 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_hal_sram.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of SRAM HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 61 | mjames | 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
| 56 | mjames | 10 | * All rights reserved.</center></h2> |
| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 61 | mjames | 15 | * opensource.org/licenses/BSD-3-Clause |
| 56 | mjames | 16 | * |
| 17 | ****************************************************************************** |
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| 61 | mjames | 18 | */ |
| 56 | mjames | 19 | |
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 61 | mjames | 21 | #ifndef STM32L1xx_HAL_SRAM_H |
| 22 | #define STM32L1xx_HAL_SRAM_H |
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| 56 | mjames | 23 | |
| 24 | #ifdef __cplusplus |
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| 61 | mjames | 25 | extern "C" { |
| 56 | mjames | 26 | #endif |
| 27 | |||
| 61 | mjames | 28 | #if defined(FSMC_BANK1) |
| 29 | |||
| 56 | mjames | 30 | /* Includes ------------------------------------------------------------------*/ |
| 31 | #include "stm32l1xx_ll_fsmc.h" |
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| 32 | |||
| 33 | /** @addtogroup STM32L1xx_HAL_Driver |
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| 34 | * @{ |
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| 35 | */ |
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| 36 | /** @addtogroup SRAM |
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| 37 | * @{ |
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| 61 | mjames | 38 | */ |
| 56 | mjames | 39 | |
| 40 | /* Exported typedef ----------------------------------------------------------*/ |
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| 41 | |||
| 42 | /** @defgroup SRAM_Exported_Types SRAM Exported Types |
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| 43 | * @{ |
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| 61 | mjames | 44 | */ |
| 45 | /** |
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| 46 | * @brief HAL SRAM State structures definition |
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| 47 | */ |
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| 56 | mjames | 48 | typedef enum |
| 49 | { |
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| 61 | mjames | 50 | HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ |
| 51 | HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ |
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| 52 | HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ |
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| 53 | HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ |
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| 54 | HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ |
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| 56 | mjames | 55 | |
| 61 | mjames | 56 | } HAL_SRAM_StateTypeDef; |
| 57 | |||
| 58 | /** |
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| 59 | * @brief SRAM handle Structure definition |
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| 60 | */ |
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| 61 | #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
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| 62 | typedef struct __SRAM_HandleTypeDef |
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| 63 | #else |
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| 56 | mjames | 64 | typedef struct |
| 61 | mjames | 65 | #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
| 56 | mjames | 66 | { |
| 61 | mjames | 67 | FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
| 68 | |||
| 56 | mjames | 69 | FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
| 61 | mjames | 70 | |
| 56 | mjames | 71 | FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ |
| 72 | |||
| 61 | mjames | 73 | HAL_LockTypeDef Lock; /*!< SRAM locking object */ |
| 74 | |||
| 56 | mjames | 75 | __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ |
| 61 | mjames | 76 | |
| 56 | mjames | 77 | DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ |
| 78 | |||
| 61 | mjames | 79 | #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
| 80 | void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ |
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| 81 | void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ |
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| 82 | void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ |
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| 83 | void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ |
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| 84 | #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
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| 85 | } SRAM_HandleTypeDef; |
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| 86 | |||
| 87 | #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
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| 56 | mjames | 88 | /** |
| 61 | mjames | 89 | * @brief HAL SRAM Callback ID enumeration definition |
| 90 | */ |
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| 91 | typedef enum |
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| 92 | { |
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| 93 | HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ |
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| 94 | HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ |
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| 95 | HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ |
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| 96 | HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ |
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| 97 | } HAL_SRAM_CallbackIDTypeDef; |
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| 98 | |||
| 99 | /** |
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| 100 | * @brief HAL SRAM Callback pointer definition |
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| 101 | */ |
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| 102 | typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); |
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| 103 | typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); |
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| 104 | #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
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| 105 | /** |
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| 56 | mjames | 106 | * @} |
| 61 | mjames | 107 | */ |
| 56 | mjames | 108 | |
| 61 | mjames | 109 | /* Exported constants --------------------------------------------------------*/ |
| 56 | mjames | 110 | /* Exported macro ------------------------------------------------------------*/ |
| 111 | |||
| 112 | /** @defgroup SRAM_Exported_Macros SRAM Exported Macros |
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| 113 | * @{ |
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| 61 | mjames | 114 | */ |
| 56 | mjames | 115 | |
| 116 | /** @brief Reset SRAM handle state |
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| 117 | * @param __HANDLE__ SRAM handle |
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| 118 | * @retval None |
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| 119 | */ |
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| 61 | mjames | 120 | #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
| 121 | #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
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| 122 | (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ |
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| 123 | (__HANDLE__)->MspInitCallback = NULL; \ |
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| 124 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
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| 125 | } while(0) |
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| 126 | #else |
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| 56 | mjames | 127 | #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) |
| 61 | mjames | 128 | #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
| 56 | mjames | 129 | |
| 130 | /** |
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| 131 | * @} |
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| 61 | mjames | 132 | */ |
| 56 | mjames | 133 | |
| 134 | /* Exported functions --------------------------------------------------------*/ |
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| 61 | mjames | 135 | /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions |
| 136 | * @{ |
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| 137 | */ |
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| 56 | mjames | 138 | |
| 61 | mjames | 139 | /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
| 140 | * @{ |
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| 141 | */ |
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| 56 | mjames | 142 | |
| 61 | mjames | 143 | /* Initialization/de-initialization functions ********************************/ |
| 144 | HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, |
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| 145 | FSMC_NORSRAM_TimingTypeDef *ExtTiming); |
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| 56 | mjames | 146 | HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); |
| 61 | mjames | 147 | void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); |
| 148 | void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); |
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| 56 | mjames | 149 | |
| 150 | /** |
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| 151 | * @} |
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| 61 | mjames | 152 | */ |
| 56 | mjames | 153 | |
| 61 | mjames | 154 | /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions |
| 155 | * @{ |
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| 156 | */ |
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| 56 | mjames | 157 | |
| 61 | mjames | 158 | /* I/O operation functions ***************************************************/ |
| 159 | HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, |
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| 160 | uint32_t BufferSize); |
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| 161 | HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, |
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| 162 | uint32_t BufferSize); |
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| 163 | HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, |
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| 164 | uint32_t BufferSize); |
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| 165 | HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, |
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| 166 | uint32_t BufferSize); |
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| 167 | HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, |
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| 168 | uint32_t BufferSize); |
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| 169 | HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, |
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| 170 | uint32_t BufferSize); |
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| 171 | HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, |
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| 172 | uint32_t BufferSize); |
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| 173 | HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, |
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| 174 | uint32_t BufferSize); |
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| 175 | |||
| 176 | void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); |
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| 177 | void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); |
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| 178 | |||
| 179 | #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) |
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| 180 | /* SRAM callback registering/unregistering */ |
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| 181 | HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, |
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| 182 | pSRAM_CallbackTypeDef pCallback); |
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| 183 | HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); |
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| 184 | HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, |
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| 185 | pSRAM_DmaCallbackTypeDef pCallback); |
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| 186 | #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ |
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| 187 | |||
| 56 | mjames | 188 | /** |
| 189 | * @} |
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| 61 | mjames | 190 | */ |
| 56 | mjames | 191 | |
| 61 | mjames | 192 | /** @addtogroup SRAM_Exported_Functions_Group3 Control functions |
| 193 | * @{ |
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| 194 | */ |
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| 195 | |||
| 196 | /* SRAM Control functions ****************************************************/ |
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| 56 | mjames | 197 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); |
| 198 | HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); |
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| 199 | |||
| 200 | /** |
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| 201 | * @} |
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| 61 | mjames | 202 | */ |
| 56 | mjames | 203 | |
| 61 | mjames | 204 | /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions |
| 205 | * @{ |
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| 206 | */ |
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| 207 | |||
| 208 | /* SRAM State functions ******************************************************/ |
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| 56 | mjames | 209 | HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); |
| 210 | |||
| 211 | /** |
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| 212 | * @} |
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| 61 | mjames | 213 | */ |
| 56 | mjames | 214 | |
| 215 | /** |
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| 216 | * @} |
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| 61 | mjames | 217 | */ |
| 56 | mjames | 218 | |
| 219 | /** |
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| 220 | * @} |
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| 61 | mjames | 221 | */ |
| 56 | mjames | 222 | |
| 223 | /** |
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| 224 | * @} |
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| 225 | */ |
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| 61 | mjames | 226 | |
| 227 | #endif /* FSMC_BANK1 */ |
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| 228 | |||
| 56 | mjames | 229 | #ifdef __cplusplus |
| 230 | } |
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| 231 | #endif |
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| 232 | |||
| 61 | mjames | 233 | #endif /* STM32L1xx_HAL_SRAM_H */ |
| 56 | mjames | 234 | |
| 235 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |