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| Rev | Author | Line No. | Line |
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| 30 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_hal_pwr.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of PWR HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 50 | mjames | 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
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| 30 | mjames | 11 | * |
| 50 | mjames | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 30 | mjames | 16 | * |
| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32L1xx_HAL_PWR_H |
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| 22 | #define __STM32L1xx_HAL_PWR_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32l1xx_hal_def.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32L1xx_HAL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | /** @addtogroup PWR |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | |||
| 39 | /* Exported types ------------------------------------------------------------*/ |
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| 40 | |||
| 41 | /** @defgroup PWR_Exported_Types PWR Exported Types |
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| 42 | * @{ |
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| 50 | mjames | 43 | */ |
| 30 | mjames | 44 | |
| 45 | /** |
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| 46 | * @brief PWR PVD configuration structure definition |
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| 47 | */ |
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| 48 | typedef struct |
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| 49 | { |
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| 50 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
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| 51 | This parameter can be a value of @ref PWR_PVD_detection_level */ |
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| 52 | |||
| 53 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
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| 54 | This parameter can be a value of @ref PWR_PVD_Mode */ |
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| 55 | }PWR_PVDTypeDef; |
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| 56 | |||
| 57 | /** |
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| 58 | * @} |
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| 59 | */ |
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| 60 | |||
| 61 | /* Internal constants --------------------------------------------------------*/ |
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| 62 | |||
| 63 | /** @addtogroup PWR_Private_Constants |
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| 64 | * @{ |
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| 50 | mjames | 65 | */ |
| 66 | #define PWR_EXTI_LINE_PVD (0x00010000U) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
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| 30 | mjames | 67 | |
| 68 | /** |
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| 69 | * @} |
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| 70 | */ |
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| 71 | |||
| 72 | |||
| 50 | mjames | 73 | |
| 30 | mjames | 74 | /* Exported constants --------------------------------------------------------*/ |
| 75 | |||
| 76 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
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| 77 | * @{ |
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| 50 | mjames | 78 | */ |
| 30 | mjames | 79 | |
| 80 | /** @defgroup PWR_register_alias_address PWR Register alias address |
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| 81 | * @{ |
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| 82 | */ |
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| 83 | /* ------------- PWR registers bit address in the alias region ---------------*/ |
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| 84 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) |
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| 85 | #define PWR_CR_OFFSET 0x00 |
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| 86 | #define PWR_CSR_OFFSET 0x04 |
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| 87 | #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) |
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| 88 | #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) |
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| 89 | /** |
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| 90 | * @} |
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| 91 | */ |
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| 50 | mjames | 92 | |
| 30 | mjames | 93 | /** @defgroup PWR_CR_register_alias PWR CR Register alias address |
| 94 | * @{ |
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| 50 | mjames | 95 | */ |
| 30 | mjames | 96 | /* --- CR Register ---*/ |
| 97 | /* Alias word address of LPSDSR bit */ |
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| 98 | #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR) |
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| 99 | #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4))) |
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| 100 | |||
| 101 | /* Alias word address of DBP bit */ |
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| 102 | #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) |
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| 103 | #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))) |
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| 104 | |||
| 105 | /* Alias word address of LPRUN bit */ |
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| 106 | #define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN) |
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| 107 | #define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4))) |
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| 108 | |||
| 109 | /* Alias word address of PVDE bit */ |
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| 110 | #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) |
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| 111 | #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))) |
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| 112 | |||
| 113 | /* Alias word address of FWU bit */ |
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| 114 | #define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU) |
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| 115 | #define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4))) |
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| 116 | |||
| 117 | /* Alias word address of ULP bit */ |
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| 118 | #define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP) |
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| 119 | #define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4))) |
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| 120 | /** |
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| 121 | * @} |
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| 122 | */ |
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| 123 | |||
| 124 | /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address |
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| 125 | * @{ |
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| 126 | */ |
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| 127 | |||
| 128 | /* --- CSR Register ---*/ |
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| 129 | /* Alias word address of EWUP1, EWUP2 and EWUP3 bits */ |
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| 130 | #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4))) |
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| 131 | /** |
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| 132 | * @} |
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| 133 | */ |
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| 50 | mjames | 134 | |
| 30 | mjames | 135 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level |
| 136 | * @{ |
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| 137 | */ |
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| 138 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 |
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| 139 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 |
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| 140 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 |
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| 141 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 |
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| 142 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 |
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| 143 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 |
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| 144 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 |
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| 50 | mjames | 145 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage |
| 30 | mjames | 146 | (Compare internally to VREFINT) */ |
| 147 | |||
| 148 | /** |
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| 149 | * @} |
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| 150 | */ |
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| 151 | |||
| 152 | /** @defgroup PWR_PVD_Mode PWR PVD Mode |
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| 153 | * @{ |
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| 154 | */ |
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| 50 | mjames | 155 | #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ |
| 156 | #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ |
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| 157 | #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ |
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| 158 | #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
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| 159 | #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ |
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| 160 | #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ |
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| 161 | #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ |
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| 30 | mjames | 162 | |
| 163 | /** |
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| 164 | * @} |
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| 165 | */ |
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| 166 | |||
| 167 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode |
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| 168 | * @{ |
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| 169 | */ |
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| 50 | mjames | 170 | #define PWR_MAINREGULATOR_ON (0x00000000U) |
| 30 | mjames | 171 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR |
| 172 | |||
| 173 | /** |
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| 174 | * @} |
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| 175 | */ |
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| 176 | |||
| 177 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
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| 178 | * @{ |
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| 179 | */ |
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| 180 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) |
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| 181 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) |
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| 182 | |||
| 183 | /** |
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| 184 | * @} |
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| 185 | */ |
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| 186 | |||
| 187 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
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| 188 | * @{ |
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| 189 | */ |
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| 190 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) |
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| 191 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) |
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| 192 | |||
| 193 | /** |
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| 194 | * @} |
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| 195 | */ |
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| 196 | |||
| 197 | /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale |
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| 198 | * @{ |
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| 199 | */ |
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| 200 | |||
| 201 | #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 |
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| 202 | #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 |
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| 203 | #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS |
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| 204 | |||
| 205 | |||
| 206 | /** |
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| 207 | * @} |
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| 208 | */ |
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| 209 | |||
| 210 | /** @defgroup PWR_Flag PWR Flag |
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| 211 | * @{ |
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| 212 | */ |
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| 213 | #define PWR_FLAG_WU PWR_CSR_WUF |
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| 214 | #define PWR_FLAG_SB PWR_CSR_SBF |
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| 215 | #define PWR_FLAG_PVDO PWR_CSR_PVDO |
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| 216 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF |
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| 217 | #define PWR_FLAG_VOS PWR_CSR_VOSF |
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| 218 | #define PWR_FLAG_REGLP PWR_CSR_REGLPF |
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| 219 | |||
| 220 | /** |
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| 221 | * @} |
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| 222 | */ |
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| 223 | |||
| 224 | /** |
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| 225 | * @} |
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| 226 | */ |
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| 227 | |||
| 228 | /* Exported macro ------------------------------------------------------------*/ |
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| 229 | /** @defgroup PWR_Exported_Macros PWR Exported Macros |
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| 230 | * @{ |
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| 231 | */ |
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| 232 | |||
| 233 | /** @brief macros configure the main internal regulator output voltage. |
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| 50 | mjames | 234 | * @param __REGULATOR__ specifies the regulator output voltage to achieve |
| 30 | mjames | 235 | * a tradeoff between performance and power consumption when the device does |
| 236 | * not operate at the maximum frequency (refer to the datasheets for more details). |
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| 237 | * This parameter can be one of the following values: |
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| 238 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, |
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| 239 | * System frequency up to 32 MHz. |
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| 240 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, |
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| 241 | * System frequency up to 16 MHz. |
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| 242 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, |
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| 243 | * System frequency up to 4.2 MHz |
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| 244 | * @retval None |
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| 245 | */ |
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| 246 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) |
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| 247 | |||
| 248 | /** @brief Check PWR flag is set or not. |
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| 50 | mjames | 249 | * @param __FLAG__ specifies the flag to check. |
| 30 | mjames | 250 | * This parameter can be one of the following values: |
| 251 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
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| 252 | * was received from the WKUP pin or from the RTC alarm (Alarm B), |
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| 253 | * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. |
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| 254 | * An additional wakeup event is detected if the WKUP pin is enabled |
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| 255 | * (by setting the EWUP bit) when the WKUP pin level is already high. |
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| 256 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
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| 257 | * resumed from StandBy mode. |
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| 50 | mjames | 258 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
| 30 | mjames | 259 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode |
| 260 | * For this reason, this bit is equal to 0 after Standby or reset |
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| 261 | * until the PVDE bit is set. |
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| 262 | * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. |
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| 263 | * This bit indicates the state of the internal voltage reference, VREFINT. |
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| 264 | * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for |
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| 265 | * the internal regulator to be ready after the voltage range is changed. |
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| 266 | * The VOSF bit indicates that the regulator has reached the voltage level |
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| 267 | * defined with bits VOS of PWR_CR register. |
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| 268 | * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run |
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| 269 | * mode, this bit stays at 1 until the regulator is ready in main mode. |
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| 270 | * A polling on this bit is recommended to wait for the regulator main mode. |
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| 271 | * This bit is reset by hardware when the regulator is ready. |
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| 272 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
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| 273 | */ |
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| 274 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
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| 275 | |||
| 276 | /** @brief Clear the PWR's pending flags. |
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| 50 | mjames | 277 | * @param __FLAG__ specifies the flag to clear. |
| 30 | mjames | 278 | * This parameter can be one of the following values: |
| 279 | * @arg PWR_FLAG_WU: Wake Up flag |
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| 280 | * @arg PWR_FLAG_SB: StandBy flag |
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| 281 | */ |
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| 282 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) |
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| 283 | |||
| 284 | /** |
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| 285 | * @brief Enable interrupt on PVD Exti Line 16. |
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| 286 | * @retval None. |
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| 287 | */ |
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| 288 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
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| 289 | |||
| 290 | /** |
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| 291 | * @brief Disable interrupt on PVD Exti Line 16. |
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| 292 | * @retval None. |
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| 293 | */ |
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| 294 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
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| 295 | |||
| 296 | /** |
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| 297 | * @brief Enable event on PVD Exti Line 16. |
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| 298 | * @retval None. |
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| 299 | */ |
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| 300 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
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| 301 | |||
| 302 | /** |
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| 303 | * @brief Disable event on PVD Exti Line 16. |
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| 304 | * @retval None. |
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| 305 | */ |
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| 306 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
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| 307 | |||
| 308 | |||
| 309 | /** |
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| 310 | * @brief PVD EXTI line configuration: set falling edge trigger. |
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| 311 | * @retval None. |
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| 312 | */ |
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| 313 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
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| 314 | |||
| 315 | |||
| 316 | /** |
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| 317 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
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| 318 | * @retval None. |
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| 319 | */ |
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| 320 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
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| 321 | |||
| 322 | |||
| 323 | /** |
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| 324 | * @brief PVD EXTI line configuration: set rising edge trigger. |
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| 325 | * @retval None. |
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| 326 | */ |
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| 327 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
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| 328 | |||
| 329 | /** |
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| 330 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
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| 331 | * @retval None. |
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| 332 | */ |
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| 333 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
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| 334 | |||
| 335 | /** |
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| 336 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. |
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| 337 | * @retval None. |
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| 338 | */ |
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| 339 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
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| 340 | do { \ |
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| 341 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ |
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| 342 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ |
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| 50 | mjames | 343 | } while(0) |
| 344 | |||
| 30 | mjames | 345 | /** |
| 346 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
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| 347 | * @retval None. |
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| 348 | */ |
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| 349 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
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| 350 | do { \ |
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| 351 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ |
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| 352 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ |
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| 50 | mjames | 353 | } while(0) |
| 30 | mjames | 354 | |
| 355 | |||
| 356 | |||
| 357 | /** |
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| 358 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
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| 359 | * @retval EXTI PVD Line Status. |
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| 360 | */ |
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| 361 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
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| 362 | |||
| 363 | /** |
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| 364 | * @brief Clear the PVD EXTI flag. |
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| 365 | * @retval None. |
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| 366 | */ |
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| 367 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
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| 368 | |||
| 369 | /** |
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| 370 | * @brief Generate a Software interrupt on selected EXTI line. |
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| 371 | * @retval None. |
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| 372 | */ |
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| 373 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
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| 374 | |||
| 375 | /** |
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| 376 | * @} |
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| 377 | */ |
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| 378 | |||
| 379 | /* Private macro -------------------------------------------------------------*/ |
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| 380 | /** @defgroup PWR_Private_Macros PWR Private Macros |
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| 381 | * @{ |
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| 382 | */ |
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| 383 | |||
| 384 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
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| 385 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
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| 386 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
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| 387 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
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| 388 | |||
| 389 | |||
| 390 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
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| 391 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
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| 392 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
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| 393 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
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| 394 | |||
| 395 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
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| 396 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
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| 397 | |||
| 398 | |||
| 399 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
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| 400 | |||
| 401 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) |
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| 402 | |||
| 403 | #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
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| 404 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ |
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| 405 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) |
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| 406 | |||
| 407 | |||
| 408 | /** |
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| 409 | * @} |
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| 410 | */ |
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| 411 | |||
| 412 | |||
| 413 | |||
| 414 | /* Include PWR HAL Extension module */ |
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| 415 | #include "stm32l1xx_hal_pwr_ex.h" |
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| 416 | |||
| 417 | /* Exported functions --------------------------------------------------------*/ |
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| 418 | |||
| 419 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions |
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| 420 | * @{ |
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| 421 | */ |
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| 50 | mjames | 422 | |
| 423 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 30 | mjames | 424 | * @{ |
| 425 | */ |
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| 426 | |||
| 427 | /* Initialization and de-initialization functions *******************************/ |
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| 428 | void HAL_PWR_DeInit(void); |
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| 429 | void HAL_PWR_EnableBkUpAccess(void); |
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| 430 | void HAL_PWR_DisableBkUpAccess(void); |
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| 431 | |||
| 432 | /** |
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| 433 | * @} |
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| 434 | */ |
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| 435 | |||
| 50 | mjames | 436 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions |
| 30 | mjames | 437 | * @{ |
| 438 | */ |
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| 439 | |||
| 440 | /* Peripheral Control functions ************************************************/ |
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| 441 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
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| 442 | void HAL_PWR_EnablePVD(void); |
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| 443 | void HAL_PWR_DisablePVD(void); |
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| 444 | |||
| 445 | /* WakeUp pins configuration functions ****************************************/ |
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| 446 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
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| 447 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
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| 448 | |||
| 449 | /* Low Power modes configuration functions ************************************/ |
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| 450 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
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| 451 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
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| 452 | void HAL_PWR_EnterSTANDBYMode(void); |
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| 453 | |||
| 454 | void HAL_PWR_EnableSleepOnExit(void); |
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| 455 | void HAL_PWR_DisableSleepOnExit(void); |
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| 456 | void HAL_PWR_EnableSEVOnPend(void); |
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| 457 | void HAL_PWR_DisableSEVOnPend(void); |
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| 458 | |||
| 459 | |||
| 460 | |||
| 461 | void HAL_PWR_PVD_IRQHandler(void); |
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| 462 | void HAL_PWR_PVDCallback(void); |
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| 463 | /** |
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| 464 | * @} |
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| 465 | */ |
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| 466 | |||
| 467 | /** |
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| 468 | * @} |
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| 469 | */ |
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| 470 | |||
| 471 | /** |
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| 472 | * @} |
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| 473 | */ |
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| 50 | mjames | 474 | |
| 30 | mjames | 475 | /** |
| 476 | * @} |
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| 477 | */ |
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| 478 | |||
| 479 | #ifdef __cplusplus |
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| 480 | } |
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| 481 | #endif |
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| 482 | |||
| 483 | |||
| 484 | #endif /* __STM32L1xx_HAL_PWR_H */ |
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| 485 | |||
| 486 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |