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| 56 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_hal_nor.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of NOR HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32L1xx_HAL_NOR_H |
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| 22 | #define __STM32L1xx_HAL_NOR_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32l1xx_ll_fsmc.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32L1xx_HAL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
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| 36 | /** @addtogroup NOR |
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| 37 | * @{ |
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| 38 | */ |
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| 39 | |||
| 40 | /** @addtogroup NOR_Private_Constants |
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| 41 | * @{ |
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| 42 | */ |
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| 43 | |||
| 44 | /* NOR device IDs addresses */ |
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| 45 | #define MC_ADDRESS ((uint16_t)0x0000) |
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| 46 | #define DEVICE_CODE1_ADDR ((uint16_t)0x0001) |
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| 47 | #define DEVICE_CODE2_ADDR ((uint16_t)0x000E) |
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| 48 | #define DEVICE_CODE3_ADDR ((uint16_t)0x000F) |
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| 49 | |||
| 50 | /* NOR CFI IDs addresses */ |
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| 51 | #define CFI1_ADDRESS ((uint16_t)0x10) |
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| 52 | #define CFI2_ADDRESS ((uint16_t)0x11) |
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| 53 | #define CFI3_ADDRESS ((uint16_t)0x12) |
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| 54 | #define CFI4_ADDRESS ((uint16_t)0x13) |
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| 55 | |||
| 56 | /* NOR operation wait timeout */ |
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| 57 | #define NOR_TMEOUT ((uint16_t)0xFFFF) |
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| 58 | |||
| 59 | /* NOR memory data width */ |
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| 60 | #define NOR_MEMORY_8B ((uint8_t)0x0) |
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| 61 | #define NOR_MEMORY_16B ((uint8_t)0x1) |
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| 62 | |||
| 63 | /* NOR memory device read/write start address */ |
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| 64 | #define NOR_MEMORY_ADRESS1 FSMC_BANK1_1 |
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| 65 | #define NOR_MEMORY_ADRESS2 FSMC_BANK1_2 |
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| 66 | #define NOR_MEMORY_ADRESS3 FSMC_BANK1_3 |
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| 67 | #define NOR_MEMORY_ADRESS4 FSMC_BANK1_4 |
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| 68 | |||
| 69 | /** |
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| 70 | * @} |
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| 71 | */ |
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| 72 | |||
| 73 | /** @addtogroup NOR_Private_Macros |
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| 74 | * @{ |
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| 75 | */ |
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| 76 | |||
| 77 | /** |
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| 78 | * @brief NOR memory address shifting. |
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| 79 | * @param __NOR_ADDRESS NOR base address |
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| 80 | * @param __NOR_MEMORY_WIDTH_ NOR memory width |
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| 81 | * @param __ADDRESS__ NOR memory address |
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| 82 | * @retval NOR shifted address value |
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| 83 | */ |
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| 84 | #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ |
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| 85 | ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ |
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| 86 | ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ |
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| 87 | ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) |
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| 88 | |||
| 89 | /** |
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| 90 | * @brief NOR memory write data to specified address. |
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| 91 | * @param __ADDRESS__ NOR memory address |
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| 92 | * @param __DATA__ Data to write |
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| 93 | * @retval None |
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| 94 | */ |
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| 95 | #define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)) |
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| 96 | |||
| 97 | /** |
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| 98 | * @} |
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| 99 | */ |
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| 100 | |||
| 101 | /* Exported typedef ----------------------------------------------------------*/ |
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| 102 | /** @defgroup NOR_Exported_Types NOR Exported Types |
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| 103 | * @{ |
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| 104 | */ |
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| 105 | |||
| 106 | /** |
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| 107 | * @brief HAL SRAM State structures definition |
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| 108 | */ |
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| 109 | typedef enum |
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| 110 | { |
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| 111 | HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ |
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| 112 | HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ |
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| 113 | HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ |
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| 114 | HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ |
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| 115 | HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ |
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| 116 | }HAL_NOR_StateTypeDef; |
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| 117 | |||
| 118 | /** |
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| 119 | * @brief FSMC NOR Status typedef |
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| 120 | */ |
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| 121 | typedef enum |
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| 122 | { |
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| 123 | HAL_NOR_STATUS_SUCCESS = 0, |
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| 124 | HAL_NOR_STATUS_ONGOING, |
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| 125 | HAL_NOR_STATUS_ERROR, |
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| 126 | HAL_NOR_STATUS_TIMEOUT |
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| 127 | }HAL_NOR_StatusTypeDef; |
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| 128 | |||
| 129 | /** |
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| 130 | * @brief FSMC NOR ID typedef |
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| 131 | */ |
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| 132 | typedef struct |
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| 133 | { |
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| 134 | uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ |
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| 135 | |||
| 136 | uint16_t Device_Code1; |
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| 137 | |||
| 138 | uint16_t Device_Code2; |
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| 139 | |||
| 140 | uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. |
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| 141 | These codes can be accessed by performing read operations with specific |
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| 142 | control signals and addresses set.They can also be accessed by issuing |
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| 143 | an Auto Select command */ |
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| 144 | }NOR_IDTypeDef; |
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| 145 | |||
| 146 | /** |
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| 147 | * @brief FSMC NOR CFI typedef |
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| 148 | */ |
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| 149 | typedef struct |
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| 150 | { |
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| 151 | /*!< Defines the information stored in the memory's Common flash interface |
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| 152 | which contains a description of various electrical and timing parameters, |
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| 153 | density information and functions supported by the memory */ |
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| 154 | |||
| 155 | uint16_t CFI_1; |
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| 156 | |||
| 157 | uint16_t CFI_2; |
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| 158 | |||
| 159 | uint16_t CFI_3; |
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| 160 | |||
| 161 | uint16_t CFI_4; |
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| 162 | }NOR_CFITypeDef; |
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| 163 | |||
| 164 | /** |
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| 165 | * @brief NOR handle Structure definition |
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| 166 | */ |
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| 167 | typedef struct |
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| 168 | { |
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| 169 | FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ |
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| 170 | |||
| 171 | FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ |
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| 172 | |||
| 173 | FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ |
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| 174 | |||
| 175 | HAL_LockTypeDef Lock; /*!< NOR locking object */ |
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| 176 | |||
| 177 | __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ |
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| 178 | |||
| 179 | }NOR_HandleTypeDef; |
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| 180 | |||
| 181 | /** |
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| 182 | * @} |
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| 183 | */ |
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| 184 | |||
| 185 | /* Exported constants --------------------------------------------------------*/ |
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| 186 | /* Exported macro ------------------------------------------------------------*/ |
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| 187 | |||
| 188 | /** @defgroup NOR_Exported_macro NOR Exported Macros |
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| 189 | * @{ |
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| 190 | */ |
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| 191 | |||
| 192 | /** @brief Reset NOR handle state |
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| 193 | * @param __HANDLE__ NOR handle |
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| 194 | * @retval None |
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| 195 | */ |
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| 196 | #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) |
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| 197 | |||
| 198 | /** |
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| 199 | * @} |
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| 200 | */ |
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| 201 | |||
| 202 | /* Exported functions --------------------------------------------------------*/ |
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| 203 | /** @addtogroup NOR_Exported_Functions NOR Exported Functions |
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| 204 | * @{ |
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| 205 | */ |
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| 206 | |||
| 207 | /** @addtogroup NOR_Exported_Functions_Group1 |
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| 208 | * @{ |
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| 209 | */ |
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| 210 | |||
| 211 | /* Initialization/de-initialization functions **********************************/ |
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| 212 | HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); |
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| 213 | HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); |
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| 214 | void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); |
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| 215 | void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); |
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| 216 | void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); |
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| 217 | |||
| 218 | /** |
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| 219 | * @} |
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| 220 | */ |
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| 221 | |||
| 222 | /** @addtogroup NOR_Exported_Functions_Group2 |
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| 223 | * @{ |
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| 224 | */ |
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| 225 | |||
| 226 | /* I/O operation functions ***************************************************/ |
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| 227 | HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); |
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| 228 | HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); |
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| 229 | HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
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| 230 | HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); |
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| 231 | |||
| 232 | HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); |
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| 233 | HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); |
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| 234 | |||
| 235 | HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); |
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| 236 | HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); |
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| 237 | HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); |
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| 238 | |||
| 239 | /** |
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| 240 | * @} |
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| 241 | */ |
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| 242 | |||
| 243 | /** @addtogroup NOR_Exported_Functions_Group3 |
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| 244 | * @{ |
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| 245 | */ |
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| 246 | |||
| 247 | /* NOR Control functions *****************************************************/ |
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| 248 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); |
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| 249 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); |
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| 250 | |||
| 251 | /** |
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| 252 | * @} |
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| 253 | */ |
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| 254 | |||
| 255 | /** @addtogroup NOR_Exported_Functions_Group4 |
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| 256 | * @{ |
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| 257 | */ |
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| 258 | |||
| 259 | /* NOR State functions ********************************************************/ |
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| 260 | HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); |
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| 261 | HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); |
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| 262 | |||
| 263 | /** |
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| 264 | * @} |
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| 265 | */ |
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| 266 | |||
| 267 | /** |
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| 268 | * @} |
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| 269 | */ |
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| 270 | |||
| 271 | |||
| 272 | /** |
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| 273 | * @} |
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| 274 | */ |
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| 275 | |||
| 276 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
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| 277 | |||
| 278 | /** |
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| 279 | * @} |
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| 280 | */ |
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| 281 | |||
| 282 | #ifdef __cplusplus |
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| 283 | } |
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| 284 | #endif |
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| 285 | |||
| 286 | #endif /* __STM32L1xx_HAL_NOR_H */ |
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| 287 | |||
| 288 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |