Rev 49 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
2 | mjames | 1 | /* ---------------------------------------------------------------------- |
2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
||
3 | * |
||
4 | * $Date: 19. March 2015 |
||
5 | * $Revision: V.1.4.5 |
||
6 | * |
||
7 | * Project: CMSIS DSP Library |
||
8 | * Title: arm_dot_prod_q31.c |
||
9 | * |
||
10 | * Description: Q31 dot product. |
||
11 | * |
||
12 | * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 |
||
13 | * |
||
14 | * Redistribution and use in source and binary forms, with or without |
||
15 | * modification, are permitted provided that the following conditions |
||
16 | * are met: |
||
17 | * - Redistributions of source code must retain the above copyright |
||
18 | * notice, this list of conditions and the following disclaimer. |
||
19 | * - Redistributions in binary form must reproduce the above copyright |
||
20 | * notice, this list of conditions and the following disclaimer in |
||
21 | * the documentation and/or other materials provided with the |
||
22 | * distribution. |
||
23 | * - Neither the name of ARM LIMITED nor the names of its contributors |
||
24 | * may be used to endorse or promote products derived from this |
||
25 | * software without specific prior written permission. |
||
26 | * |
||
27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
||
28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
||
29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
||
30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
||
31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||
32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
||
33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
||
34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||
35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||
36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
||
37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||
38 | * POSSIBILITY OF SUCH DAMAGE. |
||
39 | * -------------------------------------------------------------------- */ |
||
40 | |||
41 | #include "arm_math.h" |
||
42 | |||
43 | /** |
||
44 | * @ingroup groupMath |
||
45 | */ |
||
46 | |||
47 | /** |
||
48 | * @addtogroup dot_prod |
||
49 | * @{ |
||
50 | */ |
||
51 | |||
52 | /** |
||
53 | * @brief Dot product of Q31 vectors. |
||
54 | * @param[in] *pSrcA points to the first input vector |
||
55 | * @param[in] *pSrcB points to the second input vector |
||
56 | * @param[in] blockSize number of samples in each vector |
||
57 | * @param[out] *result output result returned here |
||
58 | * @return none. |
||
59 | * |
||
60 | * <b>Scaling and Overflow Behavior:</b> |
||
61 | * \par |
||
62 | * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these |
||
63 | * are truncated to 2.48 format by discarding the lower 14 bits. |
||
64 | * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. |
||
65 | * There are 15 guard bits in the accumulator and there is no risk of overflow as long as |
||
66 | * the length of the vectors is less than 2^16 elements. |
||
67 | * The return result is in 16.48 format. |
||
68 | */ |
||
69 | |||
70 | void arm_dot_prod_q31( |
||
71 | q31_t * pSrcA, |
||
72 | q31_t * pSrcB, |
||
73 | uint32_t blockSize, |
||
74 | q63_t * result) |
||
75 | { |
||
76 | q63_t sum = 0; /* Temporary result storage */ |
||
77 | uint32_t blkCnt; /* loop counter */ |
||
78 | |||
79 | |||
80 | #ifndef ARM_MATH_CM0_FAMILY |
||
81 | |||
82 | /* Run the below code for Cortex-M4 and Cortex-M3 */ |
||
83 | q31_t inA1, inA2, inA3, inA4; |
||
84 | q31_t inB1, inB2, inB3, inB4; |
||
85 | |||
86 | /*loop Unrolling */ |
||
87 | blkCnt = blockSize >> 2u; |
||
88 | |||
89 | /* First part of the processing with loop unrolling. Compute 4 outputs at a time. |
||
90 | ** a second loop below computes the remaining 1 to 3 samples. */ |
||
91 | while(blkCnt > 0u) |
||
92 | { |
||
93 | /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ |
||
94 | /* Calculate dot product and then store the result in a temporary buffer. */ |
||
95 | inA1 = *pSrcA++; |
||
96 | inA2 = *pSrcA++; |
||
97 | inA3 = *pSrcA++; |
||
98 | inA4 = *pSrcA++; |
||
99 | inB1 = *pSrcB++; |
||
100 | inB2 = *pSrcB++; |
||
101 | inB3 = *pSrcB++; |
||
102 | inB4 = *pSrcB++; |
||
103 | |||
104 | sum += ((q63_t) inA1 * inB1) >> 14u; |
||
105 | sum += ((q63_t) inA2 * inB2) >> 14u; |
||
106 | sum += ((q63_t) inA3 * inB3) >> 14u; |
||
107 | sum += ((q63_t) inA4 * inB4) >> 14u; |
||
108 | |||
109 | /* Decrement the loop counter */ |
||
110 | blkCnt--; |
||
111 | } |
||
112 | |||
113 | /* If the blockSize is not a multiple of 4, compute any remaining output samples here. |
||
114 | ** No loop unrolling is used. */ |
||
115 | blkCnt = blockSize % 0x4u; |
||
116 | |||
117 | #else |
||
118 | |||
119 | /* Run the below code for Cortex-M0 */ |
||
120 | |||
121 | /* Initialize blkCnt with number of samples */ |
||
122 | blkCnt = blockSize; |
||
123 | |||
124 | #endif /* #ifndef ARM_MATH_CM0_FAMILY */ |
||
125 | |||
126 | |||
127 | while(blkCnt > 0u) |
||
128 | { |
||
129 | /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ |
||
130 | /* Calculate dot product and then store the result in a temporary buffer. */ |
||
131 | sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; |
||
132 | |||
133 | /* Decrement the loop counter */ |
||
134 | blkCnt--; |
||
135 | } |
||
136 | |||
137 | /* Store the result in the destination buffer in 16.48 format */ |
||
138 | *result = sum; |
||
139 | } |
||
140 | |||
141 | /** |
||
142 | * @} end of dot_prod group |
||
143 | */ |