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| 2 | mjames | 1 | /* ---------------------------------------------------------------------- |
| 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
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| 3 | * |
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| 4 | * $Date: 19. March 2015 |
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| 5 | * $Revision: V.1.4.5 |
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| 6 | * |
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| 7 | * Project: CMSIS DSP Library |
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| 8 | * Title: arm_add_f32.c |
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| 9 | * |
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| 10 | * Description: Floating-point vector addition. |
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| 11 | * |
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| 12 | * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 |
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| 13 | * |
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| 14 | * Redistribution and use in source and binary forms, with or without |
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| 15 | * modification, are permitted provided that the following conditions |
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| 16 | * are met: |
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| 17 | * - Redistributions of source code must retain the above copyright |
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| 18 | * notice, this list of conditions and the following disclaimer. |
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| 19 | * - Redistributions in binary form must reproduce the above copyright |
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| 20 | * notice, this list of conditions and the following disclaimer in |
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| 21 | * the documentation and/or other materials provided with the |
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| 22 | * distribution. |
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| 23 | * - Neither the name of ARM LIMITED nor the names of its contributors |
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| 24 | * may be used to endorse or promote products derived from this |
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| 25 | * software without specific prior written permission. |
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| 26 | * |
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| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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| 30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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| 31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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| 33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 38 | * POSSIBILITY OF SUCH DAMAGE. |
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| 39 | * ---------------------------------------------------------------------------- */ |
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| 40 | |||
| 41 | #include "arm_math.h" |
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| 42 | |||
| 43 | /** |
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| 44 | * @ingroup groupMath |
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| 45 | */ |
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| 46 | |||
| 47 | /** |
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| 48 | * @defgroup BasicAdd Vector Addition |
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| 49 | * |
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| 50 | * Element-by-element addition of two vectors. |
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| 51 | * |
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| 52 | * <pre> |
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| 53 | * pDst[n] = pSrcA[n] + pSrcB[n], 0 <= n < blockSize. |
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| 54 | * </pre> |
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| 55 | * |
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| 56 | * There are separate functions for floating-point, Q7, Q15, and Q31 data types. |
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| 57 | */ |
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| 58 | |||
| 59 | /** |
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| 60 | * @addtogroup BasicAdd |
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| 61 | * @{ |
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| 62 | */ |
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| 63 | |||
| 64 | /** |
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| 65 | * @brief Floating-point vector addition. |
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| 66 | * @param[in] *pSrcA points to the first input vector |
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| 67 | * @param[in] *pSrcB points to the second input vector |
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| 68 | * @param[out] *pDst points to the output vector |
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| 69 | * @param[in] blockSize number of samples in each vector |
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| 70 | * @return none. |
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| 71 | */ |
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| 72 | |||
| 73 | void arm_add_f32( |
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| 74 | float32_t * pSrcA, |
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| 75 | float32_t * pSrcB, |
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| 76 | float32_t * pDst, |
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| 77 | uint32_t blockSize) |
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| 78 | { |
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| 79 | uint32_t blkCnt; /* loop counter */ |
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| 80 | |||
| 81 | #ifndef ARM_MATH_CM0_FAMILY |
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| 82 | |||
| 83 | /* Run the below code for Cortex-M4 and Cortex-M3 */ |
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| 84 | float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */ |
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| 85 | float32_t inB1, inB2, inB3, inB4; /* temporary input variables */ |
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| 86 | |||
| 87 | /*loop Unrolling */ |
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| 88 | blkCnt = blockSize >> 2u; |
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| 89 | |||
| 90 | /* First part of the processing with loop unrolling. Compute 4 outputs at a time. |
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| 91 | ** a second loop below computes the remaining 1 to 3 samples. */ |
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| 92 | while(blkCnt > 0u) |
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| 93 | { |
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| 94 | /* C = A + B */ |
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| 95 | /* Add and then store the results in the destination buffer. */ |
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| 96 | |||
| 97 | /* read four inputs from sourceA and four inputs from sourceB */ |
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| 98 | inA1 = *pSrcA; |
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| 99 | inB1 = *pSrcB; |
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| 100 | inA2 = *(pSrcA + 1); |
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| 101 | inB2 = *(pSrcB + 1); |
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| 102 | inA3 = *(pSrcA + 2); |
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| 103 | inB3 = *(pSrcB + 2); |
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| 104 | inA4 = *(pSrcA + 3); |
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| 105 | inB4 = *(pSrcB + 3); |
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| 106 | |||
| 107 | /* C = A + B */ |
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| 108 | /* add and store result to destination */ |
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| 109 | *pDst = inA1 + inB1; |
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| 110 | *(pDst + 1) = inA2 + inB2; |
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| 111 | *(pDst + 2) = inA3 + inB3; |
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| 112 | *(pDst + 3) = inA4 + inB4; |
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| 113 | |||
| 114 | /* update pointers to process next samples */ |
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| 115 | pSrcA += 4u; |
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| 116 | pSrcB += 4u; |
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| 117 | pDst += 4u; |
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| 118 | |||
| 119 | |||
| 120 | /* Decrement the loop counter */ |
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| 121 | blkCnt--; |
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| 122 | } |
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| 123 | |||
| 124 | /* If the blockSize is not a multiple of 4, compute any remaining output samples here. |
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| 125 | ** No loop unrolling is used. */ |
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| 126 | blkCnt = blockSize % 0x4u; |
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| 127 | |||
| 128 | #else |
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| 129 | |||
| 130 | /* Run the below code for Cortex-M0 */ |
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| 131 | |||
| 132 | /* Initialize blkCnt with number of samples */ |
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| 133 | blkCnt = blockSize; |
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| 134 | |||
| 135 | #endif /* #ifndef ARM_MATH_CM0_FAMILY */ |
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| 136 | |||
| 137 | while(blkCnt > 0u) |
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| 138 | { |
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| 139 | /* C = A + B */ |
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| 140 | /* Add and then store the results in the destination buffer. */ |
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| 141 | *pDst++ = (*pSrcA++) + (*pSrcB++); |
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| 142 | |||
| 143 | /* Decrement the loop counter */ |
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| 144 | blkCnt--; |
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| 145 | } |
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| 146 | } |
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| 147 | |||
| 148 | /** |
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| 149 | * @} end of BasicAdd group |
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| 150 | */ |