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30 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32l1xx_hal_pwr.c |
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4 | * @author MCD Application Team |
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5 | * @version V1.2.0 |
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6 | * @date 01-July-2016 |
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7 | * @brief PWR HAL module driver. |
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8 | * |
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9 | * This file provides firmware functions to manage the following |
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10 | * functionalities of the Power Controller (PWR) peripheral: |
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11 | * + Initialization/de-initialization functions |
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12 | * + Peripheral Control functions |
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13 | * |
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14 | ****************************************************************************** |
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15 | * @attention |
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16 | * |
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17 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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18 | * |
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19 | * Redistribution and use in source and binary forms, with or without modification, |
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20 | * are permitted provided that the following conditions are met: |
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21 | * 1. Redistributions of source code must retain the above copyright notice, |
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22 | * this list of conditions and the following disclaimer. |
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23 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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24 | * this list of conditions and the following disclaimer in the documentation |
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25 | * and/or other materials provided with the distribution. |
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26 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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27 | * may be used to endorse or promote products derived from this software |
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28 | * without specific prior written permission. |
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29 | * |
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30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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31 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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33 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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34 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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36 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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38 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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39 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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40 | * |
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41 | ****************************************************************************** |
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42 | */ |
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43 | |||
44 | /* Includes ------------------------------------------------------------------*/ |
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45 | #include "stm32l1xx_hal.h" |
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46 | |||
47 | /** @addtogroup STM32L1xx_HAL_Driver |
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48 | * @{ |
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49 | */ |
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50 | |||
51 | /** @defgroup PWR PWR |
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52 | * @brief PWR HAL module driver |
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53 | * @{ |
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54 | */ |
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55 | |||
56 | #ifdef HAL_PWR_MODULE_ENABLED |
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57 | |||
58 | /* Private typedef -----------------------------------------------------------*/ |
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59 | /* Private define ------------------------------------------------------------*/ |
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60 | #define PVD_MODE_IT ((uint32_t)0x00010000) |
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61 | #define PVD_MODE_EVT ((uint32_t)0x00020000) |
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62 | #define PVD_RISING_EDGE ((uint32_t)0x00000001) |
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63 | #define PVD_FALLING_EDGE ((uint32_t)0x00000002) |
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64 | |||
65 | /* Private macro -------------------------------------------------------------*/ |
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66 | /* Private variables ---------------------------------------------------------*/ |
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67 | /* Private function prototypes -----------------------------------------------*/ |
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68 | /* Private functions ---------------------------------------------------------*/ |
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69 | |||
70 | /** @defgroup PWR_Exported_Functions PWR Exported Functions |
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71 | * @{ |
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72 | */ |
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73 | |||
74 | /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
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75 | * @brief Initialization and de-initialization functions |
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76 | * |
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77 | @verbatim |
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78 | =============================================================================== |
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79 | ##### Initialization and de-initialization functions ##### |
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80 | =============================================================================== |
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81 | [..] |
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82 | After reset, the backup domain (RTC registers, RTC backup data |
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83 | registers) is protected against possible unwanted |
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84 | write accesses. |
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85 | To enable access to the RTC Domain and RTC registers, proceed as follows: |
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86 | (+) Enable the Power Controller (PWR) APB1 interface clock using the |
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87 | __HAL_RCC_PWR_CLK_ENABLE() macro. |
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88 | (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
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89 | |||
90 | @endverbatim |
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91 | * @{ |
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92 | */ |
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93 | |||
94 | /** |
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95 | * @brief Deinitializes the PWR peripheral registers to their default reset values. |
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96 | * @note Before calling this function, the VOS[1:0] bits should be configured |
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97 | * to "10" and the system frequency has to be configured accordingly. |
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98 | * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig() |
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99 | * function. |
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100 | * @note ULP and FWU bits are not reset by this function. |
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101 | * @retval None |
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102 | */ |
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103 | void HAL_PWR_DeInit(void) |
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104 | { |
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105 | __HAL_RCC_PWR_FORCE_RESET(); |
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106 | __HAL_RCC_PWR_RELEASE_RESET(); |
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107 | } |
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108 | |||
109 | /** |
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110 | * @brief Enables access to the backup domain (RTC registers, RTC |
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111 | * backup data registers ). |
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112 | * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the |
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113 | * Backup Domain Access should be kept enabled. |
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114 | * @retval None |
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115 | */ |
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116 | void HAL_PWR_EnableBkUpAccess(void) |
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117 | { |
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118 | /* Enable access to RTC and backup registers */ |
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119 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; |
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120 | } |
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121 | |||
122 | /** |
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123 | * @brief Disables access to the backup domain (RTC registers, RTC |
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124 | * backup data registers). |
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125 | * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the |
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126 | * Backup Domain Access should be kept enabled. |
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127 | * @retval None |
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128 | */ |
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129 | void HAL_PWR_DisableBkUpAccess(void) |
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130 | { |
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131 | /* Disable access to RTC and backup registers */ |
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132 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; |
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133 | } |
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134 | |||
135 | /** |
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136 | * @} |
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137 | */ |
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138 | |||
139 | /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions |
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140 | * @brief Low Power modes configuration functions |
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141 | * |
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142 | @verbatim |
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143 | |||
144 | =============================================================================== |
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145 | ##### Peripheral Control functions ##### |
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146 | =============================================================================== |
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147 | |||
148 | *** PVD configuration *** |
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149 | ========================= |
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150 | [..] |
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151 | (+) The PVD is used to monitor the VDD power supply by comparing it to a |
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152 | threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). |
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153 | (+) The PVD can use an external input analog voltage (PVD_IN) which is compared |
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154 | internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode |
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155 | when PWR_PVDLevel_7 is selected (PLS[2:0] = 111). |
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156 | |||
157 | (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower |
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158 | than the PVD threshold. This event is internally connected to the EXTI |
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159 | line16 and can generate an interrupt if enabled. This is done through |
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160 | __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. |
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161 | (+) The PVD is stopped in Standby mode. |
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162 | |||
163 | *** WakeUp pin configuration *** |
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164 | ================================ |
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165 | [..] |
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166 | (+) WakeUp pin is used to wake up the system from Standby mode. This pin is |
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167 | forced in input pull-down configuration and is active on rising edges. |
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168 | (+) There are two or three WakeUp pins: |
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169 | WakeUp Pin 1 on PA.00. |
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170 | WakeUp Pin 2 on PC.13. |
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171 | WakeUp Pin 3 on PE.06. : Only on product with GPIOE available |
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172 | |||
173 | [..] |
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174 | *** Main and Backup Regulators configuration *** |
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175 | ================================================ |
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176 | |||
177 | (+) The main internal regulator can be configured to have a tradeoff between |
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178 | performance and power consumption when the device does not operate at |
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179 | the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG() |
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180 | macro which configure VOS bit in PWR_CR register: |
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181 | (++) When this bit is set (Regulator voltage output Scale 1 mode selected) |
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182 | the System frequency can go up to 32 MHz. |
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183 | (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) |
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184 | the System frequency can go up to 16 MHz. |
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185 | (++) When this bit is reset (Regulator voltage output Scale 3 mode selected) |
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186 | the System frequency can go up to 4.2 MHz. |
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187 | |||
188 | Refer to the datasheets for more details. |
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189 | |||
190 | *** Low Power modes configuration *** |
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191 | ===================================== |
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192 | [..] |
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193 | The device features 5 low-power modes: |
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194 | (+) Low power run mode: regulator in low power mode, limited clock frequency, |
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195 | limited number of peripherals running. |
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196 | (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running. |
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197 | (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, |
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198 | limited number of peripherals running, regulator in low power mode. |
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199 | (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode. |
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200 | (+) Standby mode: VCORE domain powered off |
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201 | |||
202 | *** Low power run mode *** |
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203 | ========================= |
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204 | [..] |
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205 | To further reduce the consumption when the system is in Run mode, the regulator can be |
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206 | configured in low power mode. In this mode, the system frequency should not exceed |
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207 | MSI frequency range1. |
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208 | In Low power run mode, all I/O pins keep the same state as in Run mode. |
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209 | |||
210 | (+) Entry: |
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211 | (++) VCORE in range2 |
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212 | (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1. |
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213 | (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode() |
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214 | function. |
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215 | (+) Exit: |
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216 | (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode() |
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217 | function. |
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218 | (++) Increase the system frequency if needed. |
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219 | |||
220 | *** Sleep mode *** |
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221 | ================== |
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222 | [..] |
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223 | (+) Entry: |
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224 | The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
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225 | functions with |
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226 | (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
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227 | (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
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228 | |||
229 | (+) Exit: |
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230 | (++) Any peripheral interrupt acknowledged by the nested vectored interrupt |
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231 | controller (NVIC) can wake up the device from Sleep mode. |
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232 | |||
233 | *** Low power sleep mode *** |
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234 | ============================ |
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235 | [..] |
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236 | (+) Entry: |
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237 | The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
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238 | functions with |
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239 | (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
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240 | (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
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241 | (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register. |
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242 | This reduces power consumption but increases the wake-up time. |
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243 | |||
244 | (+) Exit: |
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245 | (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt |
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246 | acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device |
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247 | from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode, |
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248 | the MCU exits Sleep mode as soon as an event occurs. |
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249 | |||
250 | *** Stop mode *** |
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251 | ================= |
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252 | [..] |
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253 | The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral |
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254 | clock gating. The voltage regulator can be configured either in normal or low-power mode. |
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255 | In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and |
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256 | the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. |
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257 | To get the lowest consumption in Stop mode, the internal Flash memory also enters low |
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258 | power mode. When the Flash memory is in power-down mode, an additional startup delay is |
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259 | incurred when waking up from Stop mode. |
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260 | To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature |
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261 | sensor can be switched off before entering Stop mode. They can be switched on again by |
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262 | software after exiting Stop mode using the ULP bit in the PWR_CR register. |
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263 | In Stop mode, all I/O pins keep the same state as in Run mode. |
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264 | |||
265 | (+) Entry: |
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266 | The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI ) |
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267 | function with: |
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268 | (++) Main regulator ON. |
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269 | (++) Low Power regulator ON. |
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270 | (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
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271 | (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
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272 | (+) Exit: |
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273 | (++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock. |
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274 | |||
275 | *** Standby mode *** |
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276 | ==================== |
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277 | [..] |
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278 | The Standby mode allows to achieve the lowest power consumption. It is based on the |
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279 | Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is |
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280 | consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are |
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281 | also switched off. SRAM and register contents are lost except for the RTC registers, RTC |
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282 | backup registers and Standby circuitry. |
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283 | |||
284 | To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature |
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285 | sensor can be switched off before entering the Standby mode. They can be switched |
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286 | on again by software after exiting the Standby mode. |
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287 | function. |
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288 | |||
289 | (+) Entry: |
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290 | (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. |
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291 | (+) Exit: |
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292 | (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, |
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293 | tamper event, time-stamp event, external reset in NRST pin, IWDG reset. |
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294 | |||
295 | *** Auto-wakeup (AWU) from low-power mode *** |
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296 | ============================================= |
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297 | [..] |
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298 | The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC |
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299 | Wakeup event, a tamper event, a time-stamp event, or a comparator event, |
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300 | without depending on an external interrupt (Auto-wakeup mode). |
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301 | |||
302 | (+) RTC auto-wakeup (AWU) from the Stop mode |
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303 | (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: |
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304 | (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt |
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305 | or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() |
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306 | function |
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307 | (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() |
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308 | and HAL_RTC_SetTime() functions. |
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309 | (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it |
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310 | is necessary to: |
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311 | (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and |
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312 | Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT() |
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313 | or HAL_RTCEx_SetTimeStamp_IT() functions. |
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314 | (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: |
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315 | (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and |
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316 | Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function. |
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317 | (+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer() |
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318 | function. |
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319 | |||
320 | (+) RTC auto-wakeup (AWU) from the Standby mode |
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321 | (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: |
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322 | (+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function. |
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323 | (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() |
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324 | and HAL_RTC_SetTime() functions. |
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325 | (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it |
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326 | is necessary to: |
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327 | (+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to |
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328 | detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT() |
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329 | or HAL_RTCEx_SetTamper_IT()functions. |
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330 | (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: |
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331 | (+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event |
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332 | using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions. |
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333 | |||
334 | (+) Comparator auto-wakeup (AWU) from the Stop mode |
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335 | (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup |
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336 | event, it is necessary to: |
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337 | (+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the |
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338 | selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using |
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339 | the COMP functions. |
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340 | (+++) Configure the comparator to generate the event. |
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341 | |||
342 | |||
343 | |||
344 | @endverbatim |
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345 | * @{ |
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346 | */ |
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347 | |||
348 | /** |
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349 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). |
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350 | * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration |
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351 | * information for the PVD. |
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352 | * @note Refer to the electrical characteristics of your device datasheet for |
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353 | * more details about the voltage threshold corresponding to each |
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354 | * detection level. |
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355 | * @retval None |
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356 | */ |
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357 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) |
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358 | { |
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359 | /* Check the parameters */ |
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360 | assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); |
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361 | assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); |
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362 | |||
363 | /* Set PLS[7:5] bits according to PVDLevel value */ |
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364 | MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); |
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365 | |||
366 | /* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
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367 | __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); |
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368 | __HAL_PWR_PVD_EXTI_DISABLE_IT(); |
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369 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE(); |
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370 | |||
371 | /* Configure interrupt mode */ |
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372 | if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) |
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373 | { |
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374 | __HAL_PWR_PVD_EXTI_ENABLE_IT(); |
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375 | } |
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376 | |||
377 | /* Configure event mode */ |
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378 | if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) |
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379 | { |
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380 | __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); |
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381 | } |
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382 | |||
383 | /* Configure the edge */ |
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384 | if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) |
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385 | { |
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386 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); |
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387 | } |
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388 | |||
389 | if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) |
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390 | { |
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391 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
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392 | } |
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393 | } |
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394 | |||
395 | /** |
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396 | * @brief Enables the Power Voltage Detector(PVD). |
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397 | * @retval None |
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398 | */ |
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399 | void HAL_PWR_EnablePVD(void) |
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400 | { |
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401 | /* Enable the power voltage detector */ |
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402 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; |
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403 | } |
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404 | |||
405 | /** |
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406 | * @brief Disables the Power Voltage Detector(PVD). |
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407 | * @retval None |
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408 | */ |
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409 | void HAL_PWR_DisablePVD(void) |
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410 | { |
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411 | /* Disable the power voltage detector */ |
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412 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; |
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413 | } |
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414 | |||
415 | /** |
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416 | * @brief Enables the WakeUp PINx functionality. |
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417 | * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. |
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418 | * This parameter can be one of the following values: |
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419 | * @arg PWR_WAKEUP_PIN1 |
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420 | * @arg PWR_WAKEUP_PIN2 |
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421 | * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available |
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422 | * @retval None |
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423 | */ |
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424 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) |
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425 | { |
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426 | /* Check the parameter */ |
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427 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
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428 | /* Enable the EWUPx pin */ |
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429 | *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; |
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430 | } |
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431 | |||
432 | /** |
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433 | * @brief Disables the WakeUp PINx functionality. |
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434 | * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. |
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435 | * This parameter can be one of the following values: |
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436 | * @arg PWR_WAKEUP_PIN1 |
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437 | * @arg PWR_WAKEUP_PIN2 |
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438 | * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available |
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439 | * @retval None |
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440 | */ |
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441 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) |
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442 | { |
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443 | /* Check the parameter */ |
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444 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
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445 | /* Disable the EWUPx pin */ |
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446 | *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; |
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447 | } |
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448 | |||
449 | /** |
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450 | * @brief Enters Sleep mode. |
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451 | * @note In Sleep mode, all I/O pins keep the same state as in Run mode. |
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452 | * @param Regulator: Specifies the regulator state in SLEEP mode. |
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453 | * This parameter can be one of the following values: |
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454 | * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON |
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455 | * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON |
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456 | * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. |
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457 | * When WFI entry is used, tick interrupt have to be disabled if not desired as |
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458 | * the interrupt wake up source. |
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459 | * This parameter can be one of the following values: |
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460 | * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
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461 | * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
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462 | * @retval None |
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463 | */ |
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464 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) |
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465 | { |
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466 | /* Check the parameters */ |
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467 | assert_param(IS_PWR_REGULATOR(Regulator)); |
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468 | assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); |
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469 | |||
470 | /* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ |
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471 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); |
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472 | |||
473 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
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474 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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475 | |||
476 | /* Select SLEEP mode entry -------------------------------------------------*/ |
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477 | if(SLEEPEntry == PWR_SLEEPENTRY_WFI) |
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478 | { |
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479 | /* Request Wait For Interrupt */ |
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480 | __WFI(); |
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481 | } |
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482 | else |
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483 | { |
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484 | /* Request Wait For Event */ |
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485 | __SEV(); |
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486 | __WFE(); |
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487 | __WFE(); |
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488 | } |
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489 | } |
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490 | |||
491 | /** |
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492 | * @brief Enters Stop mode. |
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493 | * @note In Stop mode, all I/O pins keep the same state as in Run mode. |
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494 | * @note When exiting Stop mode by using an interrupt or a wakeup event, |
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495 | * MSI RC oscillator is selected as system clock. |
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496 | * @note When the voltage regulator operates in low power mode, an additional |
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497 | * startup delay is incurred when waking up from Stop mode. |
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498 | * By keeping the internal regulator ON during Stop mode, the consumption |
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499 | * is higher although the startup time is reduced. |
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500 | * @param Regulator: Specifies the regulator state in Stop mode. |
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501 | * This parameter can be one of the following values: |
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502 | * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON |
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503 | * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON |
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504 | * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. |
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505 | * This parameter can be one of the following values: |
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506 | * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction |
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507 | * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction |
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508 | * @retval None |
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509 | */ |
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510 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
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511 | { |
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512 | /* Check the parameters */ |
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513 | assert_param(IS_PWR_REGULATOR(Regulator)); |
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514 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
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515 | |||
516 | /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ |
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517 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); |
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518 | |||
519 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
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520 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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521 | |||
522 | /* Select Stop mode entry --------------------------------------------------*/ |
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523 | if(STOPEntry == PWR_STOPENTRY_WFI) |
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524 | { |
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525 | /* Request Wait For Interrupt */ |
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526 | __WFI(); |
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527 | } |
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528 | else |
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529 | { |
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530 | /* Request Wait For Event */ |
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531 | __SEV(); |
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532 | __WFE(); |
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533 | __WFE(); |
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534 | } |
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535 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
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536 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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537 | } |
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538 | |||
539 | /** |
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540 | * @brief Enters Standby mode. |
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541 | * @note In Standby mode, all I/O pins are high impedance except for: |
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542 | * - Reset pad (still available) |
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543 | * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC |
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544 | * Alarm out, or RTC clock calibration out. |
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545 | * - WKUP pin 1 (PA0) if enabled. |
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546 | * - WKUP pin 2 (PC13) if enabled. |
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547 | * - WKUP pin 3 (PE6) if enabled. |
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548 | * @retval None |
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549 | */ |
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550 | void HAL_PWR_EnterSTANDBYMode(void) |
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551 | { |
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552 | /* Select Standby mode */ |
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553 | SET_BIT(PWR->CR, PWR_CR_PDDS); |
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554 | |||
555 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
||
556 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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557 | |||
558 | /* This option is used to ensure that store operations are completed */ |
||
559 | #if defined ( __CC_ARM) |
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560 | __force_stores(); |
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561 | #endif |
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562 | /* Request Wait For Interrupt */ |
||
563 | __WFI(); |
||
564 | } |
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565 | |||
566 | |||
567 | /** |
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568 | * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. |
||
569 | * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
||
570 | * re-enters SLEEP mode when an interruption handling is over. |
||
571 | * Setting this bit is useful when the processor is expected to run only on |
||
572 | * interruptions handling. |
||
573 | * @retval None |
||
574 | */ |
||
575 | void HAL_PWR_EnableSleepOnExit(void) |
||
576 | { |
||
577 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
||
578 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
||
579 | } |
||
580 | |||
581 | |||
582 | /** |
||
583 | * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. |
||
584 | * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
||
585 | * re-enters SLEEP mode when an interruption handling is over. |
||
586 | * @retval None |
||
587 | */ |
||
588 | void HAL_PWR_DisableSleepOnExit(void) |
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589 | { |
||
590 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
||
591 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
||
592 | } |
||
593 | |||
594 | |||
595 | /** |
||
596 | * @brief Enables CORTEX M3 SEVONPEND bit. |
||
597 | * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes |
||
598 | * WFE to wake up when an interrupt moves from inactive to pended. |
||
599 | * @retval None |
||
600 | */ |
||
601 | void HAL_PWR_EnableSEVOnPend(void) |
||
602 | { |
||
603 | /* Set SEVONPEND bit of Cortex System Control Register */ |
||
604 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
||
605 | } |
||
606 | |||
607 | |||
608 | /** |
||
609 | * @brief Disables CORTEX M3 SEVONPEND bit. |
||
610 | * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes |
||
611 | * WFE to wake up when an interrupt moves from inactive to pended. |
||
612 | * @retval None |
||
613 | */ |
||
614 | void HAL_PWR_DisableSEVOnPend(void) |
||
615 | { |
||
616 | /* Clear SEVONPEND bit of Cortex System Control Register */ |
||
617 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
||
618 | } |
||
619 | |||
620 | |||
621 | |||
622 | /** |
||
623 | * @brief This function handles the PWR PVD interrupt request. |
||
624 | * @note This API should be called under the PVD_IRQHandler(). |
||
625 | * @retval None |
||
626 | */ |
||
627 | void HAL_PWR_PVD_IRQHandler(void) |
||
628 | { |
||
629 | /* Check PWR exti flag */ |
||
630 | if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) |
||
631 | { |
||
632 | /* PWR PVD interrupt user callback */ |
||
633 | HAL_PWR_PVDCallback(); |
||
634 | |||
635 | /* Clear PWR Exti pending bit */ |
||
636 | __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); |
||
637 | } |
||
638 | } |
||
639 | |||
640 | /** |
||
641 | * @brief PWR PVD interrupt callback |
||
642 | * @retval None |
||
643 | */ |
||
644 | __weak void HAL_PWR_PVDCallback(void) |
||
645 | { |
||
646 | /* NOTE : This function Should not be modified, when the callback is needed, |
||
647 | the HAL_PWR_PVDCallback could be implemented in the user file |
||
648 | */ |
||
649 | } |
||
650 | |||
651 | /** |
||
652 | * @} |
||
653 | */ |
||
654 | |||
655 | /** |
||
656 | * @} |
||
657 | */ |
||
658 | |||
659 | #endif /* HAL_PWR_MODULE_ENABLED */ |
||
660 | /** |
||
661 | * @} |
||
662 | */ |
||
663 | |||
664 | /** |
||
665 | * @} |
||
666 | */ |
||
667 | |||
668 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |