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| Rev | Author | Line No. | Line |
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| 30 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l1xx_hal_pwr.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @version V1.2.0 |
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| 6 | * @date 01-July-2016 |
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| 7 | * @brief Header file of PWR HAL module. |
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| 8 | ****************************************************************************** |
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| 9 | * @attention |
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| 10 | * |
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| 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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| 12 | * |
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| 13 | * Redistribution and use in source and binary forms, with or without modification, |
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| 14 | * are permitted provided that the following conditions are met: |
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| 15 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 16 | * this list of conditions and the following disclaimer. |
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| 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 18 | * this list of conditions and the following disclaimer in the documentation |
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| 19 | * and/or other materials provided with the distribution. |
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| 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 21 | * may be used to endorse or promote products derived from this software |
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| 22 | * without specific prior written permission. |
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| 23 | * |
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| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 34 | * |
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| 35 | ****************************************************************************** |
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| 36 | */ |
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| 37 | |||
| 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 39 | #ifndef __STM32L1xx_HAL_PWR_H |
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| 40 | #define __STM32L1xx_HAL_PWR_H |
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| 41 | |||
| 42 | #ifdef __cplusplus |
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| 43 | extern "C" { |
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| 44 | #endif |
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| 45 | |||
| 46 | /* Includes ------------------------------------------------------------------*/ |
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| 47 | #include "stm32l1xx_hal_def.h" |
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| 48 | |||
| 49 | /** @addtogroup STM32L1xx_HAL_Driver |
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| 50 | * @{ |
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| 51 | */ |
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| 52 | |||
| 53 | /** @addtogroup PWR |
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| 54 | * @{ |
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| 55 | */ |
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| 56 | |||
| 57 | /* Exported types ------------------------------------------------------------*/ |
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| 58 | |||
| 59 | /** @defgroup PWR_Exported_Types PWR Exported Types |
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| 60 | * @{ |
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| 61 | */ |
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| 62 | |||
| 63 | /** |
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| 64 | * @brief PWR PVD configuration structure definition |
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| 65 | */ |
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| 66 | typedef struct |
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| 67 | { |
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| 68 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
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| 69 | This parameter can be a value of @ref PWR_PVD_detection_level */ |
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| 70 | |||
| 71 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
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| 72 | This parameter can be a value of @ref PWR_PVD_Mode */ |
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| 73 | }PWR_PVDTypeDef; |
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| 74 | |||
| 75 | /** |
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| 76 | * @} |
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| 77 | */ |
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| 78 | |||
| 79 | /* Internal constants --------------------------------------------------------*/ |
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| 80 | |||
| 81 | /** @addtogroup PWR_Private_Constants |
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| 82 | * @{ |
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| 83 | */ |
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| 84 | #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
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| 85 | |||
| 86 | /** |
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| 87 | * @} |
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| 88 | */ |
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| 89 | |||
| 90 | |||
| 91 | |||
| 92 | /* Exported constants --------------------------------------------------------*/ |
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| 93 | |||
| 94 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
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| 95 | * @{ |
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| 96 | */ |
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| 97 | |||
| 98 | /** @defgroup PWR_register_alias_address PWR Register alias address |
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| 99 | * @{ |
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| 100 | */ |
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| 101 | /* ------------- PWR registers bit address in the alias region ---------------*/ |
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| 102 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) |
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| 103 | #define PWR_CR_OFFSET 0x00 |
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| 104 | #define PWR_CSR_OFFSET 0x04 |
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| 105 | #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) |
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| 106 | #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) |
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| 107 | /** |
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| 108 | * @} |
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| 109 | */ |
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| 110 | |||
| 111 | /** @defgroup PWR_CR_register_alias PWR CR Register alias address |
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| 112 | * @{ |
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| 113 | */ |
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| 114 | /* --- CR Register ---*/ |
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| 115 | /* Alias word address of LPSDSR bit */ |
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| 116 | #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR) |
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| 117 | #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4))) |
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| 118 | |||
| 119 | /* Alias word address of DBP bit */ |
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| 120 | #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) |
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| 121 | #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))) |
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| 122 | |||
| 123 | /* Alias word address of LPRUN bit */ |
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| 124 | #define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN) |
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| 125 | #define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4))) |
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| 126 | |||
| 127 | /* Alias word address of PVDE bit */ |
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| 128 | #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) |
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| 129 | #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))) |
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| 130 | |||
| 131 | /* Alias word address of FWU bit */ |
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| 132 | #define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU) |
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| 133 | #define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4))) |
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| 134 | |||
| 135 | /* Alias word address of ULP bit */ |
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| 136 | #define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP) |
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| 137 | #define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4))) |
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| 138 | /** |
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| 139 | * @} |
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| 140 | */ |
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| 141 | |||
| 142 | /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address |
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| 143 | * @{ |
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| 144 | */ |
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| 145 | |||
| 146 | /* --- CSR Register ---*/ |
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| 147 | /* Alias word address of EWUP1, EWUP2 and EWUP3 bits */ |
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| 148 | #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4))) |
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| 149 | /** |
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| 150 | * @} |
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| 151 | */ |
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| 152 | |||
| 153 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level |
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| 154 | * @{ |
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| 155 | */ |
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| 156 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 |
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| 157 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 |
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| 158 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 |
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| 159 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 |
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| 160 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 |
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| 161 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 |
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| 162 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 |
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| 163 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage |
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| 164 | (Compare internally to VREFINT) */ |
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| 165 | |||
| 166 | /** |
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| 167 | * @} |
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| 168 | */ |
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| 169 | |||
| 170 | /** @defgroup PWR_PVD_Mode PWR PVD Mode |
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| 171 | * @{ |
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| 172 | */ |
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| 173 | #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ |
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| 174 | #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ |
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| 175 | #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ |
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| 176 | #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
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| 177 | #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ |
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| 178 | #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ |
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| 179 | #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ |
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| 180 | |||
| 181 | /** |
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| 182 | * @} |
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| 183 | */ |
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| 184 | |||
| 185 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode |
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| 186 | * @{ |
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| 187 | */ |
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| 188 | #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) |
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| 189 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR |
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| 190 | |||
| 191 | /** |
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| 192 | * @} |
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| 193 | */ |
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| 194 | |||
| 195 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
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| 196 | * @{ |
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| 197 | */ |
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| 198 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) |
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| 199 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) |
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| 200 | |||
| 201 | /** |
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| 202 | * @} |
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| 203 | */ |
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| 204 | |||
| 205 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
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| 206 | * @{ |
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| 207 | */ |
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| 208 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) |
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| 209 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) |
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| 210 | |||
| 211 | /** |
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| 212 | * @} |
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| 213 | */ |
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| 214 | |||
| 215 | /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale |
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| 216 | * @{ |
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| 217 | */ |
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| 218 | |||
| 219 | #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 |
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| 220 | #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 |
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| 221 | #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS |
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| 222 | |||
| 223 | |||
| 224 | /** |
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| 225 | * @} |
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| 226 | */ |
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| 227 | |||
| 228 | /** @defgroup PWR_Flag PWR Flag |
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| 229 | * @{ |
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| 230 | */ |
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| 231 | #define PWR_FLAG_WU PWR_CSR_WUF |
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| 232 | #define PWR_FLAG_SB PWR_CSR_SBF |
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| 233 | #define PWR_FLAG_PVDO PWR_CSR_PVDO |
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| 234 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF |
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| 235 | #define PWR_FLAG_VOS PWR_CSR_VOSF |
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| 236 | #define PWR_FLAG_REGLP PWR_CSR_REGLPF |
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| 237 | |||
| 238 | /** |
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| 239 | * @} |
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| 240 | */ |
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| 241 | |||
| 242 | /** |
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| 243 | * @} |
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| 244 | */ |
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| 245 | |||
| 246 | /* Exported macro ------------------------------------------------------------*/ |
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| 247 | /** @defgroup PWR_Exported_Macros PWR Exported Macros |
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| 248 | * @{ |
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| 249 | */ |
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| 250 | |||
| 251 | /** @brief macros configure the main internal regulator output voltage. |
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| 252 | * @param __REGULATOR__: specifies the regulator output voltage to achieve |
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| 253 | * a tradeoff between performance and power consumption when the device does |
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| 254 | * not operate at the maximum frequency (refer to the datasheets for more details). |
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| 255 | * This parameter can be one of the following values: |
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| 256 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, |
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| 257 | * System frequency up to 32 MHz. |
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| 258 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, |
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| 259 | * System frequency up to 16 MHz. |
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| 260 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, |
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| 261 | * System frequency up to 4.2 MHz |
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| 262 | * @retval None |
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| 263 | */ |
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| 264 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) |
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| 265 | |||
| 266 | /** @brief Check PWR flag is set or not. |
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| 267 | * @param __FLAG__: specifies the flag to check. |
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| 268 | * This parameter can be one of the following values: |
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| 269 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
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| 270 | * was received from the WKUP pin or from the RTC alarm (Alarm B), |
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| 271 | * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. |
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| 272 | * An additional wakeup event is detected if the WKUP pin is enabled |
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| 273 | * (by setting the EWUP bit) when the WKUP pin level is already high. |
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| 274 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
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| 275 | * resumed from StandBy mode. |
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| 276 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
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| 277 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode |
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| 278 | * For this reason, this bit is equal to 0 after Standby or reset |
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| 279 | * until the PVDE bit is set. |
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| 280 | * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. |
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| 281 | * This bit indicates the state of the internal voltage reference, VREFINT. |
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| 282 | * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for |
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| 283 | * the internal regulator to be ready after the voltage range is changed. |
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| 284 | * The VOSF bit indicates that the regulator has reached the voltage level |
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| 285 | * defined with bits VOS of PWR_CR register. |
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| 286 | * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run |
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| 287 | * mode, this bit stays at 1 until the regulator is ready in main mode. |
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| 288 | * A polling on this bit is recommended to wait for the regulator main mode. |
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| 289 | * This bit is reset by hardware when the regulator is ready. |
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| 290 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
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| 291 | */ |
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| 292 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
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| 293 | |||
| 294 | /** @brief Clear the PWR's pending flags. |
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| 295 | * @param __FLAG__: specifies the flag to clear. |
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| 296 | * This parameter can be one of the following values: |
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| 297 | * @arg PWR_FLAG_WU: Wake Up flag |
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| 298 | * @arg PWR_FLAG_SB: StandBy flag |
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| 299 | */ |
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| 300 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) |
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| 301 | |||
| 302 | /** |
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| 303 | * @brief Enable interrupt on PVD Exti Line 16. |
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| 304 | * @retval None. |
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| 305 | */ |
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| 306 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
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| 307 | |||
| 308 | /** |
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| 309 | * @brief Disable interrupt on PVD Exti Line 16. |
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| 310 | * @retval None. |
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| 311 | */ |
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| 312 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
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| 313 | |||
| 314 | /** |
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| 315 | * @brief Enable event on PVD Exti Line 16. |
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| 316 | * @retval None. |
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| 317 | */ |
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| 318 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
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| 319 | |||
| 320 | /** |
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| 321 | * @brief Disable event on PVD Exti Line 16. |
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| 322 | * @retval None. |
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| 323 | */ |
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| 324 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
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| 325 | |||
| 326 | |||
| 327 | /** |
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| 328 | * @brief PVD EXTI line configuration: set falling edge trigger. |
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| 329 | * @retval None. |
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| 330 | */ |
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| 331 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
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| 332 | |||
| 333 | |||
| 334 | /** |
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| 335 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
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| 336 | * @retval None. |
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| 337 | */ |
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| 338 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
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| 339 | |||
| 340 | |||
| 341 | /** |
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| 342 | * @brief PVD EXTI line configuration: set rising edge trigger. |
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| 343 | * @retval None. |
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| 344 | */ |
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| 345 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
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| 346 | |||
| 347 | /** |
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| 348 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
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| 349 | * @retval None. |
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| 350 | */ |
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| 351 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
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| 352 | |||
| 353 | /** |
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| 354 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. |
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| 355 | * @retval None. |
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| 356 | */ |
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| 357 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
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| 358 | do { \ |
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| 359 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ |
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| 360 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ |
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| 361 | } while(0) |
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| 362 | |||
| 363 | /** |
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| 364 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
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| 365 | * @retval None. |
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| 366 | */ |
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| 367 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
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| 368 | do { \ |
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| 369 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ |
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| 370 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ |
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| 371 | } while(0) |
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| 372 | |||
| 373 | |||
| 374 | |||
| 375 | /** |
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| 376 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
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| 377 | * @retval EXTI PVD Line Status. |
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| 378 | */ |
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| 379 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
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| 380 | |||
| 381 | /** |
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| 382 | * @brief Clear the PVD EXTI flag. |
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| 383 | * @retval None. |
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| 384 | */ |
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| 385 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
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| 386 | |||
| 387 | /** |
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| 388 | * @brief Generate a Software interrupt on selected EXTI line. |
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| 389 | * @retval None. |
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| 390 | */ |
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| 391 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
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| 392 | |||
| 393 | /** |
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| 394 | * @} |
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| 395 | */ |
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| 396 | |||
| 397 | /* Private macro -------------------------------------------------------------*/ |
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| 398 | /** @defgroup PWR_Private_Macros PWR Private Macros |
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| 399 | * @{ |
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| 400 | */ |
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| 401 | |||
| 402 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
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| 403 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
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| 404 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
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| 405 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
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| 406 | |||
| 407 | |||
| 408 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
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| 409 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
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| 410 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
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| 411 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
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| 412 | |||
| 413 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
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| 414 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
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| 415 | |||
| 416 | |||
| 417 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
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| 418 | |||
| 419 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) |
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| 420 | |||
| 421 | #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
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| 422 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ |
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| 423 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) |
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| 424 | |||
| 425 | |||
| 426 | /** |
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| 427 | * @} |
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| 428 | */ |
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| 429 | |||
| 430 | |||
| 431 | |||
| 432 | /* Include PWR HAL Extension module */ |
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| 433 | #include "stm32l1xx_hal_pwr_ex.h" |
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| 434 | |||
| 435 | /* Exported functions --------------------------------------------------------*/ |
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| 436 | |||
| 437 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions |
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| 438 | * @{ |
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| 439 | */ |
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| 440 | |||
| 441 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 442 | * @{ |
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| 443 | */ |
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| 444 | |||
| 445 | /* Initialization and de-initialization functions *******************************/ |
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| 446 | void HAL_PWR_DeInit(void); |
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| 447 | void HAL_PWR_EnableBkUpAccess(void); |
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| 448 | void HAL_PWR_DisableBkUpAccess(void); |
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| 449 | |||
| 450 | /** |
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| 451 | * @} |
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| 452 | */ |
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| 453 | |||
| 454 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions |
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| 455 | * @{ |
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| 456 | */ |
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| 457 | |||
| 458 | /* Peripheral Control functions ************************************************/ |
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| 459 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
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| 460 | void HAL_PWR_EnablePVD(void); |
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| 461 | void HAL_PWR_DisablePVD(void); |
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| 462 | |||
| 463 | /* WakeUp pins configuration functions ****************************************/ |
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| 464 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
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| 465 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
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| 466 | |||
| 467 | /* Low Power modes configuration functions ************************************/ |
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| 468 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
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| 469 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
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| 470 | void HAL_PWR_EnterSTANDBYMode(void); |
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| 471 | |||
| 472 | void HAL_PWR_EnableSleepOnExit(void); |
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| 473 | void HAL_PWR_DisableSleepOnExit(void); |
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| 474 | void HAL_PWR_EnableSEVOnPend(void); |
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| 475 | void HAL_PWR_DisableSEVOnPend(void); |
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| 476 | |||
| 477 | |||
| 478 | |||
| 479 | void HAL_PWR_PVD_IRQHandler(void); |
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| 480 | void HAL_PWR_PVDCallback(void); |
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| 481 | /** |
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| 482 | * @} |
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| 483 | */ |
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| 484 | |||
| 485 | /** |
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| 486 | * @} |
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| 487 | */ |
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| 488 | |||
| 489 | /** |
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| 490 | * @} |
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| 491 | */ |
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| 492 | |||
| 493 | /** |
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| 494 | * @} |
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| 495 | */ |
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| 496 | |||
| 497 | #ifdef __cplusplus |
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| 498 | } |
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| 499 | #endif |
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| 500 | |||
| 501 | |||
| 502 | #endif /* __STM32L1xx_HAL_PWR_H */ |
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| 503 | |||
| 504 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |