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| 2 | mjames | 1 | /* ---------------------------------------------------------------------- |
| 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
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| 3 | * |
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| 4 | * $Date: 19. March 2015 |
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| 5 | * $Revision: V.1.4.5 |
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| 6 | * |
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| 7 | * Project: CMSIS DSP Library |
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| 8 | * Title: arm_rms_q31.c |
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| 9 | * |
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| 10 | * Description: Root Mean Square of the elements of a Q31 vector. |
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| 11 | * |
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| 12 | * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 |
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| 13 | * |
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| 14 | * Redistribution and use in source and binary forms, with or without |
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| 15 | * modification, are permitted provided that the following conditions |
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| 16 | * are met: |
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| 17 | * - Redistributions of source code must retain the above copyright |
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| 18 | * notice, this list of conditions and the following disclaimer. |
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| 19 | * - Redistributions in binary form must reproduce the above copyright |
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| 20 | * notice, this list of conditions and the following disclaimer in |
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| 21 | * the documentation and/or other materials provided with the |
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| 22 | * distribution. |
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| 23 | * - Neither the name of ARM LIMITED nor the names of its contributors |
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| 24 | * may be used to endorse or promote products derived from this |
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| 25 | * software without specific prior written permission. |
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| 26 | * |
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| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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| 30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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| 31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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| 33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 38 | * POSSIBILITY OF SUCH DAMAGE. |
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| 39 | * ---------------------------------------------------------------------------- */ |
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| 40 | |||
| 41 | #include "arm_math.h" |
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| 42 | |||
| 43 | /** |
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| 44 | * @addtogroup RMS |
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| 45 | * @{ |
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| 46 | */ |
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| 47 | |||
| 48 | |||
| 49 | /** |
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| 50 | * @brief Root Mean Square of the elements of a Q31 vector. |
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| 51 | * @param[in] *pSrc points to the input vector |
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| 52 | * @param[in] blockSize length of the input vector |
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| 53 | * @param[out] *pResult rms value returned here |
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| 54 | * @return none. |
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| 55 | * |
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| 56 | * @details |
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| 57 | * <b>Scaling and Overflow Behavior:</b> |
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| 58 | * |
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| 59 | *\par |
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| 60 | * The function is implemented using an internal 64-bit accumulator. |
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| 61 | * The input is represented in 1.31 format, and intermediate multiplication |
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| 62 | * yields a 2.62 format. |
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| 63 | * The accumulator maintains full precision of the intermediate multiplication results, |
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| 64 | * but provides only a single guard bit. |
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| 65 | * There is no saturation on intermediate additions. |
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| 66 | * If the accumulator overflows, it wraps around and distorts the result. |
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| 67 | * In order to avoid overflows completely, the input signal must be scaled down by |
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| 68 | * log2(blockSize) bits, as a total of blockSize additions are performed internally. |
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| 69 | * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. |
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| 70 | * |
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| 71 | */ |
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| 72 | |||
| 73 | void arm_rms_q31( |
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| 74 | q31_t * pSrc, |
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| 75 | uint32_t blockSize, |
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| 76 | q31_t * pResult) |
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| 77 | { |
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| 78 | q63_t sum = 0; /* accumulator */ |
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| 79 | q31_t in; /* Temporary variable to store the input */ |
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| 80 | uint32_t blkCnt; /* loop counter */ |
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| 81 | |||
| 82 | #ifndef ARM_MATH_CM0_FAMILY |
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| 83 | |||
| 84 | /* Run the below code for Cortex-M4 and Cortex-M3 */ |
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| 85 | |||
| 86 | q31_t in1, in2, in3, in4; /* Temporary input variables */ |
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| 87 | |||
| 88 | /*loop Unrolling */ |
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| 89 | blkCnt = blockSize >> 2u; |
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| 90 | |||
| 91 | /* First part of the processing with loop unrolling. Compute 8 outputs at a time. |
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| 92 | ** a second loop below computes the remaining 1 to 7 samples. */ |
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| 93 | while(blkCnt > 0u) |
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| 94 | { |
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| 95 | /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ |
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| 96 | /* Compute sum of the squares and then store the result in a temporary variable, sum */ |
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| 97 | /* read two samples from source buffer */ |
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| 98 | in1 = pSrc[0]; |
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| 99 | in2 = pSrc[1]; |
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| 100 | |||
| 101 | /* calculate power and accumulate to accumulator */ |
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| 102 | sum += (q63_t) in1 *in1; |
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| 103 | sum += (q63_t) in2 *in2; |
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| 104 | |||
| 105 | /* read two samples from source buffer */ |
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| 106 | in3 = pSrc[2]; |
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| 107 | in4 = pSrc[3]; |
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| 108 | |||
| 109 | /* calculate power and accumulate to accumulator */ |
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| 110 | sum += (q63_t) in3 *in3; |
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| 111 | sum += (q63_t) in4 *in4; |
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| 112 | |||
| 113 | |||
| 114 | /* update source buffer to process next samples */ |
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| 115 | pSrc += 4u; |
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| 116 | |||
| 117 | /* Decrement the loop counter */ |
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| 118 | blkCnt--; |
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| 119 | } |
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| 120 | |||
| 121 | /* If the blockSize is not a multiple of 8, compute any remaining output samples here. |
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| 122 | ** No loop unrolling is used. */ |
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| 123 | blkCnt = blockSize % 0x4u; |
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| 124 | |||
| 125 | #else |
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| 126 | |||
| 127 | /* Run the below code for Cortex-M0 */ |
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| 128 | blkCnt = blockSize; |
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| 129 | |||
| 130 | #endif /* #ifndef ARM_MATH_CM0_FAMILY */ |
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| 131 | |||
| 132 | while(blkCnt > 0u) |
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| 133 | { |
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| 134 | /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ |
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| 135 | /* Compute sum of the squares and then store the results in a temporary variable, sum */ |
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| 136 | in = *pSrc++; |
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| 137 | sum += (q63_t) in *in; |
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| 138 | |||
| 139 | /* Decrement the loop counter */ |
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| 140 | blkCnt--; |
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| 141 | } |
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| 142 | |||
| 143 | /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */ |
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| 144 | /* Compute Rms and store the result in the destination vector */ |
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| 145 | arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult); |
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| 146 | } |
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| 147 | |||
| 148 | /** |
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| 149 | * @} end of RMS group |
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| 150 | */ |