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| 2 | mjames | 1 | /* ---------------------------------------------------------------------- |
| 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
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| 3 | * |
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| 4 | * $Date: 19. March 2015 |
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| 5 | * $Revision: V.1.4.5 |
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| 6 | * |
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| 7 | * Project: CMSIS DSP Library |
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| 8 | * Title: arm_power_q31.c |
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| 9 | * |
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| 10 | * Description: Sum of the squares of the elements of a Q31 vector. |
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| 11 | * |
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| 12 | * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 |
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| 13 | * |
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| 14 | * Redistribution and use in source and binary forms, with or without |
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| 15 | * modification, are permitted provided that the following conditions |
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| 16 | * are met: |
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| 17 | * - Redistributions of source code must retain the above copyright |
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| 18 | * notice, this list of conditions and the following disclaimer. |
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| 19 | * - Redistributions in binary form must reproduce the above copyright |
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| 20 | * notice, this list of conditions and the following disclaimer in |
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| 21 | * the documentation and/or other materials provided with the |
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| 22 | * distribution. |
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| 23 | * - Neither the name of ARM LIMITED nor the names of its contributors |
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| 24 | * may be used to endorse or promote products derived from this |
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| 25 | * software without specific prior written permission. |
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| 26 | * |
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| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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| 30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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| 31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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| 33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 38 | * POSSIBILITY OF SUCH DAMAGE. |
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| 39 | * -------------------------------------------------------------------- */ |
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| 40 | |||
| 41 | #include "arm_math.h" |
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| 42 | |||
| 43 | /** |
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| 44 | * @ingroup groupStats |
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| 45 | */ |
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| 46 | |||
| 47 | /** |
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| 48 | * @addtogroup power |
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| 49 | * @{ |
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| 50 | */ |
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| 51 | |||
| 52 | /** |
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| 53 | * @brief Sum of the squares of the elements of a Q31 vector. |
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| 54 | * @param[in] *pSrc points to the input vector |
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| 55 | * @param[in] blockSize length of the input vector |
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| 56 | * @param[out] *pResult sum of the squares value returned here |
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| 57 | * @return none. |
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| 58 | * |
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| 59 | * @details |
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| 60 | * <b>Scaling and Overflow Behavior:</b> |
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| 61 | * |
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| 62 | * \par |
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| 63 | * The function is implemented using a 64-bit internal accumulator. |
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| 64 | * The input is represented in 1.31 format. |
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| 65 | * Intermediate multiplication yields a 2.62 format, and this |
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| 66 | * result is truncated to 2.48 format by discarding the lower 14 bits. |
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| 67 | * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. |
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| 68 | * With 15 guard bits in the accumulator, there is no risk of overflow, and the |
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| 69 | * full precision of the intermediate multiplication is preserved. |
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| 70 | * Finally, the return result is in 16.48 format. |
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| 71 | * |
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| 72 | */ |
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| 73 | |||
| 74 | void arm_power_q31( |
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| 75 | q31_t * pSrc, |
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| 76 | uint32_t blockSize, |
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| 77 | q63_t * pResult) |
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| 78 | { |
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| 79 | q63_t sum = 0; /* Temporary result storage */ |
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| 80 | q31_t in; |
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| 81 | uint32_t blkCnt; /* loop counter */ |
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| 82 | |||
| 83 | |||
| 84 | #ifndef ARM_MATH_CM0_FAMILY |
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| 85 | |||
| 86 | /* Run the below code for Cortex-M4 and Cortex-M3 */ |
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| 87 | |||
| 88 | /*loop Unrolling */ |
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| 89 | blkCnt = blockSize >> 2u; |
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| 90 | |||
| 91 | /* First part of the processing with loop unrolling. Compute 4 outputs at a time. |
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| 92 | ** a second loop below computes the remaining 1 to 3 samples. */ |
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| 93 | while(blkCnt > 0u) |
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| 94 | { |
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| 95 | /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ |
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| 96 | /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */ |
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| 97 | in = *pSrc++; |
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| 98 | sum += ((q63_t) in * in) >> 14u; |
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| 99 | |||
| 100 | in = *pSrc++; |
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| 101 | sum += ((q63_t) in * in) >> 14u; |
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| 102 | |||
| 103 | in = *pSrc++; |
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| 104 | sum += ((q63_t) in * in) >> 14u; |
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| 105 | |||
| 106 | in = *pSrc++; |
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| 107 | sum += ((q63_t) in * in) >> 14u; |
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| 108 | |||
| 109 | /* Decrement the loop counter */ |
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| 110 | blkCnt--; |
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| 111 | } |
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| 112 | |||
| 113 | /* If the blockSize is not a multiple of 4, compute any remaining output samples here. |
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| 114 | ** No loop unrolling is used. */ |
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| 115 | blkCnt = blockSize % 0x4u; |
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| 116 | |||
| 117 | #else |
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| 118 | |||
| 119 | /* Run the below code for Cortex-M0 */ |
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| 120 | |||
| 121 | /* Loop over blockSize number of values */ |
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| 122 | blkCnt = blockSize; |
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| 123 | |||
| 124 | #endif /* #ifndef ARM_MATH_CM0_FAMILY */ |
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| 125 | |||
| 126 | while(blkCnt > 0u) |
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| 127 | { |
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| 128 | /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ |
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| 129 | /* Compute Power and then store the result in a temporary variable, sum. */ |
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| 130 | in = *pSrc++; |
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| 131 | sum += ((q63_t) in * in) >> 14u; |
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| 132 | |||
| 133 | /* Decrement the loop counter */ |
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| 134 | blkCnt--; |
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| 135 | } |
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| 136 | |||
| 137 | /* Store the results in 16.48 format */ |
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| 138 | *pResult = sum; |
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| 139 | } |
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| 140 | |||
| 141 | /** |
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| 142 | * @} end of power group |
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| 143 | */ |