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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /* ---------------------------------------------------------------------- |
| 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
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| 3 | * |
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| 4 | * $Date: 19. March 2015 |
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| 5 | * $Revision: V.1.4.5 |
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| 6 | * |
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| 7 | * Project: CMSIS DSP Library |
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| 8 | * Title: arm_dot_prod_q7.c |
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| 9 | * |
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| 10 | * Description: Q7 dot product. |
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| 11 | * |
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| 12 | * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 |
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| 13 | * |
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| 14 | * Redistribution and use in source and binary forms, with or without |
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| 15 | * modification, are permitted provided that the following conditions |
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| 16 | * are met: |
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| 17 | * - Redistributions of source code must retain the above copyright |
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| 18 | * notice, this list of conditions and the following disclaimer. |
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| 19 | * - Redistributions in binary form must reproduce the above copyright |
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| 20 | * notice, this list of conditions and the following disclaimer in |
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| 21 | * the documentation and/or other materials provided with the |
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| 22 | * distribution. |
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| 23 | * - Neither the name of ARM LIMITED nor the names of its contributors |
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| 24 | * may be used to endorse or promote products derived from this |
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| 25 | * software without specific prior written permission. |
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| 26 | * |
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| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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| 30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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| 31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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| 33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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| 34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 38 | * POSSIBILITY OF SUCH DAMAGE. |
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| 39 | * -------------------------------------------------------------------- */ |
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| 40 | |||
| 41 | #include "arm_math.h" |
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| 42 | |||
| 43 | /** |
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| 44 | * @ingroup groupMath |
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| 45 | */ |
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| 46 | |||
| 47 | /** |
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| 48 | * @addtogroup dot_prod |
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| 49 | * @{ |
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| 50 | */ |
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| 51 | |||
| 52 | /** |
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| 53 | * @brief Dot product of Q7 vectors. |
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| 54 | * @param[in] *pSrcA points to the first input vector |
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| 55 | * @param[in] *pSrcB points to the second input vector |
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| 56 | * @param[in] blockSize number of samples in each vector |
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| 57 | * @param[out] *result output result returned here |
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| 58 | * @return none. |
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| 59 | * |
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| 60 | * <b>Scaling and Overflow Behavior:</b> |
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| 61 | * \par |
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| 62 | * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these |
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| 63 | * results are added to an accumulator in 18.14 format. |
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| 64 | * Nonsaturating additions are used and there is no danger of wrap around as long as |
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| 65 | * the vectors are less than 2^18 elements long. |
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| 66 | * The return result is in 18.14 format. |
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| 67 | */ |
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| 68 | |||
| 69 | void arm_dot_prod_q7( |
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| 70 | q7_t * pSrcA, |
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| 71 | q7_t * pSrcB, |
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| 72 | uint32_t blockSize, |
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| 73 | q31_t * result) |
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| 74 | { |
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| 75 | uint32_t blkCnt; /* loop counter */ |
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| 76 | |||
| 77 | q31_t sum = 0; /* Temporary variables to store output */ |
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| 78 | |||
| 79 | #ifndef ARM_MATH_CM0_FAMILY |
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| 80 | |||
| 81 | /* Run the below code for Cortex-M4 and Cortex-M3 */ |
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| 82 | |||
| 83 | q31_t input1, input2; /* Temporary variables to store input */ |
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| 84 | q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */ |
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| 85 | |||
| 86 | |||
| 87 | |||
| 88 | /*loop Unrolling */ |
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| 89 | blkCnt = blockSize >> 2u; |
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| 90 | |||
| 91 | /* First part of the processing with loop unrolling. Compute 4 outputs at a time. |
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| 92 | ** a second loop below computes the remaining 1 to 3 samples. */ |
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| 93 | while(blkCnt > 0u) |
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| 94 | { |
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| 95 | /* read 4 samples at a time from sourceA */ |
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| 96 | input1 = *__SIMD32(pSrcA)++; |
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| 97 | /* read 4 samples at a time from sourceB */ |
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| 98 | input2 = *__SIMD32(pSrcB)++; |
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| 99 | |||
| 100 | /* extract two q7_t samples to q15_t samples */ |
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| 101 | inA1 = __SXTB16(__ROR(input1, 8)); |
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| 102 | /* extract reminaing two samples */ |
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| 103 | inA2 = __SXTB16(input1); |
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| 104 | /* extract two q7_t samples to q15_t samples */ |
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| 105 | inB1 = __SXTB16(__ROR(input2, 8)); |
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| 106 | /* extract reminaing two samples */ |
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| 107 | inB2 = __SXTB16(input2); |
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| 108 | |||
| 109 | /* multiply and accumulate two samples at a time */ |
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| 110 | sum = __SMLAD(inA1, inB1, sum); |
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| 111 | sum = __SMLAD(inA2, inB2, sum); |
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| 112 | |||
| 113 | /* Decrement the loop counter */ |
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| 114 | blkCnt--; |
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| 115 | } |
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| 116 | |||
| 117 | /* If the blockSize is not a multiple of 4, compute any remaining output samples here. |
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| 118 | ** No loop unrolling is used. */ |
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| 119 | blkCnt = blockSize % 0x4u; |
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| 120 | |||
| 121 | while(blkCnt > 0u) |
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| 122 | { |
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| 123 | /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ |
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| 124 | /* Dot product and then store the results in a temporary buffer. */ |
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| 125 | sum = __SMLAD(*pSrcA++, *pSrcB++, sum); |
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| 126 | |||
| 127 | /* Decrement the loop counter */ |
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| 128 | blkCnt--; |
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| 129 | } |
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| 130 | |||
| 131 | #else |
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| 132 | |||
| 133 | /* Run the below code for Cortex-M0 */ |
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| 134 | |||
| 135 | |||
| 136 | |||
| 137 | /* Initialize blkCnt with number of samples */ |
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| 138 | blkCnt = blockSize; |
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| 139 | |||
| 140 | while(blkCnt > 0u) |
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| 141 | { |
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| 142 | /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ |
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| 143 | /* Dot product and then store the results in a temporary buffer. */ |
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| 144 | sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++); |
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| 145 | |||
| 146 | /* Decrement the loop counter */ |
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| 147 | blkCnt--; |
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| 148 | } |
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| 149 | |||
| 150 | #endif /* #ifndef ARM_MATH_CM0_FAMILY */ |
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| 151 | |||
| 152 | |||
| 153 | /* Store the result in the destination buffer in 18.14 format */ |
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| 154 | *result = sum; |
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| 155 | } |
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| 156 | |||
| 157 | /** |
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| 158 | * @} end of dot_prod group |
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| 159 | */ |